Coupler comprising a waveguide core with integrated air gap
By introducing an air gap structure and dielectric clamp into the waveguide core of the photonic chip, the problems of large area occupation and low efficiency of traditional couplers are solved, achieving more efficient optical coupling and reduced cost.
Patent Information
- Application Number
- CN202210600126.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2021-06-29
- Filing Date
- 2022-05-27
- Publication Date
- 2026-01-06
- Estimated Expiration
- 2042-05-27
AI Technical Summary
Traditional directional couplers and edge couplers occupy a large layout area on photonic chips and increase processing costs, and their optical coupling efficiency is insufficient.
Introducing an air gap structure into the waveguide core of a photonic chip, and improving optical coupling performance by forming a series of air gaps and dielectric clamps in the waveguide core, including setting air gaps in the coupling region and using dielectric materials for mode modulation.
This reduces the length and spacing requirements of the waveguide core, improves optical coupling efficiency, reduces chip size and cost, and enhances the performance of the optical coupler.
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Figure CN115542457B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to photonic chips, and more particularly to structures for couplers and methods for forming structures for couplers. Background Technology
[0002] Photonic chips are used in many applications and systems, such as data communication and computing systems. Photonic chips integrate optical components (such as waveguides, optical switches, optical power splitters, edge couplers, and directional couplers) with electronic components (such as field-effect transistors) on a unified platform. Among other factors, layout area, cost, and operational overhead can be reduced by integrating two types of components on the same chip.
[0003] Directional couplers are employed on photonic chips to distribute propagating optical signals between different waveguide cores. The directional coupler comprises segments of the different waveguide cores, routed with a reduced lateral spacing selected to facilitate optical coupling over a given coupling length. Conventional directional couplers have a large footprint because a large coupling length and / or tight spacing are required to compensate for insufficient coupling strength between the waveguide core segments. These limitations can lead to increased chip size and increased processing costs.
[0004] Edge couplers (also known as spot-size couplers) are typically used to couple optical signals of a given mode from an optical fiber or laser to optical components on a photonic chip. An edge coupler may include a segment of waveguide core defined as an inverse taper. Corresponding to the direction of mode propagation, an inverse taper is a tapered segment of the waveguide core characterized by a gradually increasing width along the mode propagation direction. As light is transmitted from the optical fiber or laser to the photonic chip, the gradually increasing cross-sectional area of the inverse taper supports mode transformation and the associated mode size variation.
[0005] The need is for improvements to the structure of the coupler and the methods for forming the structure of the coupler. Summary of the Invention
[0006] In one embodiment of the present invention, a structure for a directional coupler is provided. The structure includes a first waveguide core having one or more first air gaps, and a second waveguide core including one or more second air gaps. The one or more second air gaps are disposed in the second waveguide core adjacent to the one or more first air gaps in the first waveguide core.
[0007] In one embodiment of the invention, a structure for an edge coupler is provided. The structure includes an intermediate component, an optical assembly, and a waveguide core disposed between the intermediate component and the optical assembly. The waveguide core includes one or more air gaps.
[0008] In one embodiment of the present invention, a method for forming a directional coupler is provided. The method includes forming a first waveguide core and a second waveguide core, forming one or more first air gaps in the first waveguide core, and forming one or more second air gaps in the second waveguide core. The one or more second air gaps are disposed in the second waveguide core adjacent to the one or more first air gaps in the first waveguide core. Attached Figure Description
[0009] The accompanying drawings, which are included and constitute a part of this specification, illustrate various embodiments of the invention and, together with the foregoing general description of the invention and the following detailed description of these embodiments, serve to explain these embodiments of the invention. In these drawings, similar reference numerals denote similar features in different views.
[0010] Figure 1 A top view showing a structure in the initial manufacturing stage of a processing method according to an embodiment of the present invention.
[0011] Figure 2 Showing the general outline Figure 1 The sectional view made by line 2-2 in the diagram.
[0012] Figure 2A Showing the general outline Figure 1 The sectional view is drawn along line 2A-2A in the diagram.
[0013] Figure 2B Showing the general outline Figure 1 The sectional view is drawn along line 2B-2B.
[0014] Figure 3 Display in Figure 1 A top view of the structure during the manufacturing stage of this processing method.
[0015] Figure 4 Showing the general outline Figure 3 The sectional view made along line 4-4 in the diagram.
[0016] Figure 4A Showing the general outline Figure 3 The sectional view is drawn along line 4A-4A.
[0017] Figure 4B Showing the general outline Figure 3 The sectional view is drawn along line 4B-4B.
[0018] Figure 5 , Figure 5A , Figure 5B Display in Figure 4 , Figure 4A , Figure 4B A cross-sectional view of the structure during the manufacturing stage of this processing method.
[0019] Figure 6 , Figure 6A , Figure 6B Display in Figure 5 , Figure 5A , Figure 5B A cross-sectional view of the structure during the manufacturing stage of this processing method.
[0020] Figure 7 , Figure 7A A cross-sectional view showing a structure according to an alternative embodiment of the present invention.
[0021] Figure 8 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.
[0022] Figure 9 A top view showing a structure according to an alternative embodiment of the present invention.
[0023] Figure 9A Showing the general outline Figure 9 The sectional view is drawn along line 9A-9A.
[0024] Figure 9B Showing the general outline Figure 9 The sectional view is drawn along line 9B-9B.
[0025] Figure 10 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.
[0026] Figure 11 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.
[0027] Figure 11A Showing the general outline Figure 11 The sectional view is drawn along line 11A-11A.
[0028] Figure 12 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.
[0029] Figure 12AShowing the general outline Figure 12 The sectional view is drawn along line 12A-12A. Detailed Implementation
[0030] Please refer to Figure 1 , Figure 2 , Figure 2A , Figure 2B According to an embodiment of the present invention, the structure 10 for an optocoupler includes waveguide core 12 and waveguide core 14. Waveguide cores 12 and 14 may be disposed on a dielectric layer 16. In one embodiment, waveguide cores 12 and 14 may be composed of a semiconductor material, such as single-crystal silicon. In one embodiment, the semiconductor material may be derived from a device layer of a silicon-on-insulator (SOI) substrate, which further includes a buried oxide layer providing the dielectric layer 16, and a substrate 25 composed of a semiconductor material such as single-crystal silicon. Waveguide cores 12 and 14 may be formed by patterning the device layer using photolithography and etching processes during front-end-of-line processing. The device layer of the silicon-on-insulator wafer may be fully etched to define a ridge waveguide (as shown), or, alternatively, only partially etched near waveguide cores 12 and 14 to define a rib waveguide.
[0031] Structure 10 has a coupling region 18, wherein a segment 20 of waveguide core 12 extends longitudinally along the longitudinal axis 13, and a segment 21 of waveguide core 14 extends longitudinally along the longitudinal axis 15. The segments 20 of waveguide core 12 and adjacent segments 21 of waveguide core 14 are arranged adjacent to each other in the coupling region 18. In the coupling region 18, the longitudinal axis 13 of the segment 20 of waveguide core 12 located in the coupling region 18 may be arranged parallel to the longitudinal axis 15 of the adjacent segment 21 of waveguide core 14.
[0032] The waveguide core 12 also includes a set of curved segments 22 located in the input region 17 of the structure 10 and a set of curved segments 24 located in the output region 19 of the structure 10. Segments 20 are longitudinally disposed between the curved segments 22 and 24, with one end of the curved segment 22 adjacent to the other end of the curved segment 20 and the other end of the curved segment 24 adjacent to the opposite end of the curved segment 20. The curved segments 22 may be bent in opposite directions to route the waveguide core 12 in the input region 17. The curved segments 24 may be bent in opposite directions to route the waveguide core 12 in the output region 19. In an alternative embodiment, the segments 20 may be tapered instead of straight.
[0033] The waveguide core 14 also includes a set of curved segments 26 located in the input region 17 of the structure 10 and a set of curved segments 28 located in the output region 19 of the structure 10. A segment 21 is longitudinally disposed between the curved segments 26 and 28, with the curved segment 26 adjacent to one end of the segment 20 and the curved segment 28 adjacent to the opposite end of the segment 21. The curved segments 26 may be bent in opposite directions to route the waveguide core 14 in the input region 17. The curved segments 28 may be bent in opposite directions to route the waveguide core 14 in the output region 19. In an alternative embodiment, the segment 21 may be tapered instead of straight.
[0034] Waveguide core 12 has a top surface 38, and waveguide core 14 has a top surface 40 that is coplanar with the top surface 38. Waveguide core 12 has sidewalls in the form of opposing side surfaces 32, 33 that project upward from dielectric layer 16 to the top surface 38, and waveguide core 14 has sidewalls in the form of opposing side surfaces 34, 35 that project upward from dielectric layer 16 to the top surface 40. In coupling region 18, the side surface 32 of segment 20 of waveguide core 12 is arranged adjacent to the side surface 34 of segment 21 of waveguide core 14 along a length L. In one embodiment, the width of segments 20, 21 may be constant along their respective lengths.
[0035] The distance by which segment 20 of waveguide core 12 is laterally separated from segment 21 of waveguide core 14 in coupling region 18 is less than the distance by which waveguide cores 12 and 14 are separated outside coupling region 18. In this respect, the side surface 32 of segment 20 of waveguide core 12 may be arranged adjacent to and parallel to the side surface 34 of segment 21 of waveguide core 14 along length L within coupling region 18, and the side surfaces 32 and 34 may be separated by a gap G in coupling region 18, which may be consistent within coupling region 18.
[0036] Outside coupling region 18, the side surface 32 of waveguide core 12 is diverged from the side surface 34 of waveguide core 14, and the side surfaces 32 and 34 can be separated by a corresponding gap greater than gap G in input region 17 and output region 19. The set of curved segments 22 and 26 in input region 17 and the set of curved segments 24 and 28 in output region 19 help provide variation in the spacing between the side surfaces 32 and 34 of waveguide core 12 and waveguide core 14. Due to the large distance between the side surfaces 32 and 34 in input region 17 and output region 19, optical coupling between waveguide cores 12 and 14 is negligible outside coupling region 18.
[0037] Please refer to Figure 3 , Figure 4 , Figure 4A , Figure 4B In which similar reference numerals indicate Figure 1 , Figure 2 , Figure 2A , Figure 2B Similar features are incorporated, and in the next manufacturing stage, openings 42 are formed in waveguide core 12 and openings 44 are formed in waveguide core 14. Openings 42 may be arranged in a row in waveguide core 12, and openings 44 may be arranged in a row in waveguide core 14. To pattern the openings 42 and 44, photolithography and etching processes can be performed using an etching mask and a directional etching process, such as reactive ion etching (RIE), to form openings 42 and 44 at the positions of the corresponding openings in the etching mask. Dielectric collars 46 may be formed inside each opening 42 and 44. The dielectric collars 46 may be composed of, for example, silicon dioxide.
[0038] Cavities 52 are formed as inclusions in waveguide core 12, extending outward from the bottom of opening 42, and cavities 54 are formed as inclusions in waveguide core 14, extending outward from the bottom of opening 44. Cavities 52 and 54 can be formed by performing an isotropic etching process and can be merged together by this process. A dielectric hoop 46 masks openings 42 and 44, thereby preventing expansion during isotropic etching. In one embodiment, cavities 52 may not be merged and are distributed at corresponding positions in a row extending along the longitudinal axis 13 of segment 20 of waveguide core 12. In one embodiment, cavities 54 may not be merged and are distributed at corresponding positions in a row extending along the longitudinal axis 15 of segment 21 of waveguide core 14. Due to this isotropic etching, cavities 52 can be symmetrical about opening 42, and cavities 54 can be symmetrical about opening 44.
[0039] An opening 42 is disposed between the cavity 52 and the top surface 38 of the waveguide core 12. Similarly, an opening 44 is disposed between the cavity 54 and the top surface 40 of the waveguide core 14. The openings 42 and 44 are then plugged to seal the cavities 52 and 54.
[0040] Please refer to Figure 5 , Figure 5A , Figure 5B In which similar reference numerals indicate Figure 3 , Figure 4 , Figure 4A , Figure 4BSimilar features are present in the next manufacturing stage of this process, where plugs 56 are formed inside openings 42, 44 to seal cavities 52, 54, and epitaxial layers 58 can be epitaxially grown on the top surfaces 38, 40 of waveguide cores 12, 14. Epitaxial layers 58 may be composed of silicon. Plugs 56 may include a thin silicon-germanium layer epitaxially grown as a liner on the surface of waveguide cores 12, 14 bordering openings 42, 44 and silicon from epitaxial layer 58. Epitaxial layer 58 can be formed using a low-temperature epitaxial growth process, such as vapor phase epitaxy. This epitaxial growth allows the previously deposited thin silicon-germanium layer to be reflowed and bonded to the semiconductor material of epitaxial layer 58 to form plugs 56 inside openings 42, 44.
[0041] Uncombined and discrete sealed cavities 52 define multiple air gaps in waveguide core 12, and uncombined and discrete sealed cavities 54 define multiple air gaps in waveguide core 14. The air gaps defined by sealed cavity 52 and sealed cavity 54 can be characterized by a dielectric constant close to one (i.e., the vacuum dielectric constant). The air gaps defined by sealed cavity 52 and sealed cavity 54 can be filled with gas, such as atmospheric pressure or near atmospheric pressure.
[0042] Please refer to Figure 6 , Figure 6A , Figure 6B In which similar reference numerals indicate Figure 5 , Figure 5A , Figure 5B Similar features are present in the layer stack above waveguide cores 12 and 14, and additional dielectric layers 60, 62, 64, and 66 can be formed in the next manufacturing stage. Dielectric layer 60 (which may be composed of silicon dioxide) may be planarized to be coplanar with the top surface of waveguide cores 12 and 14 and provide lateral coverage. Dielectric layer 64 may be composed of silicon nitride, and dielectric layers 62 and 66 may be composed of silicon dioxide. In an alternative embodiment, the silicon nitride-containing dielectric layer 64 may be omitted from the layer stack. A back-end process stack 68 may be formed above dielectric layer 66 by back-end process processing. The back-end process stack 68 may include one or more dielectric layers composed of dielectric materials such as silicon dioxide, silicon nitride, or low-k dielectric materials.
[0043] The dielectric material surrounding the dielectric layers 16, 60, and 62 of waveguide cores 12 and 14 is provided with a low refractive index cladding to provide refractive index contrast. Dielectric layers 16, 60, and 62 have no cavities or voids (filled or unfilled) near the waveguide cores 12 and 14.
[0044] In any embodiment of structure 10 described herein, structure 10 may be integrated into a photonic chip, which may include electronic components and additional optical components. The electronic components may include, for example, field-effect transistors, which are fabricated using a device layer on a silicon-on-insulator substrate via CMOS processing.
[0045] During use, laser light can be guided to structure 10 on the photonic chip via waveguide core 22. The laser light is laterally transmitted within coupling region 18 via evanescent coupling from waveguide core 12 to waveguide core 14. In one embodiment, the coupling ratio may be approximately 50:50, such that approximately half of the laser light is laterally transmitted from waveguide core 12 to waveguide core 14. The air gap provided by sealing cavities 52 and 54 can be used to improve the optical coupling performance of structure 10, allowing for a shorter length L of segments 20 and 21 of waveguide cores 12 and 14 and / or an increased dimension of the gap G between waveguide cores 12 and 14. Sealing cavities 52 and 54 can relax the refractive index contrast, modify the mode distribution, and promote optical interactions, resulting in improved optical coupling performance.
[0046] Please refer to Figure 7 , Figure 7A In which similar reference numerals indicate Figure 5 , Figure 5A Similar features, and according to an alternative embodiment of the invention, cavities 52 in waveguide core 12 may be merged and combined to define a single air gap sealed by a plurality of plugs 56 in waveguide core 12, rather than multiple air gaps individually sealed by a single plug 56. Similarly, cavities 54 in waveguide core 14 may be merged and combined to define a single air gap sealed by a plurality of plugs 56 in waveguide core 14, rather than multiple air gaps individually sealed by a single plug 56. In one embodiment, the spacing of the openings 42 in waveguide core 12 and the spacing of the openings 44 in waveguide core 14 may be reduced, thereby facilitating the merging of cavities 52, 54 during the isotropic etching process due to the reduced spacing. The sealed single air gap provided by the merged cavity 52 extends longitudinally along the longitudinal axis 13 of waveguide core 12, and similarly, the sealed single air gap provided by the merged cavity 54 extends longitudinally along the longitudinal axis 15 of waveguide core 14.
[0047] Please refer to Figure 8According to an alternative embodiment of the invention, a solid material layer 53 may be formed to line cavities 52, 54 before sealing by forming plug 56, thereby allowing each cavity 52, 54 to contain a combination of the solid material and air or gas. This composite filling of cavities 52, 54 allows for further mode adjustment by specifying the material and thickness of layer 53. In one embodiment, the composition of the material in layer 53 may differ from the composition of the waveguide cores 12, 14. For example, for waveguide cores 12, 14 made of silicon, the material in layer 53 may include silicon nitride or silicon dioxide. Cavities 52, 54 coated by layer 53 may not be merged (e.g., Figure 5 , Figure 5A (as shown), or, as an alternative, can be merged (such as...) Figure 7 , Figure 7A (As shown in the diagram) to define a single air gap for sealing.
[0048] Please refer to Figure 9 , Figure 9A , Figure 9B According to an alternative embodiment of the invention, openings 42 may also be formed in one or both of the curved sections 22 of the waveguide core 12, and openings 42 may also be formed in one or both of the curved sections 24 of the waveguide core 12. The openings 42 are connected to cavities 52 in the curved sections 22. Subsequently, the cavities 52 are plugged and sealed by plugs 56. In an alternative embodiment, openings 42 and cavities 52 may be formed only in one or both of the curved sections 22. In an alternative embodiment, openings 42 and cavities 52 may be formed only in one or both of the curved sections 24. The cavities 52 located in the curved sections 22 and / or curved sections 24 may not be merged (e.g., Figure 5 (as shown), and define multiple air gaps after sealing. Alternatively, cavities 52 located in curved sections 22 and / or curved sections 24 can be combined (e.g. Figure 7 (as shown), and merged with the merged cavity 52 in section 20 to define a single air gap after sealing.
[0049] Similarly, openings 44 may be formed in one or both of the bends 26 of the waveguide core 14, and openings 44 may also be formed in one or both of the bends 28 of the waveguide core 14. The openings 44 are connected to cavities 54. The cavities 54 are then plugged and sealed by plugs 56. In an alternative embodiment, openings 44 and cavities 54 may be formed only in one or both of the bends 26. In an alternative embodiment, openings 44 and cavities 54 may be formed only in one or both of the bends 28. The cavities 54 located in the bends 26 and / or bends 28 may not be merged (e.g., Figure 5A(as shown in the diagram), and define multiple air gaps after sealing. Alternatively, cavities 54 located in curved sections 26 and / or curved sections 28 can be combined (as shown in the diagram). Figure 7A (as shown in the diagram), and merged with the merged cavity 54 in section 21 to define a single air gap after sealing.
[0050] In addition to arranging the cavity 52 in section 20, arranging the cavity 52 in curved sections 22 and / or curved sections 24 can extend the coupling region 18 beyond sections 20 and 21, and partially extend into curved sections 22 and 24 and / or curved sections 26 and 28.
[0051] Please refer to Figure 10 According to alternative embodiments of the invention, the waveguide core 14 having cavity 54 can be deployed in different types of structures 10a, such as edge couplers (i.e., spot size converters), wherein the waveguide core 14 is optically coupled to an optical fiber or laser via an intermediary 78, and the waveguide core 14 guides light from the optical fiber or laser to an optical component, such as a photodetector 70. Cavity 54 can be used to enhance field confinement and reduce propagation loss, thereby enhancing the performance of the edge coupler. Cavity 54 can be non-merged and discrete to define multiple air gaps. In an alternative embodiment, cavity 54 can be merged (e.g., Figure 7A (As shown in the figure) to define a single air gap.
[0052] Please refer to Figure 11 , Figure 11A In which similar reference numerals indicate Figure 10 Similar features to those in the original invention, and according to an alternative embodiment of the invention, dielectric layer 16 may be replaced by a set of cavities 72 similar to cavity 54, formed in a manner similar to the formation of cavity 54 in the bulk substrate 74. In one embodiment, bulk substrate 74 may be a silicon substrate. Each cavity 72 may be sealed by a plug 76, similar to the plug 56 used to seal each cavity 54. In one embodiment, cavities 72 may be combined to provide a single air gap. In one embodiment, cavities 72 may be arranged in multiple rows and columns, and the multiple rows and columns of cavities 72 may be combined to provide the single air gap. Waveguide core 14 may be formed over bulk substrate 74 and over cavities 72 by a self-planarization epitaxial process. Cavities 72 provide an optical isolation layer for waveguide core 14, which behaves similarly to the replaced dielectric layer 16 during use.
[0053] Please refer to Figure 12 , Figure 12A In which similar reference numerals indicate Figure 11ASimilar features to those in the present invention, and according to an alternative embodiment of the invention, the waveguide core 14 may be modified to include cavities 54 arranged in side-by-side rows 48, 50. The cavities 54 in each row 48, 50 may be distributed along the longitudinal axis 15 without being merged. The solid material of the waveguide core 14 separates the rows 48 and 50 of the cavities 54. In one embodiment, the cavities 54 in each row 48, 50 may not be merged (e.g., Figure 5A As shown in the diagram, multiple air gaps are defined. In one embodiment, cavities 54 located in rows 48, 50 can be merged (as shown in the diagram). Figure 7A (As shown in the diagram) to define a single air gap. Due to the multiple rows 48, 50 of the cavity 54, the waveguide core 14 can function in a manner similar to a slotted waveguide core.
[0054] The method described above is used for the manufacture of integrated circuit chips. Manufacturers can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as bare chips, or in packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product. The final product can be any product including the integrated circuit chip, such as a computer product with a central processing unit or a smartphone.
[0055] The terms used herein, modified by approximate language such as “approximately,” “roughly,” and “substantially,” are not limited to the specified precise values. This approximate language may correspond to the accuracy of the instrument used to measure the value, and may represent + / - 10% of the value unless otherwise dependent on the accuracy of that instrument.
[0056] The terms "vertical" and "horizontal" are used in this document as examples to establish a reference framework and are not intended to be limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the layers defined above. The term "lateral" refers to a direction within this horizontal plane.
[0057] A feature "connected" or "coupled" to another feature may be directly connected or coupled to that other feature, or one or more intermediate features may exist. If no intermediate features exist, the feature may be "directly connected" or "directly coupled" to the other feature. If at least one intermediate feature exists, the feature may be "indirectly connected" or "indirectly coupled" to the other feature. A feature "on" or "in contact" with another feature may be directly on or in direct contact with that other feature, or one or more intermediate features may exist. If no intermediate features exist, the feature may be directly "on" or in direct contact with the other feature. If at least one intermediate feature exists, the feature may not be "directly" on or in direct contact with the other feature. If a feature extends over and covers a portion of another feature in a manner that is either directly or indirectly in contact with it, the different features may "overlap".
[0058] The descriptions of various embodiments of the invention are for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements upon technical techniques known in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.
Claims
1. A structure for a directional coupler, characterized by, The structure comprises: a first waveguide core including one or more first air gaps, a first top surface, a plurality of first openings arranged between the first top surface and the one or more first air gaps, and a first dielectric post inside each of the plurality of first openings, and each of the one or more first air gaps extends outwardly from a respective bottom of the plurality of first openings; a second waveguide core including one or more second air gaps disposed in the second waveguide core adjacent to the one or more first air gaps in the first waveguide core; and a dielectric layer including a dielectric material, wherein the first waveguide core and the second waveguide core are disposed on the dielectric layer.
2. The structure of claim 1, wherein The first waveguide core includes a first section and a second section adjacent to the first section, the second section of the first waveguide core is curved, and the one or more first air gaps are disposed in the first section and the second section of the first waveguide core.
3. The structure of claim 2, wherein The second waveguide core includes a first section and a second section adjacent to the first section, the first section of the first waveguide core is disposed adjacent to the first section of the second waveguide core, the second section of the second waveguide core is curved, and the one or more second air gaps are disposed in the first section and the second section of the second waveguide core.
4. The structure of claim 1, wherein The first waveguide core includes a first longitudinal axis, and the one or more first air gaps include a plurality of first air gaps distributed along the first longitudinal axis.
5. The structure of claim 4, wherein The second waveguide core includes a second longitudinal axis, and the one or more second air gaps include a plurality of second air gaps distributed along the second longitudinal axis.
6. The structure of claim 1, wherein The one or more first air gaps is a single first air gap, the first waveguide core includes a first longitudinal axis, and the single first air gap extends longitudinally along the first longitudinal axis.
7. The structure of claim 6, wherein The one or more second air gaps is a single second air gap, the second waveguide core includes a second longitudinal axis, and the single second air gap extends longitudinally along the second longitudinal axis.
8. The structure of claim 1, further comprising: a plurality of plugs formed inside the plurality of first openings to enclose and seal the one or more first air gaps.
9. The structure of claim 1, wherein The first waveguide core and the second waveguide core include a first material, the one or more first air gaps and the one or more second air gaps contain a gas, and the structure includes: a layer lining the one or more first air gaps and the one or more second air gaps, the layer including a second material different from the first material.
10. The structure of claim 1, wherein The second waveguide core includes a second top surface, a plurality of second openings arranged between the second top surface and the one or more second air gaps, and a second dielectric post inside each of the plurality of second openings, and each of the one or more second air gaps extends outwardly from a respective bottom of the plurality of second openings.
11. The structure of claim 1, wherein The first waveguide core includes a first sidewall and a second sidewall opposite to the first sidewall, the first sidewall and the second sidewall protrude upwardly from the dielectric layer to the first top surface, and the one or more first air gaps are disposed between the first sidewall and the second sidewall.
12. A structure for an edge coupler, characterized by The structure comprises: an intermediate piece; an optical assembly; a waveguide core disposed between the intermediate piece and the optical component, the waveguide core comprising one or more first air gaps, a top surface, a plurality of openings disposed between the top surface and the one or more first air gaps, and a dielectric post inside each of the plurality of openings, and each of the one or more first air gaps extending outwardly from a respective bottom of the plurality of openings; and a dielectric layer comprising a dielectric material, wherein the waveguide core is disposed on the dielectric layer.
13. The structure of claim 12, wherein The waveguide core comprises a longitudinal axis, and the one or more first air gaps comprise a plurality of first air gaps distributed in a first row along the longitudinal axis.
14. The structure of claim 13, wherein Also comprising: one or more second air gaps disposed in the waveguide core adjacent to the one or more first air gaps, wherein the one or more second air gaps comprise a plurality of second air gaps distributed in a second row along the longitudinal axis.
15. The structure of claim 12, wherein The one or more first air gaps is a single air gap, the waveguide core comprises a longitudinal axis, and the single air gap extends longitudinally along the longitudinal axis.
16. The structure of claim 12, wherein Also comprising: a bulk semiconductor substrate; and a third air gap in the bulk semiconductor substrate, wherein the waveguide core is disposed on the bulk semiconductor substrate above the third air gap.
17. The structure of claim 12, wherein The optical component is a photodetector.
18. A method of forming a directional coupler, characterized by, The method comprises: forming a first waveguide core and a second waveguide core disposed on a dielectric layer; forming a plurality of openings on the first waveguide core; forming a dielectric post disposed inside each of the plurality of openings; forming one or more first air gaps in the first waveguide core, wherein the plurality of openings are disposed between a top surface of the first waveguide core and the one or more air gaps, and each of the one or more first air gaps extends outwardly from a respective bottom of the plurality of openings; and forming one or more second air gaps in the second waveguide core, wherein the one or more second air gaps are disposed in the second waveguide core adjacent to the one or more first air gaps in the first waveguide core.
19. The method of claim 18, wherein, The first waveguide core and the second waveguide core comprise a first material, the one or more first air gaps and the one or more second air gaps are filled with a gas, and the method further comprises: forming a layer lining the one or more first air gaps and the one or more second air gaps, wherein the layer comprises a second material different from the first material.
20. The method of claim 18, wherein, The one or more first air gaps and the one or more second air gaps are formed simultaneously. The waveguide core comprises a longitudinal axis, and the one or more first air gaps comprise a plurality of first air gaps distributed in a first row along the longitudinal axis. Also comprising: one or more second air gaps disposed in the waveguide core adjacent to the one or more first air gaps, wherein the one or more second air gaps comprise a plurality of second air gaps distributed in a second row along the longitudinal axis. The one or more first air gaps is a single air gap, the waveguide core comprises a longitudinal axis, and the single air gap extends longitudinally along the longitudinal axis. Also comprising: a bulk semiconductor substrate; and a third air gap in the bulk semiconductor substrate, wherein the waveguide core is disposed on the bulk semiconductor substrate above the third air gap. The optical component is a photodetector. The method comprises: forming a first waveguide core and a second waveguide core disposed on a dielectric layer; forming a plurality of openings on the first waveguide core; forming a dielectric post disposed inside each of the plurality of openings; forming one or more first air gaps in the first waveguide core, wherein the plurality of openings are disposed between a top surface of the first waveguide core and the one or more air gaps, and each of the one or more first air gaps extends outwardly from a respective bottom of the plurality of openings; and forming one or more second air gaps in the second waveguide core, wherein the one or more second air gaps are disposed in the second waveguide core adjacent to the one or more first air gaps in the first waveguide core. The first waveguide core and the second waveguide core comprise a first material, the one or more first air gaps and the one or more second air gaps are filled with a gas, and the method further comprises: forming a layer lining the one or more first air gaps and the one or more second air gaps, wherein the layer comprises a second material different from the first material. The one or more first air gaps and the one or more second air gaps are formed simultaneously.
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