Low power consumption and high power supply rejection ratio LDO circuit and algorithm with sampling load current technology

Abstract

The present invention relates to a low-power high-power supply rejection ratio LDO circuit and algorithm with a sampling load current technology. The output current dynamic sampling circuit in the circuit is connected to the dynamic bias input end of the error amplifier; the inverting input of the error amplifier is connected to the reference voltage source V REF is connected, the output end of the error amplifier is connected to the control ends of the regulating transistor and the sampling transistor, and the regulating transistor is connected to the non-inverting input end of the error amplifier through a resistor feedback circuit; the input end of the regulating transistor is connected to the power supply, and the common end of the regulating transistor and the resistor feedback circuit is used as the output end of the low-dropout linear regulator circuit; the error amplifier compares the feedback voltage V FB output by the resistor feedback circuit with the reference voltage V REF to generate an error signal, and adjusts the regulating transistor by amplifying the error signal; the load current is sampled and fed back to the bias current distribution circuit of the error amplifier to increase the gain of the error amplifier in the medium and high frequencies and also increase the bandwidth of the error amplifier.

Description

Technical Field

[0001] The invention belongs to the technical field of voltage stabilizers, and particularly relates to a low-power consumption and high power supply rejection ratio LDO circuit and algorithm with a sampling load current technology. Background Art

[0002] Low-dropout linear regulators have the advantages of low output noise, simple circuit structure, small chip area and small voltage ripple, and have become an important circuit in power management chips. Especially in mobile devices, the ultra-low static power consumption of low-dropout linear regulators is more advantageous. Ultra-low static power consumption can extend the battery life and life. Therefore, low power consumption design has also become a key indicator in the design of low-dropout linear regulators. However, low static current will affect other parameters of low-dropout linear regulators, such as load transient response, power supply rejection ratio (PSRR), output noise, etc.

[0003] Among them, low static power consumption and power supply rejection ratio (PSRR) are the key performance indicators of linear regulators. The power supply rejection ratio often depends on the accuracy of the bandgap reference and the open-loop gain of the error amplifier loop of the linear regulator. Usually, in order to obtain a higher power supply rejection ratio, the linear regulator adopts a larger error amplifier open-loop gain or increases the coupling capacitor at the output. The use of a larger error amplifier open-loop gain, such as a multi-stage operational amplifier, will not only increase the power consumption and area of ​​the chip, but also bring greater challenges to circuit design. Increasing the coupling capacitor at the output will increase the area of ​​the chip and increase the production cost. At the same time, this approach will lead to a reduction in the bandwidth of the linear regulator, so a higher power supply rejection ratio cannot be obtained in the medium and high frequency bands.

[0004] As users' requirements for power supply ripple suppression capability increase, low-power, high power supply rejection ratio linear regulators are required to have a good power supply rejection ratio of 60dB at 100kHz. This is also a challenge for low-power circuit design, because if the quiescent current of the circuit is low, the bandwidth of the entire system will be reduced, and the power supply rejection ratio in the high frequency band will also be limited.

[0005] In the requirements of low power consumption and low cost, the LDO power supply rejection ratio curve using a conventional error amplifier is as follows Figure 3 As shown in Curve 1, it decreases at a rate of 20dB / 10dec at a relatively low frequency point. Under the constraints of the contradiction between open-loop gain and bandwidth, the power supply rejection ratio of the LDO circuit in the high frequency band is not ideal.

[0006] According to relevant theories, the bandwidth of the error amplifier is proportional to the gm value of the input pair, and gm increases as the current flowing through the input pair increases. By utilizing the load current sampling feedback technology, a dynamic bias current can be injected into the error amplifier without increasing the static power consumption, and the gm of the input pair can be dynamically increased when the LDO is loaded. However, the current design method is to directly inject the sampled bias current into the bias circuit of the error amplifier. Although this dynamic current injection method increases the bias current of the input pair and partially increases the gm of the differential input pair, widening the bandwidth of the error amplifier, it also increases the bias current flowing through the load circuit, and correspondingly significantly reduces the output resistance of the error amplifier. According to the gain formula of the error amplifier Av=gm*Rout, the gain of the error amplifier is also reduced accordingly, resulting in a decrease in the power supply rejection ratio of the LDO at low frequencies, such as Figure 3 As shown in curve 2, Figure 3 By comparing the first curve, we can find that: although the power supply rejection ratio in the high frequency band is improved due to the increase in bandwidth, the power supply rejection ratio in the medium and low frequencies is also significantly reduced due to the decrease in DC gain. This design method does not have a significant effect on improving the power supply rejection ratio. Summary of the invention

[0007] In order to solve the low power consumption and high power supply rejection ratio indicators of low-dropout linear regulators, the purpose of the present invention is to provide a bias circuit that samples the load current and feeds it back to the error amplifier, adopts a new bias current distribution circuit, and improves the gain of the medium and high frequency error amplifier while also increasing the error amplifier bandwidth. The low power consumption and high power supply rejection ratio LDO circuit and algorithm with sampling load current technology. Another purpose of the present invention is to provide a low power consumption and high power supply rejection ratio LDO circuit and algorithm with sampling load current technology, which samples the output current, feeds the sampled current back to the error amplifier, and adopts a new bias current distribution circuit to superimpose with the fixed bias current of the error amplifier to increase the bandwidth of the error amplifier, improve the high frequency gain of the error amplifier, and maintain low cost, while achieving a high power supply rejection ratio in the high frequency band. Another purpose of the present invention is to provide a low power consumption and high power supply rejection ratio LDO circuit and algorithm with sampling load current technology, which samples the output current to perform high-efficiency dynamic bias on the error amplifier, improves the power supply rejection ratio in the high frequency band, and maintains ultra-low power consumption under no-load conditions, so as to achieve ultra-low static power consumption and high power supply rejection ratio of a low-dropout linear regulator.

[0008] The technical solution of the present invention is the low-power consumption and high power supply rejection ratio LDO circuit with sampling load current technology, which is special in that it includes: an error amplifier with dynamic current bias, an adjustment tube MP, a resistor feedback circuit, a reference circuit, and an output current dynamic sampling circuit: the output current dynamic sampling circuit is connected to the dynamic bias input end of the error amplifier; the inverting input of the error amplifier is connected to the reference voltage source VREF, the output end of the error amplifier is connected to the control end of the adjustment tube MP and the sampling tube MS, and the adjustment tube MP is connected to the non-inverting input end of the error amplifier through the resistor feedback circuit; the input end of the adjustment tube is connected to the power supply, and the common end of the adjustment tube MP and the resistor feedback circuit is used as the output end of the low voltage difference linear regulator circuit; the error amplifier converts the feedback voltage V output by the resistor feedback circuit into a voltage V FB With reference voltage V REF An error signal is generated by comparison, and the adjustment tube MP is adjusted by amplifying the error signal; the bias current in the error amplifier is fed back by sampling the load current, and the bias current distribution circuit is used to increase the gain of the medium and high frequency error amplifier while also increasing the bandwidth of the error amplifier.

[0009] As a preferred embodiment: the output current dynamic sampling circuit includes a first transistor M1, a second transistor M2, an eighteenth transistor M S The eighteenth body tube M S The input end of the eighteenth transistor M is connected to the power supply. S The output end is connected to the output end of the first transistor M1 and the control ends of the first transistor M1 and the second transistor M2, the output end of the second transistor M2 is connected to the dynamic bias input end of the error amplifier, and the input ends of the first transistor M1 and the second transistor M2 are connected to the ground end.

[0010] Preferably, the error amplifier includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M 10 , the eleventh transistor M 11 , the twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 , the fifteenth transistor M 15 , the sixteenth transistor M 16 and the seventeenth transistor M 17 The input end of the fifth transistor M5 is connected to the power supply, and the control end of the fifth transistor M5 is connected to the fourth bias voltage V b4The output end of the fifth transistor M5 is connected to the input end of the sixth transistor M6 and the input end of the seventh transistor M7 respectively; the control end of the sixth transistor M6 is connected to the feedback circuit as the positive input end of the error amplifier, and the control end of the seventh transistor M7 is connected to the reference voltage source VREF as the negative input end of the error amplifier; the sixteenth transistor M 16 The input terminal and the seventeenth transistor M 17 The input ends of the sixteenth transistor M are connected to the power supply. 16 The output terminal and the control terminal and the seventeenth transistor M 17 The control end of the fourteenth transistor M is connected; 14 The input terminal of the sixteenth transistor M is connected 16 The output terminal of the fourteenth transistor M 14 The control terminal of the fifteenth transistor M is connected to 15 The common end of the two control ends is connected to the first bias voltage V b1 , the fifteenth transistor M 15 The input terminal of the seventeenth transistor M is connected 17 The output terminal of the twelfth transistor M 12 The input terminal of the fourteenth transistor M is connected 14 The output terminal of the twelfth transistor M 12 The control end of the thirteenth transistor M is connected to 13 The common end of the two control ends is connected to the second bias voltage V b2 , the thirteenth transistor M 13 The input terminal of the fifteenth transistor M is connected 15 The output terminal of the thirteenth transistor M 13 and the fifteenth transistor M 15 The common end of the tenth transistor M is used as the output end of the error amplifier; 10 The input terminal of the twelfth transistor M is connected 12 The output terminal of the tenth transistor M 10 The input end of the tenth transistor M 10 The output end of the tenth transistor M is connected to the ground end. 10 The control end of the eleventh transistor M is connected to 11 The common end of the two control ends is connected to the third bias voltage V b3 , the eleventh transistor M 11 The input terminal of the thirteenth transistor M is connected 13 The output terminal of the thirteenth transistor M 13The input end of the transistor M is connected to the output end of the seventh transistor M7, and the thirteenth transistor M 13 The output end of the third transistor M3 is connected to the ground end; the input end of the third transistor M3 and the input end of the fourth transistor M4 are both connected to the power supply, the output end of the third transistor M3 is connected to the output end of the second transistor M2, the control end of the third transistor M3 is connected to the control end of the fourth transistor M4 and the common end of the two control ends is connected to the output end of the second transistor M2, the output end of the fourth transistor M4 is connected to the input end of the sixth transistor M6 and the input end of the seventh transistor M7 respectively; the input end of the eighth transistor M8 and the input end of the ninth transistor M9 are both connected to the ground end, the control end of the eighth transistor M8 is connected to the control end of the ninth transistor M9 and the common end of the two control ends is connected to the eighteenth transistor M S The output end of the eighth transistor M8 is connected to the input end of the twelfth transistor M 12 The output end of the ninth transistor M9 is connected to the input end of the thirteenth transistor M 13 The output terminal.

[0011] As a preference, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 , the fifteenth transistor M 15 , the sixteenth transistor M 16 and the thirteenth transistor M 13 is a PMOS tube; the eighth transistor M8, the ninth transistor M9, the tenth transistor M 10 and the eleventh transistor M 11 It is an NMOS tube.

[0012] Preferably, the resistor feedback circuit comprises: a first resistor R1 and a second resistor R2; one end of the first resistor R1 is connected to the output end of the adjustment tube MP, the other end of the first resistor R1 is connected to the ground end through the second resistor R2, and the common end of the first resistor R1 and the second resistor R2 is connected to the non-inverting input end of the error amplifier as the output end of the feedback resistor.

[0013] Another technical solution of the present invention is the low power consumption and high power supply rejection ratio algorithm with the sampling load current technology, which is special in that it includes:

[0014] Increase the loop gain of the LDO to improve the power supply noise rejection characteristics of the LDO:

[0015]

[0016] In the formula, A EA is the gain of the error amplifier, β is the feedback factor of the feedback circuit, A POW is the gain of the power stage, PSR EA and PSR POW are the power supply rejection ratios of the error amplifier and the power stage, respectively. From this formula, we can see that increasing the gain of the error amplifier can improve the power supply noise rejection characteristics of the LDO;

[0017] To improve the power supply noise suppression characteristics of LDO in the medium and high frequency range, it can be achieved by increasing the gain of the error amplifier in the medium and high frequency range. For the error amplifier:

[0018] A EA =g m *R out (2)

[0019]

[0020]

[0021] R OUT ≈g m15 r m15 r m17 ||g m13 r m13 (r m7 ||r m11 ) (5)

[0022]

[0023] In the formula, g m represents the transconductance of the error amplifier input tube, r m15 、r m17 、r m13 、r m7 、r m11 They are the fifteenth transistor M in the error amplifier sleeve structure. 10 , the seventeenth transistor M 17 , the thirteenth transistor M 13 , the seventh transistor M7, the eleventh transistor M 11 Output resistance, g m15 , g m13 The thirteenth transistor M 13 and the fifteenth transistor M 15 The transconductance, R out Represents the output resistance of the error amplifier, GBW EA is the gain-bandwidth product of the error amplifier, CPOW is the load capacitance of the error amplifier output stage, I D is the drain-source current flowing through the input tube;

[0024] From the above formula, we can know that the bandwidth of the error amplifier is related to the g of the input pair tube. m is proportional to the value, and g m As the current I flowing through the input pair D The dynamic current bias circuit using load current sampling feedback technology directly injects the sampled bias current into the bias circuit of the error amplifier. The dynamic current is distributed to the differential input pair tube and the sleeve structure according to the fixed bias current distribution ratio designed by the original error amplifier:

[0025] Where no dynamic bias current is injected:

[0026] Injecting dynamic bias current:

[0027]

[0028] along with The bias current I flowing through the differential input pair tube D The increase of I′2 increases the gm of the differential input pair and correspondingly broadens the bandwidth of the error amplifier. However, the output resistance r of each transistor in the sleeve structure is also significantly reduced with the injection of I′2. o , which also reduces the output resistance R of the error amplifier OUT According to formula (2), the gain of the error amplifier is also reduced accordingly, which causes the power supply rejection ratio of the LDO to decrease at low frequencies.

[0029] As a preferred method: To further improve the power supply rejection ratio of the LDO, M4 provides a dynamic bias current I for the amplifier input pair tube. B1 , M7 and M8 provide dynamic bias current I for the common source and common gate circuit B2 and I B3 , where the dynamic bias current is:

[0030] When no dynamic bias current is injected:

[0031]

[0032] Injecting dynamic bias current:

[0033]

[0034]

[0035] design Then I′2=0

[0036] Since the values ​​of I'1 and I'2 are zero, the current flowing through the twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 , the fifteenth transistor M 15 , the sixteenth transistor M 16 , the seventeenth transistor M 17 The current is the same as that without adding dynamic bias current. According to formula (4) and formula (6), g m15 , g m13 、r m15 、r m17 、r m13 The values ​​of are the same as before the dynamic bias current is injected. According to formula (5), the output resistance of the error amplifier will not be significantly reduced due to the addition of the dynamic bias current, and the injected dynamic bias current is all injected into the differential input pair tube, significantly improving the gm of the input pair tube. According to formula (2) and formula (3), this injection method will increase the open-loop gain and widen the bandwidth of the error amplifier. Similarly, as the gain A of the error amplifier increases EA According to formula (1), the power supply rejection ratio of LDO is significantly improved.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] (1) The present invention utilizes load current sampling feedback technology to increase the bias current of some key modules of the error amplifier in a targeted manner through a new type of dynamic bias circuit modulation module. While significantly improving the transconductance Gm of the error amplifier, it slows down the resistance change of the error amplifier output resistor, improves the gain of the medium and high frequencies, and then increases the loop bandwidth, so that the power supply rejection ratio of the LDO loop at high frequencies is still large, while the power supply rejection ratio of the medium and low frequencies is not affected by the newly added dynamic current and remains at a relatively high level. From the above, it can be seen that the low-power consumption and high power supply rejection ratio LDO circuit of the present invention achieves a high power supply rejection ratio in the high frequency band while maintaining low cost.

[0039] (2) The present invention performs high-efficiency dynamic current biasing on the error amplifier by sampling the output current, thereby maintaining the high gain characteristics of the error amplifier and broadening the bandwidth of the error amplifier, thereby improving the power supply rejection ratio of the LDO high frequency band while maintaining ultra-low power consumption under no-load conditions.

[0040] (3) The present invention samples the output current and feeds the sampled current back to the error amplifier, and uses a new bias current distribution circuit to superimpose the fixed bias current of the error amplifier to increase the bandwidth of the error amplifier and improve the power supply rejection ratio of the error amplifier in the high frequency band.

[0041] (4) The LDO power supply suppression using the sampling circuit and dynamic bias adjustment error amplifier of the present invention is as follows: Figure 4 The dotted line of curve 2 is shown. Figure 4 By comparing Curve 1 (the LDO power supply rejection ratio curve using an error amplifier without dynamic bias adjustment), it can be found that the power supply rejection ratio in the mid-to-high frequency band has been greatly improved, while the power supply rejection ratio in the mid-to-low frequency band has also remained at a relatively high level. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a block diagram of a low-dropout linear regulator with low power consumption and high power supply rejection ratio of the present invention;

[0043] Figure 2 It is a block diagram of an error amplifier with a dynamic sampling current bias circuit of the present invention;

[0044] Figure 3 This is a comparison chart of the power supply rejection ratio of an LDO with a conventional dynamic bias error amplifier and an LDO with a conventional error amplifier.

[0045] Figure 4 The figure is a comparison diagram of the power supply rejection ratio of the LDO with the novel dynamic bias error amplifier added in the present invention and the LDO with the conventional error amplifier. DETAILED DESCRIPTION

[0046] The present invention will be further described below in conjunction with the accompanying drawings:

[0047] See also Figure 1 As shown, the low voltage drop linear regulator circuit of the present invention includes: a reference circuit, an error amplifier with dynamic current bias, a regulating tube MP, an output current sampling circuit and a feedback circuit. Among them:

[0048] The inverting input terminal of the error amplifier is connected to the reference voltage source VREF, the output terminal of the error amplifier is connected to the control terminal of the adjustment tube Mp, the output terminal of the adjustment tube MP is connected to the non-inverting input terminal of the error amplifier through a feedback circuit, the input terminal of the output current sampling circuit is connected to the output terminal of the error amplifier, and the output terminal of the output current sampling circuit is connected to the dynamic current input terminal of the error amplifier;

[0049] Since the function of the error amplifier is to compare the feedback voltage with the reference voltage Vref to generate an error signal, the adjustment tube Mp is adjusted by amplifying the error signal, and finally the output voltage of the whole circuit is stabilized. Therefore, the performance of the error amplifier directly affects the various performance parameters of the whole circuit, such as power supply rejection ratio, load regulation rate, linear regulation rate, etc. In order to achieve a high power supply rejection ratio in a wider frequency band, the error amplifier is usually required to have a higher gain in a wider frequency band. Therefore, the error amplifier generally adopts a folded cascode amplifier or a two-stage operational amplifier structure. Because the two-stage operational amplifier will produce two poles, it is necessary to design a compensation circuit to generate a zero point to offset a pole, which undoubtedly increases the design difficulty of the compensation network of the whole circuit. The folded cascode amplifier is a single-stage operational amplifier that can reduce the compensation difficulty. The folded cascode amplifier can also provide a larger gain and a larger loop bandwidth. Therefore, the present invention adopts a dynamic current bias error amplifier based on the folded cascode amplifier.

[0050] See also Figure 2 As shown, the error amplifier with dynamic current bias provided in the embodiment of the present invention includes: a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7, an eighth switch tube M8, a ninth switch tube M9, a tenth switch tube M 10 , the eleventh switch tube M 11 , the twelfth switch tube M 12 、Thirteenth switch tube M 13 , the fourteenth switch tube M 14 , the fifteenth switch tube M 15 , the sixteenth switch tube M 16 and the seventeenth switch tube M 17 ;

[0051] Wherein: the input end of the fifth transistor M5 is connected to the power supply VDD, the control end of the fifth transistor M5 is connected to the fourth bias voltage M4, and the output end of the fifth transistor M5 is respectively connected to the input end of the sixth transistor M6 and the input end of the seventh transistor M7;

[0052] The control terminal of the sixth transistor M6 is connected to the feedback circuit (feedback power supply V FB ), the control end of the seventh transistor M7 is connected to the reference voltage source V as the inverting input end of the error amplifier REF ;

[0053] The sixteenth transistor M 16 The input terminal and the seventeenth transistor M 17 The input terminals are connected to the power supply V DD , the sixteenth transistor M16 The output terminal and the control terminal and the seventeenth transistor M 17 The control end connection;

[0054] The fourteenth transistor M 14 The input terminal of the sixteenth transistor M is connected 16 The output terminal of the fourteenth transistor M 14 The control terminal of the fifteenth transistor M is connected to 15 The control terminal of the fifteenth transistor M is connected to the common terminal of the two control terminals and connected to the first bias voltage. 15 The input terminal of the seventeenth transistor M is connected 17 The output terminal;

[0055] The twelfth transistor M 12 The input terminal of the fourteenth transistor M is connected 14 The output terminal of the twelfth transistor M 12 The control end of the thirteenth transistor M is connected to 13 The control end of the two control ends and the common end of the two control ends are connected to the second bias voltage, the thirteenth transistor M 13 The input terminal of the fifteenth transistor M is connected 15 The output terminal of the thirteenth transistor M 13 and the fifteenth transistor M 15 The common end of the error amplifier is used as the output end of the error amplifier;

[0056] The tenth transistor M 10 The input terminal of the twelfth transistor M is connected 12 The output terminal of the tenth transistor M 10 The input end of the tenth transistor M 10 The output end of the tenth transistor M is connected to the ground end GND. 10 The control end of the eleventh transistor M is connected to 11 The common end of the two control ends is connected to the third bias voltage, and the eleventh transistor M 11 The input terminal of the thirteenth transistor M is connected 13 The output terminal of the thirteenth transistor M 13 The input end of the transistor M is connected to the output end of the seventh transistor M7, and the thirteenth transistor M 13 The output end is connected to the ground end GND;

[0057] The input end of the third transistor M3 and the input end of the fourth transistor M4 are both connected to the power supply V DD, the output end of the third transistor M3 is connected to the output end of the second transistor M2, the control end of the third transistor M3 is connected to the control end of the fourth transistor M4 and the common end of the two control ends is connected to the output end of the second transistor M2, and the output end of the fourth transistor M4 is connected to the input end of the sixth transistor M6 and the input end of the seventh transistor M7 respectively;

[0058] The input end of the eighth transistor M8 and the input end of the ninth transistor M9 are both connected to the ground end, the control end of the eighth transistor M8 is connected to the control end of the ninth transistor M9, and the common end of the two control ends is connected to the eighteenth transistor M S The output end of the eighth transistor M8 is connected to the input end of the twelfth transistor M 12 The output end of the ninth transistor M9 is connected to the input end of the thirteenth transistor M 13 The output terminal;

[0059] It should be noted that, in the error amplifier, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor and the thirteenth transistor are PMOS transistors;

[0060] The eighth transistor, the ninth transistor, the tenth transistor and the eleventh transistor are NMOS transistors.

[0061] As can be seen from the figure, the input pair of the error amplifier is a PMOS tube, so that the error amplifier can still work normally when the input voltage is relatively low. There are three bias voltages in the sleeve structure to provide a DC bias point for the op amp.

[0062] To further illustrate that the low voltage drop linear regulator circuit provided by the present invention can significantly improve the power supply rejection ratio, the error amplifier with dynamic current bias is analyzed and calculated below. According to relevant theories, increasing the loop gain of the LDO is beneficial to improving the power supply noise suppression characteristics of the LDO:

[0063]

[0064] Among them, A EA is the gain of the error amplifier, β is the feedback factor of the feedback circuit, A pow is the gain of the power stage, PSR EA and PSR pow are the power supply rejection ratios of the error amplifier and the power stage respectively. From the above formula, it can be seen that increasing the gain of the error amplifier can improve the power supply noise rejection characteristics of the LDO.

[0065] It can also be seen that to improve the power supply noise suppression characteristics of LDO in the medium and high frequency range, it can be achieved by increasing the gain of the error amplifier in the medium and high frequency band. For the error amplifier:

[0066] A EA =g m *R out (2)

[0067]

[0068]

[0069] R OUT ≈g m15 r m15 r m17 ||g m13 r m13 (r m7 ||r m11 ) (5)

[0070]

[0071] In the formula, g m represents the transconductance of the error amplifier input tube, r m15 、r m17 、r m13 、r m7 、r m11 are the output resistances of the fifteenth transistor, the seventeenth transistor, the thirteenth transistor, the seventh transistor, and the eleventh transistor in the sleeve structure of the error amplifier, respectively. m15 , g m13 are the transconductances of the thirteenth and fifteenth transistors, R out Represents the output resistance of the error amplifier, GBW EA is the gain-bandwidth product of the error amplifier, C pow is the load capacitance of the error amplifier output stage, I D is the drain-source current flowing through the input tube;

[0072] From the above formula, we can know that the bandwidth of the error amplifier is related to the g of the input pair tube. m is proportional to the value, and g m As the current I flowing through the input pair D If the dynamic current bias circuit of the load current sampling feedback technology is used to directly inject the sampled bias current into the bias circuit of the error amplifier, the dynamic current is distributed to the differential input pair tube and the sleeve structure according to the distribution ratio of the fixed bias current designed by the original error amplifier:

[0073] Where no dynamic bias current is injected:

[0074] Injecting dynamic bias current:

[0075]

[0076] along with The bias current I flowing through the differential input pair tube D The increase of I′2 increases the gm of the differential input pair and correspondingly broadens the bandwidth of the error amplifier. However, the output resistance r of each transistor in the sleeve structure is also significantly reduced with the injection of I′2. o , which also reduces the output resistance R of the error amplifier OUT According to Formula 2, the gain of the error amplifier is also reduced accordingly, which causes the power supply rejection ratio of the LDO to decrease at low frequencies, such as Figure 3 As shown in the figure, curve 1 is the LDO power supply rejection ratio curve without dynamic bias circuit, and curve 2 is the LDO power supply rejection ratio curve with dynamic bias circuit. By comparison, it can be found that: although due to g m As the bias current increases, the LDO power supply rejection ratio in the high frequency band is improved, but as the bias current increases, the error amplifier R out It's getting smaller. EA As a result, the power supply rejection ratio of mid- and low-frequency has also decreased significantly, which does not meet our design goals.

[0077] In order to more reasonably broaden the bandwidth of the error amplifier, improve the high-frequency open-loop gain of the error amplifier, and further improve the power supply rejection ratio of the LDO, the present invention adopts a new type of dynamic sampling current bias circuit module in the error amplifier, such as Figure 2 As shown. Isense is the sampling current, M1 and M2, M3 and M4 form current mirrors respectively, and M4 provides dynamic bias current I for the amplifier input pair tube. B1 , M7 and M8 provide dynamic bias current I for the common source and common gate circuit B2 and I B3 , where the dynamic bias current is:

[0078] Where no dynamic bias current is injected:

[0079]

[0080] Injecting dynamic bias current:

[0081]

[0082]

[0083] design Then I′2=0

[0084] Since the values ​​of I′1 and I′2 are zero, the currents flowing through the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, and the seventeenth transistor are the same as when no dynamic bias current is added. According to Formula 4 and Formula 6, g m15 , g m13 、r m15 、r m17 、r m13 The values ​​of are the same as before the dynamic bias current is injected. According to Formula 5, the output resistance of the error amplifier will not be significantly reduced due to the addition of the dynamic bias current. The dynamic bias current is injected into the differential input pair tube, which can significantly increase the gm of the input pair tube. According to Formula 2 and Formula 3, this injection method will greatly increase the open-loop gain and widen the bandwidth of the error amplifier. Similarly, as the gain A of the error amplifier increases EA According to formula (1), this method can significantly improve the power supply rejection ratio of the LDO. The power supply rejection ratio of the LDO using the sampling circuit and the dynamic bias adjustment error amplifier in the embodiment of the present invention is as follows: Figure 4 The dotted line of curve 2 is shown. Figure 4 By comparing Curve 1 (the LDO power supply rejection ratio curve using an error amplifier without dynamic bias adjustment), it can be found that the power supply rejection ratio in the mid-to-high frequency band has been greatly improved, while the power supply rejection ratio in the mid-to-low frequency band has also remained at a relatively high level.

[0085] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should fall within the scope of the claims of the present invention.

Claims

1. A low power consumption and high power supply rejection ratio LDO circuit with sampling load current technology, characterized in that: include: An error amplifier with dynamic current bias, an adjustment tube MP, a resistor feedback circuit, a reference circuit, and an output current sampling circuit: the output current sampling circuit is connected to the dynamic bias input terminal of the error amplifier; the inverting input of the error amplifier is connected to a reference voltage source VREF, the output terminal of the error amplifier is connected to the control terminal of the adjustment tube MP and the input terminal of the output current sampling circuit, the adjustment tube MP is connected to the non-inverting input terminal of the error amplifier through the resistor feedback circuit; the input terminal of the adjustment tube is connected to a power supply, the common terminal of the adjustment tube MP and the resistor feedback circuit is used as the output terminal of a low voltage difference linear regulator circuit; the error amplifier converts the feedback voltage V output by the resistor feedback circuit into a voltage V FB With reference voltage V REF An error signal is generated by comparison, and the adjustment tube MP is adjusted by amplifying the error signal; the bias current in the error amplifier is fed back by sampling the load current, thereby increasing the gain of the medium and high frequency error amplifier and the bandwidth of the error amplifier; The output current sampling circuit comprises a first transistor M1, a second transistor M2, and an eighteenth transistor MS; the input end of the eighteenth transistor MS is connected to a power supply, the output end of the eighteenth transistor MS is connected to the output end of the first transistor M1 and the control ends of the first transistor M1 and the second transistor M2, the output end of the second transistor M2 is connected to the dynamic bias input end of the error amplifier, and the input ends of the first transistor M1 and the second transistor M2 are connected to the ground end; The error amplifier includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M 10 , the eleventh transistor M 11 , the twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 , the fifteenth transistor M 15 , the sixteenth transistor M 16 and the seventeenth transistor M 17 The input end of the fifth transistor M5 is connected to the power supply, and the control end of the fifth transistor M5 is connected to the fourth bias voltage V b4 The output end of the fifth transistor M5 is connected to the input end of the sixth transistor M6 and the input end of the seventh transistor M7 respectively; the control end of the sixth transistor M6 is connected to the feedback circuit as the positive input end of the error amplifier, and the control end of the seventh transistor M7 is connected to the reference voltage source VREF as the negative input end of the error amplifier; the sixteenth transistor M 16 The input terminal and the seventeenth transistor M 17 The input ends of the sixteenth transistor M are connected to the power supply. 16 The output terminal and the control terminal and the seventeenth transistor M 17 The control end of the fourteenth transistor M is connected; 14 The input terminal of the sixteenth transistor M is connected 16 The output terminal of the fourteenth transistor M 14 The control terminal of the fifteenth transistor M is connected to 15 The common end of the two control ends is connected to the first bias voltage V b1 , the fifteenth transistor M 15 The input terminal of the seventeenth transistor M is connected 17 The output terminal of the twelfth transistor M 12 The input terminal of the fourteenth transistor M is connected 14 The output terminal of the twelfth transistor M 12 The control end of the thirteenth transistor M is connected to 13 The common end of the two control ends is connected to the second bias voltage V b2 , the thirteenth transistor M 13 The input terminal of the fifteenth transistor M is connected 15 The output terminal of the thirteenth transistor M 13 and the fifteenth transistor M 15 The common end of the tenth transistor M is used as the output end of the error amplifier; 10 The input terminal of the twelfth transistor M is connected 12 The output terminal of the tenth transistor M 10 The input end of the tenth transistor M 10 The output end of the tenth transistor M is connected to the ground end. 10 The control end of the eleventh transistor M is connected to 11 The common end of the two control ends is connected to the third bias voltage V b3 , the eleventh transistor M 11 The input terminal of the thirteenth transistor M is connected 13 The output terminal of the thirteenth transistor M 13 The input end of the thirteenth transistor M 13 The output end of the third transistor M3 is connected to the ground end; the input end of the third transistor M3 and the input end of the fourth transistor M4 are both connected to the power supply, the output end of the third transistor M3 is connected to the output end of the second transistor M2, the control end of the third transistor M3 is connected to the control end of the fourth transistor M4 and the common end of the two control ends is connected to the output end of the second transistor M2, the output end of the fourth transistor M4 is connected to the input end of the sixth transistor M6 and the input end of the seventh transistor M7 respectively; the input end of the eighth transistor M8 and the input end of the ninth transistor M9 are both connected to the ground end, the control end of the eighth transistor M8 is connected to the control end of the ninth transistor M9 and the common end of the two control ends is connected to the output end of the eighteenth transistor MS, the input end of the eighth transistor M8 is connected to the twelfth transistor M 12 The output end of the ninth transistor M9 is connected to the input end of the thirteenth transistor M 13 The output terminal.

2. The low power consumption and high power supply rejection ratio LDO circuit with sampling load current technology according to claim 1, characterized in that: The third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 , the fifteenth transistor M 15 , the sixteenth transistor M 16 is a PMOS tube; the eighth transistor M8, the ninth transistor M9, the tenth transistor M 10 and the eleventh transistor M 11 It is an NMOS tube.

3. The low power consumption and high power supply rejection ratio LDO circuit with sampling load current technology according to claim 1, characterized in that: The resistor feedback circuit includes: a first resistor R1 and a second resistor R2; one end of the first resistor R1 is connected to the output end of the adjustment tube MP, the other end of the first resistor R1 is connected to the ground end through the second resistor R2, and the common end of the first resistor R1 and the second resistor R2 is connected to the non-inverting input end of the error amplifier as the output end of the feedback resistor.

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