A Design Method for Single-Particle Transient Hardened LDO

Abstract

The present invention relates to a design method for single-particle transient hardened LDO, belonging to the technical field of protection against single-particle effects in CMOS integrated circuits for space applications. By using a double-exponential current source model, the single-particle transient sensitive nodes in the LDO circuit are located as the main loop point and the positive input point of the negative feedback amplifier in the bandgap reference source circuit respectively. For the LDO core circuit, the branch current of the main loop point circuit module is increased; for the bandgap reference source circuit of the LDO, the ratio of the left and right bjt transistors in the reference circuit is adjusted to 1:2, and a dual-redundant circuit structure for analog signals is designed to achieve hardening. The reliability of the LDO in the space radiation environment is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of protection against single event effects in CMOS integrated circuits, and relates to a design method for single event transient hardened LDO. Background Art

[0002] With the continuous improvement of the integration level, performance and complexity of ASIC / SoC chips for aerospace applications, the types and performance requirements of on-chip power supply voltages are constantly increasing. LDO (linear voltage regulator) can optimize the performance such as voltage accuracy, power supply capacity, power supply rejection ratio, noise and transient response required by the power supply module, improve the overall performance of the system, and reduce the types of chip power supplies and the number of PADs. Therefore, more and more LDO IPs, especially capless (without off-chip capacitor) LDO types, are integrated as on-chip power management modules in high-grade ASIC / SoC chips. However, as the power supply circuit for the on-chip core module, once the LDO fails in the radiation environment, it will bring very serious consequences to the entire chip and even the entire circuit system. Judging from the currently published materials, the research on the radiation resistance of LDO mainly focuses on the directions of total dose and single event latch-up, and there are few studies on the single event transient hardening technology for it. This is because the LDO circuit is a linear conversion circuit from high voltage to low voltage, with a relatively high supply voltage itself, and the application of frequency compensation makes the node capacitance very large. Therefore, it has good anti-single event soft error ability by itself. However, the LDO circuit structure is complex, with a large number of devices and circuit nodes. It is found that the reduction of the process node and the circuit structure characteristics of the capless LDO make some nodes sensitive to SET (single event transient). As an on-chip power supply system, once radiation problems occur, whether it is soft error or hard damage, the impact on the entire chip is catastrophic. Therefore, radiation resistance is a problem that must be solved for the space application of LDO IP.

[0003] In the space radiation environment, CMOS integrated circuits are vulnerable to single event transients. The generation of SET is when high-energy ions are incident on its path, electron-hole pairs will be generated. Under the action of the electric field, for NMOS, electrons drift towards the drain terminal, and for PMOS, holes drift towards the drain terminal, thus generating a transient pulse (SET). As a pure analog circuit, the supply voltage and node compatibility of LDO are relatively large, and the height of the SET pulse generated by particles with lower energy in the circuit is negligible. Moreover, most MOS transistors in the analog circuit work in the saturation region, and it is difficult to cause single event soft errors to it. However, in the space orbit environment, the energy range of irradiated particles is very wide, from several keV to dozens of MeV, and due to the relatively slow response speed of the analog circuit, once the system stability is affected by single particles and changes, the time for the system to return to normal through its own negative feedback circuit is very long.

[0004] Such asFigure 1 As shown in (a), it is a capless LDO used to provide a stable output voltage of 1.2V for the chip core. This circuit consists of a core circuit and a BG (bandgap reference) circuit. The core circuit includes a power transistor (MP), an error amplifier (EA), a transient response enhancement circuit, a soft start circuit, and a feedback resistor-capacitor network. By using the "virtual short" characteristic of the negative feedback operational amplifier, the output voltage has a linear relationship with the reference voltage, and the main pole of the loop is placed at the input of the power transistor; BG provides a stable reference voltage Vref for the LDO. A double-exponential current source is used to simulate the bombardment of all nodes of the LDO circuit with 75MeV. When SET bombards the main pole of the core circuit, a co-pulse as high as 1.5V appears at the output of the LDO, as shown in Figure 1 shown in (b); when SET bombards the Vn node of the BG circuit, the SET generated by it can even cause the output of the LDO to have a power-down lasting up to more than ten microseconds, as shown in Figure 2 shown in (b). As the operating frequency of the chip continues to increase, a power-down of more than ten microseconds will cause extremely serious functional errors from the entire chip to the system single machine; the power supply voltage range of the chip core is 1.2V ± 10%. Exceeding the power supply voltage range of the core will cause chip timing problems, resulting in logic errors. At the same time, too high a power supply voltage pulse will also affect the chip life. Therefore, it is necessary to strengthen the design of the sensitive areas of the circuit to avoid such errors. Summary of the Invention

[0005] The technical problem solved by the present invention is: overcoming the deficiencies of the prior art, and proposing a single-event transient hardened LDO design method.

[0006] The technical solution adopted by the present invention is:

[0007] A single-event transient hardened LDO design method includes:

[0008] (1) Design an LDO IP circuit according to application requirements, and the LDO IP circuit is not hardened against SET.

[0009] (2) Use a double-exponential current source model to simulate the bombardment of different nodes of the LDO IP circuit by high-energy particles with a LET threshold of 75MeV, and determine the sensitive nodes of SET in the circuit. The sensitive nodes include the main pole of the loop and the positive input point of the negative feedback amplifier in the bandgap reference source circuit.

[0010] (3) Strengthen the sensitive nodes of SET in the circuit to obtain an LDO IP circuit hardened against SET. The strengthening process for the sensitive nodes of SET in the circuit includes:

[0011] Increase the branch current of the main pole of the loop.

[0012] Adjust the ratio of the left and right BJT tubes and the layout of the bandgap reference source circuit;

[0013] The reference voltage V output by the bandgap reference circuit ref The signal has dual-path redundancy;

[0014] (4) Simulate the SET-hardened LDO IP circuit to verify whether the circuit's functions and performance meet the design expectations. If so, determine the device parameters, design the LDO IP circuit layout, and use physical tools to verify the correctness of the layout. Once the layout is verified to be correct, proceed to step (5);

[0015] (5) Extract the parasitic parameters of the LDO IP circuit and build a simulation verification environment based on the actual application to verify whether the function, performance, and anti-SET capability of the LDO IP circuit meet the requirements. If they do, the design is completed; if not, return to step (4) and modify the device parameters until the function, performance, and anti-SET capability of the LDO IP circuit meet the requirements.

[0016] Preferably, the adjustment of the ratio of the left and right BJT tubes and the layout of the circuit in the bandgap reference source is implemented as follows:

[0017] Adjust the size ratio of the left BJT tube Q1 and the right BJT tube Q0 in the bandgap reference source circuit to 1:2;

[0018] The two BJT tubes Q0 are connected in parallel, and the collector active areas of the two Q0 and the collector active area of Q1 are shared on the layout.

[0019] Preferably, an N+ guard ring is designed for each Q0.

[0020] Preferably, the reference voltage V output by the bandgap reference source circuit is ref The implementation of dual-path redundancy of signals is as follows:

[0021] A backup bandgap reference source circuit is designed. By adjusting the voltage divider resistor value, the output voltage of the backup bandgap reference source circuit is made 0.05V lower than that of the main bandgap reference source circuit. The output voltages of the main bandgap reference source circuit and the backup bandgap reference source circuit are simultaneously output to a comparison circuit. Under normal circumstances, the comparison circuit outputs the output voltage of the main bandgap reference source circuit. When the main bandgap reference source circuit is bombarded by a single-particle transient, the output voltage of the backup bandgap reference source circuit is output.

[0022] Preferably, the comparison circuit includes an error comparator, an inverter INV1, an inverter INV2, a first MOS switch and a second MOS switch; the first MOS switch and the second MOS switch are each composed of an NMOS and a PMOS;

[0023] The output signal of the primary bandgap reference circuit is simultaneously connected to the positive input terminal Vp1 of the error comparator and the input terminal of the first MOS switch, and the output signal of the primary bandgap reference circuit is simultaneously connected to the negative input terminal Vn1 of the error comparator and the input terminal of the second MOS switch. The output terminal of the error comparator is connected to the input terminal of the inverter INV1, and the output of INV1 is simultaneously connected to the input terminal of the inverter INV2, the gate of the PMOS in the first MOS switch, and the gate of the NMOS in the second MOS switch; the output terminal of INV2 is simultaneously connected to the gate of the NMOS in the first MOS switch and the gate of the PMOS in the second MOS switch, and the output terminals of the first MOS switch and the second MOS switch are shorted together as the output V of the dual redundant BG circuit ref 。

[0024] Preferably, in the step (3), after reinforcement, the circuit area increment should be ensured to be less than 15%, and the LET threshold reaches 75 MeV·cm 2 / mg。

[0025] Preferably, the LDO IP circuit and its reinforcement process are both implemented by the 1P6M_1TM process

[0026] Preferably, N+ guard ring design is performed on the parallel PMOS transistors in the LDO IP circuit

[0027] In view of the functional influence of single event transient effect in space on the LDO IP and based on the reliability problem of LDO in the space radiation environment, the present invention proposes a particle transient hardened LDO design method. By using a double exponential current source model, the single event transient sensitive nodes in the LDO circuit are located as the main loop point and the Vn point of the gap basic source circuit respectively. For different parts of the circuit structure, targeted reinforcement measures are formulated. While greatly reducing the area and performance overhead, SET hardening of the LDO is achieved. The advantages are as follows

[0028] (1) For different parts of the circuit structure, targeted reinforcement measures are formulated. For the LDO core circuit, by increasing the branch current passing through the main loop point circuit module; for the bandgap basic source circuit of the LDO, the ratio of the left and right bjt transistors in the reference circuit is adjusted to 1:2, and a dual redundant circuit structure for analog signals is designed to achieve anti-SET hardening with an area overhead of less than 15%, and the LET threshold can reach 75 MeV·cm 2 / mg。

[0029] (2) Currently, for the SET hardening of the BG circuit, it is mainly achieved by adding filter capacitors at the output end, which will bring a large on-chip area overhead; the most commonly used TMR hardening method is mainly for the redundancy hardening of digital signals and is not applicable to analog signals. Starting from the characteristics of analog signals, the present invention proposes an analog circuit redundancy method in BG hardening and gives the corresponding circuit structure, opening up a new implementation method for the SET hardening of the BG circuit. Description of the Drawings

[0030] Figure 1 It is a schematic diagram of bombarding simulation of all nodes of the core circuit in the LDO at 75 MeV for all process corners. Among them, (a) is the block diagram of the LDO structure, and (b) is the waveform change at the output end caused by bombarding the core circuit of the LDO with particles;

[0031] Figure 2 It is a schematic diagram of bombarding simulation of all nodes of the BG circuit in the LDO at 75 MeV for all process corners. Among them, (a) is the circuit structure diagram of the BG circuit, and (b) is the waveform change at the output end caused by bombarding the bandgap reference circuit of the LDO with particles;

[0032] Figure 3 It is the layout design of the bjt transistor in the BG circuit;

[0033] Figure 4 It is a schematic diagram of the BG circuit;

[0034] Figure 5 It is the post-simulation result of the LDO;

[0035] Figure 6 It is the overall layout of the LDO of the present invention;

[0036] Figure 7 It is a schematic diagram of the method of the present invention. Detailed Embodiment

[0037] The present invention will be further described below with reference to the drawings.

[0038] As Figure 7 shown, the specific design process of the single-event transient hardening LDO design method of the present invention is as follows:

[0039] (1) According to the application requirements, design the LDO IP circuit without SET hardening as the input for the SET analysis and development of the present invention.

[0040] (2) Use the double-exponential current source model to simulate the bombardment of different nodes of the LDO circuit by high-energy particles with a LET threshold of 75 MeV, determine the positions of the SET-sensitive nodes in the circuit, and locate the single-event transient sensitive nodes in the LDO circuit as the main loop point and the Vn point of the gap basic source circuit.

[0041] (3) For different parts of the circuit structure, comprehensively consider the layout area and circuit performance overhead, and specifically formulate reinforcement measures. On the premise of ensuring circuit performance, achieve SET hardening with an area overhead increment less than 15%, and the LET threshold can reach 75 MeV·cm 2 / mg.

[0042] (4) According to the reinforcement plan, design the LDO IP circuit for SET hardening, and simulate and verify whether the functional performance of the circuit meets the design expectations; according to the LDO IP circuit with adjusted structure and device parameters, design the layout, and use physical tools to verify the correctness of the layout.

[0043] (5) Extract the parasitic parameters of the LDO circuit, construct a simulation verification environment according to the actual application, and simulate and verify the function, performance, and SET resistance ability of the designed LDO.

[0044] The specific implementation details of the above steps are as follows:

[0045] 1. SET Hardening Scheme for LDO IP

[0046] Most nodes of the LDO circuit have good SET resistance ability. However, after simulating the bombardment of different nodes of the LDO circuit by high-energy particles with an analog LET threshold of 75 MeV, it is determined that the main stage point of the LDO loop and the Vn node of the BG circuit are sensitive areas for SET. In the analog circuit, the larger the branch current, the stronger the SET resistance ability of the circuit. Research shows that when the branch current is greater than 10 uA, the analog circuit system can resist most SETs. Since the error amplifier and the transient response enhancement circuit are connected to the main stage point of the circuit, and their outputs directly affect the stability of the output voltage as the input of the power MOS transistor, these nodes are SET-sensitive nodes. By increasing the branch current of these nodes, SET hardening of the main stage point of the LDO can be well achieved. The area overhead of the capless LDO is mainly caused by the frequency compensation capacitor. Therefore, increasing the MOS transistors (increasing the branch circuit) at the main stage point has little impact on the area of the entire IP; and for the entire very large-scale ASIC, the additional power consumption overhead of dozens of microamperes is completely acceptable.

[0047] Since the core part of the BG circuit and the SET-sensitive node are in the bjt transistor, and the area of the bjt in the circuit is much larger than that of the MOS transistor, in order to achieve smaller area and performance overhead, the upper SET hardening of the BG circuit is relatively complex. In order to improve the SET protection effect of the on-chip LDO IP, the present invention solves the upper SET hardening problem of the BG circuit through two ways: (1) Adjust the ratio of the left and right bjt transistors in the bandgap reference source circuit, and combine the layout to improve the SET resistance ability of the BG itself; (2) For the reference voltage V output by the BG refThe signal is made into a dual - path redundancy to further improve the SET - resistance ability of the LDO circuit.

[0048] (1) Adjust the ratio of the left - and - right - hand side bjt transistors in the reference circuit, and combine the layout to improve the SET - resistance ability of the BG itself.

[0049] Since the function of the BG circuit is to provide a stable input reference voltage for the LDO, whether it is a case - code structure or an op - amp structure BG, its area is closely related to the sizes of the MOS transistors and bjt transistors, and the overall area is much smaller than that of the LDO core circuit. If the branch current is increased several times, it will have a greater impact on the overall area and power consumption of the LDO. Therefore, using the method of increasing the branch current to achieve SET hardening is not the best choice in the BG circuit.

[0050] The basic principle of the BG circuit is to utilize the fact that the base - emitter voltage V BE of the bipolar transistor has a negative temperature coefficient, while the voltage difference ΔV BE between the two base - emitter regions under different current - density biasing has a positive temperature coefficient. These two voltages are linearly superimposed to obtain a reference voltage source with a low temperature coefficient.

[0051] As Figure 2 shown in (a) of ref , V

[0052]

[0053] As Figure 2 shown, in the formula, V ref is the output voltage of the band - gap reference source circuit, R ref is the output - branch resistance, I D(M3) is the output - branch current, V BE(Q1) is the voltage of the emitter of bjt transistor Q1 with respect to ground, V BE(Q0) is the voltage of the emitter of bjt transistor Q0 with respect to ground, n is the ratio of Q1 to Q0, R1 is the resistance of the Q0 branch, in series with Q0, R2 is the resistance in parallel with Q0 and R1, V T is the voltage equivalent of temperature (at room temperature, V T = 26mV), I SS is the reverse saturation current of the diode (since the base and collector of this bjt transistor are short - circuited, it is equivalent to a diode), I D(M1) is the emitter current of Q1, and I D(M2) is the emitter current of Q2.

[0054] From Equation 1, when the ratio n value of the left - and - right - hand side bjt transistors in the BG circuit becomes smaller, in order to ensure V refFor the low temperature coefficient, the resistance R1 should also be reduced, so as to reduce the voltage change caused by high-energy particle incidence on the Vn node, and further reduce the perturbation and recovery time of the output voltage V. ref Therefore, the ratio of the bjts on the left and right sides is adjusted to 1:2 (the ratio of the traditional BG circuit is 1:8). And in the layout design, the bjt Q1 is placed on the left side, and the two Q0s on the right side are connected in parallel. The active regions of the collectors of Q0 and Q1 share the same layout. While reducing the on-chip process deviation, it can improve both the reduction of the circuit area and the SET tolerance of the circuit. As Figure 3 shown in the layout design of the bjts in the BG circuit.

[0055] (2) Double-path redundancy is performed on the reference voltage V ref signal output by the BG circuit to further improve the SET tolerance of the LDO circuit.

[0056] For digital circuits, TMR is a very effective reinforcement measure. However, the BG outputs a voltage value rather than a logic value. Therefore, the traditional TMR method for the reinforcement of BG cannot be realized. From the currently published literature, the SET reinforcement of the BG circuit is mainly achieved by leading out a large capacitor at the output voltage terminal. However, since the establishment time of the BG circuit is in the microsecond level, at least an nF-level filtering capacitor is required to filter out such a large SET pulse, which will bring a huge area overhead on the chip. Therefore, it is necessary to develop a reinforcement method with low resource overhead for analog circuits. Through simulation analysis, the SET pulse will cause the output reference voltage to lose power and will not bring an overshoot of the output voltage. Therefore, the present invention uses two BGs with two comparators to realize the reinforcement of the BG circuit. The specific scheme is as Figure 4 shown.

[0057] As Figure 4 shown, BGR100 is a bandgap reference circuit with an output voltage of 1V, and the output signal is V ref 100, BGR095 is a bandgap reference circuit with an output voltage of 0.95V, and the output signal is V ref 095, V ref 100 are respectively connected to the positive electrode Vp1 of the error comparator and the input pole of MOS switch 1 (the source levels of PMOS and NMOS transistors); V ref095 is respectively connected to the negative electrode Vn1 of the error comparator and the input stage of the MOS switch 2 (the source electrodes of the PMOS transistor and the NMOS transistor). The output Vout of the error comparator is connected to the input port of the inverter INV1, and the output of INV1 is respectively connected to the input port of the inverter INV2, the gate of the PMOS in the MOS switch 1, and the gate of the NMOS in the MOS switch 2; the output of INV2 is respectively connected to the gate of the NMOS in the MOS switch 1 and the gate of the PMOS in the MOS switch 2, and the output ends of the MOS switch 1 and the MOS switch 2 are shorted together as the output V of the dual - path redundant BG circuit ref 。

[0058] Under normal circumstances, V ref = 1V. When a high - energy particle hits BG1 and causes the output voltage to lose power, V ref = 0.95V, making the output voltage of the LDO = 0.95 * 1.2 = 1.14V, which can meet the power supply requirements until the output returns to 1.2V.

[0059] 2. LDO Layout Strengthening Design and Post - simulation

[0060] The LDO in this design is implemented with double - gate MOS transistors under a 3.3V supply voltage. In order to further improve the SET - resistance ability of the circuit itself and overcome the possible SEL effect, this design uses a double - protection ring to achieve layout - level strengthening. Since the LDO IP of the present invention can support the core power supply of the whole chip, the maximum load current is much larger than that of the commercial IP under the same process, which makes the size of the power MOS transistor very large. In the case of heavy load, heat dissipation becomes a problem. This poses very high requirements for the layout design of the power MOS transistor. In the layout design of the present invention, the large power MOS transistor is split and paralleled, so that the output current is evenly distributed, avoiding the reliability problem caused by overheating of the chip due to excessive local current in the power MOS, and at the same time, an N + protection ring design is made for each paralleled PMOS transistor, avoiding the SEL risk caused by too large local active area and the influence of on - chip noise on the circuit.

[0061] Figure 6 This is the overall layout of the LDO of the present invention. The present invention is implemented using the 1P6M_1TM process, and the IP area is 440 * 290um 2 . Compared with the SMIC commercial LDO IP under the same process, the area increase does not exceed 15%, and some key indicators are better than those of the commercial IP. The specific situation is shown in Table 1.

[0062] Table 1 Comparison of Main Indicators with Commercial IP under the Same Process

[0063] LDO IP Design of This Project SMIC Commercial LDO IP Process SMIC 0.13um Commercial SMIC 0.13um Commercial Number of Metal Layers 6 6 Input Voltage VIN 2.64～3.8V 2.97～3.63V Output Voltage VOUT 1.16~1.26V@all conner 1.08~1.32V@all conner Operating Temperature Range -55～125℃ -40～125℃ Area <![CDATA[442*290um 2 > <![CDATA[398*280um 2 > Maximum Load Current 400mA 100mA Transient Line Regulation 20mV 37mV Transient Load Regulation 80mV 84mV External Capacitor 0 4.7uF Single-Event Transient Index <![CDATA[≥75MeV·cm 2 / mg]]> / Single-Event Latchup Index Immune / Total Dose Index 100krad(Si) /

[0064] The post-layout simulation of the LDO of the present invention is carried out under the following conditions: powered on at 1 μs, the load changes from 0 to 400 mA within 200 ns, and the equivalent SET threshold is 75 MeV·cm2 / mg; the supply voltage ripple is 100 kHz with a peak-to-peak value of 100 mV, and the simulation results of the LDO IP under the full process corner (1215 corners, the permutations and combinations of process, voltage, and temperature within the typical, maximum, and minimum ranges). Figure 5 The post-layout simulation results of the LDO show that neither the supply voltage, the load, nor the heavy particle incidence will cause the output voltage to change beyond a range of 10%. The LDO based on the present invention has strong single-event transient immunity (LET threshold ≥ 75 MeV·cm 2 / mg) and will not result in performance degradation.

[0065] The content not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art.

Claims

1. A design method for single-particle transient hardened LDO, characterized in that Including: (1) Design an LDO IP circuit according to application requirements, and the LDO IP circuit is not SET-hardened; (2) Use a double-exponential current source model to simulate the bombardment of different nodes of the LDO IP circuit by high-energy particles with a LET threshold of 75 MeV, and determine the sensitive nodes of SET in the circuit. The sensitive nodes include the main loop point and the positive input point of the negative feedback amplifier in the bandgap reference source circuit; (3) Perform hardening processing on the sensitive nodes of SET in the circuit to obtain a SET-hardened LDO IP circuit; The hardening processing of the sensitive nodes of SET in the circuit includes: Increase the branch current of the main loop point; Adjust the ratio of the left and right BJT transistors and the layout in the bandgap reference source circuit; Dual-channel redundancy is performed on the reference voltage V ref signal output by the bandgap reference source circuit; (4) Simulate the SET-hardened LDO IP circuit to verify whether the functions and performance of the circuit meet the design expectations. If they meet, determine the device parameters, design the layout of the LDO IP circuit, and use physical tools to verify the correctness of the layout. After the layout verification is correct, proceed to step (5); (5) Extract the parasitic parameters of the LDO IP circuit, construct a simulation verification environment according to the actual application, and verify whether the functions, performance, and SET resistance of the LDO IP circuit meet the requirements. If they meet the requirements, the design is completed; if they do not meet the requirements, return to step (4) to modify the device parameters until the functions, performance, and SET resistance of the LDO IP circuit meet the requirements.

2. The single-particle transient hardening LDO design method according to claim 1, wherein The implementation method of adjusting the ratio of the left and right BJT transistors and the layout in the bandgap reference source circuit is as follows: Adjust the size ratio of the left BJT transistor Q1 to the right BJT transistor Q0 in the bandgap reference source circuit to 1:2; Connect two BJT transistors Q0 in parallel, and the active regions of the collectors of the two Q0s share the same area with the collector of Q1 in the layout.

3. A single-particle transient hardening LDO design method according to claim 2, characterized in that Design an N+ protection ring for each Q0.

4. A single-particle transient hardening LDO design method according to claim 1, characterized in that The implementation method of dual-channel redundancy for the reference voltage V ref output by the bandgap reference source circuit is as follows: Design a backup bandgap reference source circuit. By adjusting the value of the voltage-dividing resistor, make the output voltage of the backup bandgap reference source circuit 0.05 V lower than that of the main bandgap reference source circuit. Output the output voltages of the main bandgap reference source circuit and the backup bandgap reference source circuit to the comparison circuit at the same time. Under normal circumstances, the comparison circuit outputs the output voltage of the main bandgap reference source circuit. When the main bandgap reference source circuit is bombarded by a single-event transient, it outputs the output voltage of the backup bandgap reference source circuit.

5. A single-particle transient hardening LDO design method according to claim 4, characterized in that The comparison circuit includes an error comparator, an inverter INV1, an inverter INV2, a first MOS switch, and a second MOS switch; both the first MOS switch and the second MOS switch are composed of an NMOS and a PMOS; The output signal of the primary bandgap reference circuit is simultaneously connected to the positive input terminal Vp1 of the error comparator and the input terminal of the first MOS switch, and the output signal of the primary bandgap reference circuit is simultaneously connected to the negative input terminal Vn1 of the error comparator and the input terminal of the second MOS switch. The output terminal of the error comparator is connected to the input terminal of the inverter INV1, and the output of INV1 is simultaneously connected to the input terminal of the inverter INV2, the gate of the PMOS in the first MOS switch, and the gate of the NMOS in the second MOS switch; the output terminal of INV2 is simultaneously connected to the gate of the NMOS in the first MOS switch and the gate of the PMOS in the second MOS switch. The output terminals of the first MOS switch and the second MOS switch are shorted together as the output V of the dual-redundancy BG circuit ref .

6. A single-particle transient hardening LDO design method according to claim 1, characterized in that In the step (3), after reinforcement, the circuit area increment should be ensured to be less than 15%, and the LET threshold reaches 75 MeV·cm 2 / mg.

7. A single-particle transient hardening LDO design method according to claim 1, characterized in that The LDO IP circuit and its hardening process are both implemented using the 1P6M_1TM process.

8. A single-particle transient hardening LDO design method according to claim 1, characterized in that Design an N+ protection ring for the parallel PMOS transistors in the LDO IP circuit.

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