An over-temperature protection circuit suitable for ultra-low power linear regulator

Abstract

The invention discloses an over-temperature protection circuit suitable for an ultra-low power linear regulator, comprising a load detection module, a PTAT voltage generation module and a voltage comparator module. The load detection module is used to detect the load state of the linear regulator. When the load is zero, the load detection module outputs a control signal to turn off the PTAT voltage generation module and the voltage comparator module, so that the over-temperature protection circuit is in a dormant state; when the load increases, the load detection module outputs a control signal to turn on the PTAT voltage generation module and the voltage comparator module; the PTAT voltage generation module uses a self-biased current mirror structure to achieve real-time temperature detection, and the output voltage is proportional to the temperature. The over-temperature protection circuit of the invention is to reduce the problem of excessive transient current during logic flipping. A current limiting protection circuit composed of an NMOS power consumption circuit is connected in series at the ground end of the logic gate circuit, which effectively reduces the impact of transient current on the ultra-low power linear regulator.

Description

Technical Field

[0001] The invention relates to the field of linear voltage stabilizers, and in particular to an over-temperature protection circuit suitable for ultra-low power consumption linear voltage stabilizers. Background Art

[0002] Linear regulator is a commonly used power management chip. It cannot work at high temperature for a long time. When the local temperature of the chip exceeds a certain upper limit, the PN junction will be thermally broken down, resulting in overcurrent, causing irreversible damage to the entire chip. The reasons for the excessive temperature of the chip are excessive output current, poor chip heat dissipation, or local circuit short circuit. Therefore, when the temperature is too high, the linear regulator needs to shut down the chip through the over-temperature protection circuit to ensure that the chip is not damaged.

[0003] Figure 1 The figure shows a typical linear regulator over-temperature protection circuit structure, which utilizes the fact that the forward bias voltage of the transistor PN junction is a function of temperature, decreases with increasing temperature, and has good consistency. The over-temperature protection function is achieved by comparing the temperature-related PN junction forward bias voltage with the reference voltage.

[0004] Figure 1 In the figure, Vbias is the bias voltage output by the reference source that is independent of temperature. It drives M1 and M2 to generate bias current. The current I1 generates the reference voltage VY through the resistors R1 and R2. VY is also independent of temperature. The voltage VX at point X is the forward conduction voltage VBE of the PN junction, which has a negative temperature characteristic. When working normally, VX is greater than VY, the comparator output is 0, Vctrl is 1, the M3 tube is turned on, R2 is short-circuited, and the reference voltage is VY=I1*R1; when the temperature rises, the voltage VX decreases. When the maximum temperature is reached, VX is less than VY, the comparator output is 1, Vctrl is 0, the M3 tube is turned off, and the reference voltage increases to VY'=I1*(R1+R2). Over-temperature protection is performed, the linear regulator power tube is turned off, and there is no output current. Because the reference voltage is VY' at this time, the comparator will flip only when the temperature drops to a point lower than the maximum value, so that the linear regulator returns to normal working state.

[0005] This circuit structure uses a dual-end input comparator and a normally open bias circuit, which consumes a certain amount of current and cannot be used in an ultra-low power linear regulator with a μA-level quiescent current. Summary of the invention

[0006] The purpose of the present invention is: In view of the above problem, the present invention proposes an over-temperature protection circuit suitable for an ultra-low power consumption linear regulator.

[0007] The technical solution of the present invention is:

[0008] An over-temperature protection circuit suitable for an ultra-low power linear regulator includes a load detection module, a PTAT voltage generation module and a voltage comparator module, wherein:

[0009] The load detection module is used to detect the load state of the linear regulator. When the load is zero, the load detection module outputs a control signal to turn off the PTAT voltage generation module and the voltage comparator module, so that the over-temperature protection circuit is in a dormant state; when the load increases, the load detection module outputs a control signal to turn on the PTAT voltage generation module and the voltage comparator module, monitor the regulator temperature and realize the over-temperature protection function;

[0010] The PTAT voltage generation module uses a self-biased current mirror structure to achieve real-time temperature detection, and the output voltage is directly proportional to the temperature;

[0011] The voltage comparator uses a transistor single-ended input structure, and the comparator threshold voltage is equal to the BE junction turn-on voltage of the NPN transistor.

[0012] Preferably, the linear regulator includes a bandgap reference module, a high voltage pre-modulation module, an error amplifier, an over-temperature protection circuit, a power tube and a feedback resistor network; wherein:

[0013] The high-voltage pre-modulation module converts the high-voltage input power supply VDD_H into a low-voltage power supply VDD_L that is weakly correlated with the input power supply, and supplies power to the error amplifier preamplifier stage and the over-temperature protection circuit;

[0014] The error amplifier comprises a preamplifier stage EA1 and an output driver stage MN1 branch connected in sequence; the output driver stage MN1 branch is connected to control the on-off of the power tube MP, and the power tube MP is connected in series with a feedback resistor network;

[0015] The gap reference module and the feedback resistor network are respectively connected to the two-phase input terminals of the preamplifier stage EA1;

[0016] The over-temperature protection circuit is connected between the preamplifier stage and the output driver stage of the error amplifier, and determines the load condition of the linear regulator by sampling the gate voltage of the input tube MN1 of the output driver stage.

[0017] Preferably, the load detection module includes MOS tubes M20, M21, M22, M23, M24, inverters INV1, INV2, INV3 and NAND gates NAND;

[0018] The MOS tubes M22, M23, and M20 are connected in series between the low-voltage power supply VDD_L and VSS in sequence, the gates of M20 and M21 are connected to the gate voltage EA_O1 of MN1, the source of M21 is connected to VSS, the drain is connected to the drain of M20 through M24, the drain of M20 is also connected to the input end of the inverter INV1, the gate of M24 is connected to the output end of the inverter INV1, and the output end of INV1 is connected to the input end of INV2; the output end of INV2 and the output end OTP_ctrn of the voltage comparator are respectively connected to the two input ends of the NAND gate NAND, the output end enb of the NAND gate NAND is connected to the input end of the inverter INV3, and the output end of INV3 generates an enable signal en.

[0019] Preferably, the PTAT voltage generating module is composed of two parts: a temperature detection circuit and a startup circuit; the temperature detection circuit includes two parts: a current mirror self-bias circuit and a current mirror replication circuit; the current mirror self-bias circuit generates a current IPTAT that is proportional to the absolute temperature; the current mirror replication circuit proportionally replicates the IPTAT current and generates a voltage VPTAT that is proportional to the temperature after flowing through a resistor, thereby realizing real-time monitoring of the temperature; the startup circuit is used to prevent the PTAT voltage generating module from being in a degenerate state when it is enabled.

[0020] Preferably, the current mirror self-bias circuit of the temperature detection circuit includes transistors Q1, Q2, a resistor R1 and PMOS tubes M1, M2; the current mirror replication circuit includes a PMOS tube M3 and resistors R2, R3; the bases of the transistors Q1, Q2 are connected in common, the gates of the PMOS tubes M1, M2, M3 are connected in common, the PMOS tube M1, the transistor Q1, and the resistor R1 are connected in series between the low-voltage power supply VDD_L and VSS in sequence, the PMOS tube M2 and the transistor Q2 are connected in series between the low-voltage power supply VDD_L and VSS in sequence; the PMOS tube M3 and the resistors R2, R3 are connected in series between the low-voltage power supply VDD_L and VSS in sequence.

[0021] Preferably, the startup circuit includes M9, M10, M11, M12, M13, M14 and capacitor C1; when the enable is just turned on, the gate voltage of M13 is high, the gate voltages of M11 and M12 are low, and the gate voltage of M14 is also low, so the gate voltage of M10 is high, and the NMOS tube M10 is turned on. Since the M9 tube is a consumption tube, the threshold voltage is less than 0, so the M9 and M10 tube branches generate current to charge the capacitor C1, thereby lowering the gate voltage of M1, and the current mirror self-bias circuit leaves the degenerate state and starts to work.

[0022] Preferably, when the current mirror self-bias circuit is started up, the gate voltage of M13 becomes low, and the gate voltages of M11 and M12 are pulled up. Since the width-to-length ratio of M11 is much larger than the width-to-length ratio of M14, the gate voltage of M10 is pulled down, the M10 tube is cut off, and the currents of the M9 and M10 branches are zero, which does not affect the operation of the current mirror self-bias circuit.

[0023] The advantages of the present invention are:

[0024] The ultra-low power consumption linear regulator over-temperature protection circuit of the present invention is to reduce the problem of excessive transient current during logic flipping. A current limiting protection circuit composed of an NMOS power transistor is connected in series to the ground end of the logic gate circuit, which effectively reduces the impact of transient current on the ultra-low power consumption linear regulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0026] Figure 1 It is a typical linear regulator over-temperature protection circuit structure;

[0027] Figure 2 This is a principle block diagram of the ultra-low power linear regulator with over-temperature protection described in the present invention;

[0028] Figure 3 This is a structural diagram of an over-temperature protection circuit suitable for an ultra-low power consumption linear regulator according to the present invention;

[0029] Figure 4 The inverter with NMOS power consumption limiting current circuit of the present invention;

[0030] Figure 5 The figure shows a NAND gate with an NMOS power consumption current limiting circuit according to the present invention;

[0031] Figure 6 This is a comparison diagram of transient current simulation of the inverter with infinite current tube according to the present invention;

[0032] Figure 7 This is the simulation result of the over-temperature protection of the linear regulator at 1mA load described in the present invention;

[0033] Figure 8 These are simulation results of the over-temperature protection start-up process of the linear regulator under different load conditions described in the present invention. DETAILED DESCRIPTION

[0034] like Figure 2 As shown, the circuit principle block diagram of the ultra-low power consumption linear regulator with over-temperature protection described in the present invention, the linear regulator mainly includes modules such as bandgap reference, high voltage pre-modulation, error amplifier, over-temperature protection, power tube and feedback resistor network.

[0035] The ultra-low power linear regulator supports a wide range of input voltages and uses a high-voltage pre-modulation module to convert the high-voltage input power supply VDD_H into a low-voltage power supply VDD_L that is weakly related to the input power supply, and to power modules such as the error amplifier preamplifier stage and over-temperature protection.

[0036] The error amplifier consists of the preamplifier stage EA1 and the output driver stage MN1 branch. The preamplifier stage is powered by a low-voltage power supply to take advantage of the superior performance of the low-voltage MOS tube; the input tube MN1 of the output driver stage is still a low-voltage tube, and the bias current Ib is generated by a high-voltage tube, which can achieve a wide output range to better drive the gate of the high-voltage power tube MP.

[0037] The over-temperature protection module is located between the preamplifier stage and the output driver stage of the error amplifier, and determines the load condition of the linear regulator by sampling the gate voltage of the output driver input tube MN1. Since the MOS tube of the micro-power linear regulator works in the sub-threshold region when the static state is zero or very light, the gate voltage EA_O1 of MN1 is very low, and the load detection module in the over-temperature protection module generates an enable signal en=1, turns off the PTAT voltage module and the voltage comparator module, and reduces the static power consumption. When the load increases, MN1 works in the saturation region, and its gate voltage EA_O1 increases. The load detection module in the over-temperature protection module generates an enable signal en=0, and the PTAT voltage module and the voltage comparator module start working and realize the detection of the chip temperature. When the chip junction temperature exceeds a certain threshold voltage, the voltage comparator outputs a high level, pulls the gate voltage of MN1 to the ground, and then turns off the power tube MP to realize the over-temperature protection function.

[0038] Figure 3 The figure shows a structure diagram of an over-temperature protection circuit suitable for an ultra-low power linear regulator according to the present invention, which is mainly composed of a load detection module, a PTAT voltage generation module and a voltage comparator module, and is powered by a low-voltage power supply VDD_L.

[0039] The load detection module is mainly used to detect the load state of the linear regulator. When the load of the linear regulator is zero, the EA_O1 voltage is very low, and the M20 drain outputs a high level, then the inverter INV1 outputs a low level, and similarly INV2 outputs a high level. Therefore, one input of the two-input NAND gate NAND is high, and the other input is connected to the voltage comparator output OTP_ctrn. When the power is just turned on or there is no overheating, OTP_ctrn is high, so the NAND output is low, that is, enb = "0", en = "1". At this time, under the action of the pull-down tubes M15, M16, M17 and the pull-up tubes M18, M19, the PTAT voltage generation module and the voltage comparator module are forced to shut down, thereby reducing the static power consumption of the linear regulator.

[0040] When the load of the linear regulator gradually increases, the EA_O1 voltage gradually increases, the M20 drain voltage gradually decreases, and the INV1 output gradually increases until the M24 tube is turned on to form a positive feedback, which quickly pulls the M20 drain voltage to the ground, the INV1 output becomes high, and the INV2 output is low. Then the NAND gate NAND output becomes high, that is, enb = "1", en = "0". At this time, the pull-down tube and the pull-up tube are both turned off, and the PTAT voltage generation module and the voltage comparator module start working.

[0041] Since logic circuits such as inverters and NAND gates will have relatively large transient currents when the level is flipped, it will cause a large impact on the low-voltage power supply VDD_L, thereby affecting the normal operation of its power supply circuit. Therefore, the transient current of the logic circuit must be reduced. This circuit uses a current limiting circuit composed of NMOS power consumption to achieve this function, that is, a current limiting circuit composed of NMOS power consumption is connected in series at the ground end of the logic circuit, such as Figure 4 and Figure 5 As shown in Figure 2, since the gate-source voltage of the NMOS consumption tube is fixed and the channel length modulation effect is ignored, when its source-drain voltage is greater than the gate-source voltage minus the threshold voltage, the current flowing through the NMOS consumption tube remains unchanged.

[0042] Figure 6 Shown are the transient current simulation results of the inverter with and without the NMOS power consumption limiting circuit described in the present invention. It can be seen from the figure that the current limiting circuit composed of the NMOS power consumption can greatly reduce the transient current of the logic circuit and improve the stability of the internal power supply.

[0043] The PTAT voltage generation module consists of two parts: a temperature detection circuit and a startup circuit.

[0044] The temperature detection circuit includes two parts: the current mirror self-bias circuit and the current mirror replication circuit. The current mirror self-bias circuit is composed of three-stage tubes Q1, Q2, resistor R1 and PMOS tubes M1, M2, which mainly generates a current IPTAT proportional to the absolute temperature. The current mirror replication circuit includes PMOS tube M3 and resistors R2, R3. M3 tube proportionally replicates the IPTAT current and generates a voltage VPTAT proportional to the temperature after flowing through the resistor, realizing real-time monitoring of the temperature.

[0045] Since the width-to-length ratio of M1 and M2 is 1:1, the collector currents of transistors Q1 and Q2 are equal, and the area ratio of Q1 and Q2 is n:1, so the base and emitter voltages of Q1 and Q2 can be expressed as:

[0046]

[0047]

[0048] Among them, I c represents the collector current of Q1 and Q2; V T =kTq is the thermovoltage, which is proportional to the absolute temperature, k is the Boltzmann constant, T is the thermodynamic temperature, q is the unit charge; n is the area ratio of Q1 and Q2; I s is the transistor saturation current constant.

[0049] Then the drain current flowing through M1 and M2 is equal to the current flowing through resistor R1, which can be expressed as:

[0050]

[0051] From formula (3), we can see that the drain current of M1 and M2 is proportional to the thermodynamic temperature T, so it is also called PTAT current. Since the width-to-length ratio of M3 tube is m:1:1 with that of M1 and M2 tubes, the current flowing through M3 tube is equal to:

[0052]

[0053] When the temperature is low, the collector output voltage OTP_ctrn of Q3 is high, the control switch tube M5 is turned on, and the resistor R3 is short-circuited, so the drain voltage of M3 is equal to:

[0054]

[0055] From the above formula, we can see that V temp The voltage is linearly related to the thermodynamic temperature and has a positive temperature coefficient, so the voltage can be used to characterize the chip temperature.

[0056] The drain output voltage of M3 is loaded on the base of Q3 as the input voltage of the voltage comparator. The voltage comparator includes a single-ended input comparator composed of Q3 and M4 and an inverter INV4.

[0057] When the temperature is low, V temp The voltage is lower than the turn-on voltage of transistor Q3, Q3 is cut off, the comparator output OTP_ctrn is high, and the inverter output OTP_ctr is low.

[0058] As the temperature gradually increases, V temp When the voltage is greater than the turn-on voltage of transistor Q3, Q3 is turned on, the comparator output OTP_ctrn becomes low, the inverter output OTP_ctr becomes high, and the linear regulator MN2 is controlled to turn on and pull down, thereby further turning off the power tube MP. At the same time, OTP_ctrn is fed back to the NAND gate input terminal in the load detection module, further locking the en voltage to keep it low, preventing the load from becoming zero at this time, causing the over-temperature protection module to be shut down by mistake.

[0059] Assume that the turn-on voltage of transistor Q3 is equal to V th When the temperature changes from low to high, it is easy to calculate the opening threshold temperature of the over-temperature protection module by formula (5):

[0060]

[0061] After over-temperature protection occurs, OTP_ctrn becomes low, M5 is disconnected, and V temp The voltage increases instantaneously, equal to:

[0062]

[0063] After over-temperature protection occurs, the power tube is turned off and the chip temperature gradually decreases. temp When the voltage drops below the turn-on voltage of Q3, OTP_ctrn becomes high, OTP_ctr becomes low, and the power circuit starts working again. Combining formula (7), the threshold temperature for the shutdown of the over-temperature protection module can be calculated as:

[0064]

[0065] By comparing equation (6) and equation (8), it can be seen that the turn-on threshold temperature of the over-temperature protection is greater than the turn-off threshold temperature, leaving a certain hysteresis interval to prevent thermal oscillation near the turn-on threshold temperature.

[0066] From the above analysis, it can be seen that the PTAT voltage generation module may be in the enabled and disabled state at any time. When the enable is turned on, in order to prevent the circuit from being in a degenerate state, a startup circuit must be used. The startup circuit consists of M9, M10, M11, M12, M13, M14 and capacitor C1.

[0067] When the enable is just turned on, the gate voltage of M13 is high, the gate voltages of M11 and M12 are low, and the gate voltage of M14 is also low, so the gate voltage of M10 is high, and the NMOS tube M10 is turned on. Since the M9 tube is a consumption tube, the threshold voltage is less than 0, so the M9 and M10 tube branches generate current to charge the capacitor C1, thereby lowering the gate voltage of M1, and the current mirror self-bias circuit leaves the degenerate state and starts to work.

[0068] When the current mirror self-bias circuit is started up, the gate voltage of M13 becomes low, and the gate voltages of M11 and M12 are pulled up. Since the width-to-length ratio of M11 is much larger than that of M14, the gate voltage of M10 is pulled down, the M10 tube is cut off, and the currents of the M9 and M10 branches are zero, which does not affect the operation of the current mirror self-bias circuit.

[0069] Figure 7The figure shows the simulation result of the over-temperature protection of the linear regulator at 1mA load described in the present invention. It can be seen from the figure that when the temperature is higher than 165°C, the over-temperature protection is turned on and the power tube is turned off; when the temperature is lower than 154°C again, the over-temperature protection is turned off and the power tube starts working again. Figure 8 The figure shows the simulation results of the over-temperature protection startup process of the linear regulator under different load conditions described in the present invention. It can be seen from the figure that when the load current is less than 10μA, the over-temperature protection module is in a dormant state to reduce system power consumption. At this time, the circuit has no over-temperature protection function.

[0070] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any modifications made according to the spirit of the main technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. An over-temperature protection circuit suitable for an ultra-low power linear regulator, characterized in that: It includes a load detection module, a PTAT voltage generation module and a voltage comparator, wherein: The load detection module is used to detect the load state of the linear regulator. When the load is zero, the load detection module outputs a control signal to turn off the PTAT voltage generation module and the voltage comparator, so that the over-temperature protection circuit is in a dormant state; when the load increases, the load detection module outputs a control signal to turn on the PTAT voltage generation module and the voltage comparator, monitors the regulator temperature and realizes the over-temperature protection function; The PTAT voltage generation module uses a self-biased current mirror structure to achieve real-time temperature detection, and the output voltage is directly proportional to the temperature; The voltage comparator uses a transistor single-ended input structure, and the comparator threshold voltage is equal to the BE junction turn-on voltage of the NPN transistor; The linear regulator includes a bandgap reference module, a high voltage pre-modulation module, an error amplifier, an over-temperature protection circuit, a power tube and a feedback resistor network; wherein: The high-voltage pre-modulation module converts the high-voltage input power supply VDD_H into a low-voltage power supply VDD_L that is weakly correlated with the high-voltage input power supply VDD_H, and supplies power to the error amplifier preamplifier stage and the over-temperature protection circuit; The error amplifier comprises a preamplifier stage and an output driver stage connected in sequence; the output driver stage is connected to control the on-off of the power tube, and the power tube is connected in series with a feedback resistor network; The bandgap reference module and the feedback resistor network are respectively connected to the two-phase input terminals of the preamplifier stage; The over-temperature protection circuit is connected between the preamplifier stage and the output driver stage of the error amplifier, and determines the load condition of the linear regulator by sampling the gate voltage of the output driver stage; The load detection module includes MOS tubes M20, M21, M22, M23, M24, inverters INV1, INV2, INV3 and NAND gates NAND; The MOS tubes M23, M22, and M20 are connected in series between the low-voltage power supply VDD_L and VSS in sequence, the gates of M20 and M21 are connected to the gate voltage EA_O1 of the output driver stage, the source of M21 is connected to VSS, the drain of M21 is connected to the drain of M20 through M24, the drain of M20 is also connected to the input end of the inverter INV1, the gate of M24 is connected to the output end of the inverter INV1, and the output end of INV1 is connected to the input end of INV2; the output end of INV2 and the output end OTP_ctrn of the voltage comparator are respectively connected to the two input ends of the NAND gate NAND, the output end enb of the NAND gate NAND is connected to the input end of the inverter INV3, and the output end of INV3 generates an enable signal en.

2. The over-temperature protection circuit suitable for an ultra-low power consumption linear regulator according to claim 1, characterized in that: The PTAT voltage generation module is composed of a temperature detection circuit and a startup circuit; the temperature detection circuit includes a current mirror self-bias circuit and a current mirror replication circuit; the current mirror self-bias circuit generates a current IPTAT proportional to the absolute temperature; the current mirror replication circuit replicates the IPTAT current in proportion and generates a voltage VPTAT proportional to the temperature after flowing through a resistor, thereby realizing real-time monitoring of the temperature; the startup circuit is used to prevent the PTAT voltage generation module from being in a degenerate state when it is enabled.

3. The over-temperature protection circuit suitable for an ultra-low power consumption linear regulator according to claim 2, characterized in that: The current mirror self-bias circuit of the temperature detection circuit includes transistors Q1, Q2, a resistor R1 and PMOS tubes M1, M2; the current mirror replication circuit includes a PMOS tube M3 and resistors R2, R3; the bases of the transistors Q1, Q2 are connected in common, the gates of the PMOS tubes M1, M2, M3 are connected in common, the PMOS tube M1, the transistor Q1, and the resistor R1 are connected in series between the low-voltage power supply VDD_L and VSS in sequence, the PMOS tube M2 and the transistor Q2 are connected in series between the low-voltage power supply VDD_L and VSS in sequence; the PMOS tube M3 and the resistors R2, R3 are connected in series between the low-voltage power supply VDD_L and VSS in sequence.

4. The over-temperature protection circuit suitable for an ultra-low power consumption linear regulator according to claim 3, characterized in that: The startup circuit includes M9, M10, M11, M12, M13, M14 and capacitor C1; when the enable is just turned on, the gate voltage of M13 is high, the gate voltages of M11 and M12 are low, and the gate voltage en of M14 is also low, the gate voltage of M10 is high, and the NMOS tube M10 is turned on; Since the M9 tube is a power dissipation tube and its threshold voltage is less than 0, the M9 and M10 tube branches generate current to charge the capacitor C1, thereby lowering the gate voltage of M1, and the current mirror self-bias circuit leaves the degenerate state and starts to work.

5. The over-temperature protection circuit suitable for an ultra-low power consumption linear regulator according to claim 4, characterized in that: When the current mirror self-bias circuit is started up, the gate voltage of M13 becomes low, and the gate voltages of M11 and M12 are pulled up. Since the width-to-length ratio of M11 is much larger than that of M14, the gate voltage of M10 is pulled down, the M10 tube is cut off, and the currents of the M9 and M10 branches are zero, which does not affect the operation of the current mirror self-bias circuit.

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