An equivalence verification device and method based on XMG combinational circuits

Abstract

The equivalence verification device based on the XMG combinational circuit disclosed by the present invention includes an input reading module, a Miter circuit construction module, a circuit structure conversion module, a constant substitution algorithm module, and an equivalence judgment module that are connected in sequence. By combining a constant substitution algorithm for the XOR nodes inside XMG that is more suitable for the XMG network, the present invention regards the XOR nodes inside XMG and their sub-circuits as Miter circuits for equivalence verification, divides the large circuit into small circuits, retains the topological information between the circuits, and significantly speeds up the calculation time. Compared with traditional equivalence verification tools, the present invention reduces the CPU calculation time and memory occupancy by 3097.03 times and 40.7% respectively, can not only reduce the equivalence verification time, but also reduce the memory consumption, and at the same time reduces the difficulty of calculating large-bit arithmetic circuits, which has strong practical significance for the development of the equivalence verification of combinational circuits.

Description

Technical Field

[0001] The present invention relates to the field of combinational circuit equivalence verification, and specifically to an equivalence verification device and method for combinational circuits based on XMG. Background Art

[0002] The automation of integrated circuit design (electronic design automation, EDA) has been highly modularized. The top-down design process includes system level, behavioral level, logic level, physical level, etc. Verification accompanies the entire EDA process, specifically including whether the design meets the specifications and whether the functions at different levels are equivalent. Verification can ensure the correctness of the functions of the designed product, reduce the risk of tape-out failure, and accelerate the time to market of the product. Considering the increasing design scale of integrated circuits, an efficient verification methodology is crucial.

[0003] Since the logic gate-level circuit description is accurate, it is often used for equivalence verification at different levels. The equivalence verification methods for gate-level circuits include functional and structural methods. The functional method is to obtain the canonical representation of the circuit to be detected through simulation or construction methods for the gate-level circuit to be detected, such as simulating the truth table and constructing the reduced ordered binary decision diagram (ROBDD) of the circuit. Canonical means that each Boolean function has a unique corresponding representation. Since both the truth table and the ROBDD representation have canonicality, it is only necessary to determine whether the canonical representations of the two circuits to be detected are the same to determine whether the circuits are equivalent. However, this method is only applicable to small-scale circuits. Whether it is the truth table or the ROBDD, when the circuit scale increases, there will be non-linear memory and time growth. The principle of the structural method is to find the possible equivalent nodes inside the circuit to be detected, and simplify the equivalence verification of large-scale circuits into the verification problems of multiple small-scale circuits. The commonly used method is to use a formal method based on a Boolean Satisfiability (SAT) solver to determine the equivalence of nodes.

[0004] Combinational circuits can be further divided into control logic circuits and arithmetic logic circuits. There is more research on the verification of control logic, and the difficulty is also lower. Arithmetic logic often involves word-level arithmetic operations with multiple bit widths. During verification, it is necessary to flatten the word-level operations into bit-level operations, which increases the verification difficulty. Traditional equivalence verification methods cannot verify multiplier circuits with a large bit width. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an equivalence verification device and method based on an XMG combinational circuit in view of the deficiencies of the prior art, which can not only reduce the equivalence verification time but also reduce the memory consumption of equivalence verification.

[0006] The technical solution adopted by the present invention to solve the above technical problems is as follows: An equivalence verification device based on an XMG combinational circuit includes an input reading module, a Miter circuit construction module, a circuit structure conversion module, a constant substitution algorithm module, and an equivalence judgment module that are connected in sequence.

[0007] The input reading module is used to respectively transmit the parsed data of the information files of the two circuits to be verified for equivalence to the open-source tool ALSO, and obtain the parsed data of the two circuits, wherein the two circuits are respectively represented by aig files storing circuit information.

[0008] The Miter circuit construction module is used to respectively construct circuit networks according to the parsed data of the two circuits obtained by the input reading module, connect the output ends of the circuit networks corresponding to the two circuits with XOR gates respectively, and then connect all the XOR gates with an OR gate to construct a Miter circuit, and use the output end of the OR gate as the total output end of the Miter circuit.

[0009] The circuit structure conversion module is used to convert the constructed Miter circuit into an XMG network structure.

[0010] The constant substitution algorithm module is used to perform constant substitution on the internal XOR nodes in the Miter circuit of the XMG network structure and output the substituted XMG network.

[0011] The equivalence judgment module is used to judge the equivalence of the two circuits according to the number of XOR nodes in the finally output XMG network.

[0012] An equivalence verification method based on an XMG combinational circuit includes the following steps:

[0013] 1) The input reading module reads the information files of the two circuits and transmits them to the open-source tool ALSO to obtain the parsed data of the two circuits.

[0014] 2) The Miter circuit construction module respectively constructs circuit networks according to the parsed data of the two circuits obtained by the input reading module, connects the output ends of the circuit networks corresponding to the two circuits with XOR gates respectively, and then connects all the XOR gates with an OR gate to construct a Miter circuit, and uses the output end of the OR gate as the total output end of the Miter circuit.

[0015] 3) The circuit structure conversion module converts the constructed Miter circuit into an XMG network structure;

[0016] 4) The constant replacement algorithm module performs constant replacement on the internal XOR nodes in the Miter circuit of the XMG network structure, and outputs the XMG network after replacement;

[0017] 5) The equivalence judgment module judges the equivalence of the two circuits according to the number of XOR nodes in the finally output XMG network.

[0018] Preferably, the specific process of step 1) is as follows: The input reading module reads the aig file containing the information of the two circuits and stores it to obtain the dataset of the AIG-network. The dataset of the AIG-network includes all types of nodes of the two circuits, the connection relationships between each node, and the number of original input terminals and original output terminals of the two circuits.

[0019] Preferably, the specific process of step 3) is as follows: The circuit structure conversion module first converts the constructed Miter circuit into a LUT network structure, and equivalently converts the LUT network structure into an XMG network structure by querying the optimal logic expression in the logic expression library of XMG.

[0020] Preferably, the specific process of step 4) is as follows: Traverse the internal XOR nodes in the Miter circuit of the XMG network structure. Treat each XOR node and its sub-nodes as a Miter circuit unit, convert it into CNF and hand it over to the SAT solver for solution. If it is SAT, jump to the next XOR node. If it is UNSAT, replace the current XOR node with the constant 0, and finally output the XMG network after replacement.

[0021] Preferably, the specific process of step 5) is as follows: Judge whether the number of XOR nodes in the finally output XMG network after traversing the XOR nodes is 0. If the number of nodes is 0, judge that the two circuits are equivalent. If the number of nodes is not 0, continue to hand it over to the SAT solver for solution and judge whether the two circuits are equivalent.

[0022] Compared with the prior art, the present invention has the following advantages:

[0023] 1) For the traditional equivalence verification tool, the time to find the equivalence of a 9-bit three-input adder multiplier is too long, exceeding 1 day. However, the equivalence verification device and method based on XMG combinational circuits proposed by the present invention reduces the verification difficulty of the multiplier, and significantly improves in terms of verification time and memory consumption.

[0024] 2) When verifying the equivalence of an 8-bit adder multiplier, the device and method of the present invention reduce the verification time and memory consumption by 15,151.5 times and 87.1% respectively compared with traditional equivalence verification tools. It can be seen that the equivalence verification device and method based on the XMG combinational circuit proposed by the present invention greatly improve the equivalence verification efficiency and at the same time reduce the computer memory consumed during calculation.

[0025] 3) By combining a constant substitution algorithm for XOR nodes inside XMG that is more suitable for the XMG network, regarding the XOR nodes and their sub-circuits inside XMG as a Miter circuit for equivalence verification, splitting the large circuit into small circuits, it retains the topological information between circuits and significantly speeds up the calculation time. Compared with traditional equivalence verification tools, the equivalence verification device and method based on the XMG combinational circuit proposed by the present invention reduce the difficulty of equivalence verification and are significantly improved in terms of the quality of satisfiable solutions and calculation speed: the equivalence verification device and method based on the XMG combinational circuit proposed by the present invention reduce the CPU calculation time and memory occupancy by 3,097.03 times and 40.7% respectively. It can be seen that the equivalence verification device and method based on the XMG combinational circuit proposed by the present invention greatly improve the equivalence verification efficiency and at the same time reduce the difficulty of calculating large-bit arithmetic circuits. The present invention provides a new research idea for the design of equivalence verification based on XMG combinational circuits, which can not only reduce the equivalence verification time, but also reduce memory consumption, and at the same time reduce the difficulty of calculating large-bit arithmetic circuits, and has strong practical significance for the development of equivalence verification of combinational circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the composition of the equivalence verification device based on the XMG combinational circuit in Embodiment 1;

[0027] Figure 2 Schematic diagram of the method for converting the Miter circuit in step 3) of Embodiment 2 into an XMG network structure;

[0028] Figure 3 Schematic diagram of the XMG structure rewriting of the DAG network in step 3) of Embodiment 2;

[0029] Figure 4 Schematic diagram of constant substitution for internal XOR nodes in the Miter circuit of the XMG network structure in step 4) of Embodiment 2. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The present invention will be further described in detail below in conjunction with the embodiments of the drawings.

[0031] Embodiment 1

[0032] An equivalence verification device based on an XMG combinational circuit, as Figure 1 shown, includes an input reading module 10, a Miter circuit construction module 20, a circuit structure conversion module 30, a constant replacement algorithm module 40, and an equivalence judgment module 50 that are connected in sequence. The input reading module 10 is used to respectively transmit the parsed data of the information files of the two circuits whose equivalence is to be verified to the open-source tool ALSO to obtain the parsed data of the two circuits. Among them, the two circuits are respectively represented by aig files storing circuit information. In this embodiment, the two circuits are two AIG circuits, represented by 1.aig101 and 2.aig102 respectively. The Miter circuit construction module 20 is used to respectively construct circuit networks according to the parsed data of the two circuits obtained by the input reading module 10, connect the output ends of the circuit networks corresponding to the two circuits with XOR gates respectively, and then connect all the XOR gates with OR gates to construct a Miter circuit, and use the output end of the OR gate as the total output end of the Miter circuit. The circuit structure conversion module 30 is used to convert the constructed Miter circuit into an XMG network structure. The constant replacement algorithm module 40 is used to perform constant replacement on the internal XOR nodes in the Miter circuit of the XMG network structure and output the replaced XMG network. The equivalence judgment module 50 is used to judge the equivalence of the two circuits according to the number of XOR nodes in the finally output XMG network.

[0033] Embodiment 2

[0034] For the equivalence verification problem of two input variables with a bit width of 8 bits for the arithmetic circuits (a + b)c and ac + bc to be verified, the equivalence verification method based on the XMG combinational circuit implemented by using the equivalence verification device of Embodiment 1 includes the following steps:

[0035] 1) The input reading module reads the information files of the two circuits and transmits them to the open-source tool ALSO to obtain the parsed data of the two circuits. The specific process is as follows: The input reading module reads and stores the aig file containing the information of the two circuits to obtain the dataset of the AIG-network. The dataset of the AIG-network includes all types of nodes of the two circuits, the connection relationships between each node, and the number of original input ends and original output ends of the two circuits.

[0036] 2) The Miter circuit construction module respectively constructs circuit networks according to the parsed data of the two circuits obtained by the input reading module, connects the output ends of the circuit networks corresponding to the two circuits with XOR gates respectively, and then connects all the XOR gates with OR gates to construct a Miter circuit, and uses the output end of the OR gate as the total output end of the Miter circuit.

[0037] 3) The circuit structure conversion module converts the constructed Miter circuit into an XMG network structure, as Figure 2 shown. The specific process is as follows: The circuit structure conversion module first converts the constructed Miter circuit into a LUT network structure, and then equivalently converts the LUT network structure into an XMG network structure by querying the optimal logic expression in the logic expression library of XMG.

[0038] In Embodiment 2, the constructed Miter circuit is a directed acyclic graph network DAG (Directed Acyclic Graph), as Figure 3 shown. First, a DAG network needs to be read, then the DAG network is converted into a LUT network structure, and finally, the LUT network structure is equivalently converted into an XMG network structure by querying the optimal logic expression in the logic expression library of XMG.

[0039] 4) The constant replacement algorithm module performs constant replacement on the internal XOR nodes in the Miter circuit of the XMG network structure and outputs the replaced XMG network. The specific process is as follows: Traverse the internal XOR nodes in the Miter circuit of the XMG network structure as shown in Figure 4 . Regard each XOR node and its 4 child nodes and 4 inputs as a Miter circuit unit, convert it into CNF and hand it over to the SAT solver for solution. If it is SAT, jump to the next XOR node; if it is UNSAT, replace the current XOR node with the constant 0. Finally, the replaced XMG network is output.

[0040] 5) The equivalence judgment module judges the equivalence of the two circuits according to the number of XOR nodes in the finally output XMG network. The specific process is as follows: Judge whether the number of XOR nodes in the finally output XMG network after traversing the XOR nodes is 0. If the number of nodes is 0, it is judged that the two circuits are equivalent; if the number of nodes is not 0, continue to hand it over to the SAT solver for solution and judge whether the two circuits are equivalent.

[0041] The equivalence verification device and method based on XMG combinational circuits proposed by the present invention, compared with the traditional equivalence verification tool ABC with the best performance (Mishchenko A, Chatterjee S, Brayton R, et al. Improvements to combinational equivalence checking[C] / / 2006 IEEE / ACM International Conference on Computer Aided Design: IEEE, 2006: 836 - 843.), reduce the calculation speed and memory occupancy by 3097.03 times and 40.7% on average respectively. The performance comparison between the equivalence verification device and method based on XMG combinational circuits proposed by the present invention and the traditional equivalence verification tool with the best performance is shown in Table 1.

[0042] Table 1

[0043]

[0044] By combining a constant substitution algorithm for XOR nodes inside XMG that is more suitable for XMG networks, the present invention regards the XOR nodes and their sub - circuits inside XMG as Miter circuits for equivalence verification, divides large circuits into small circuits, which retains the topological information between circuits and significantly speeds up the calculation time. Compared with traditional equivalence verification tools, the equivalence verification device and method based on XMG combinational circuits proposed by the present invention reduce the difficulty of equivalence verification and have obvious improvements in the quality of satisfiable solutions and calculation speed: the equivalence verification device and method based on XMG combinational circuits proposed by the present invention reduce the CPU calculation time and memory occupancy by 3097.03 times and 40.7% respectively. Thus, it can be seen that the equivalence verification device and method based on XMG combinational circuits proposed by the present invention greatly improve the equivalence verification efficiency and at the same time reduce the difficulty of calculating large - bit arithmetic circuits. The present invention provides a new research idea for the design of equivalence verification based on XMG combinational circuits, which can not only reduce the calculation time, but also reduce the memory occupancy, and at the same time reduce the difficulty of calculating large - bit arithmetic circuits, and has strong practical significance for the development of equivalence verification of combinational circuits.

Claims

1. An equivalence verification device based on an XMG combinational circuit, characterized in that, It includes an input reading module, a Miter circuit building module, a circuit structure conversion module, a constant substitution algorithm module, and an equivalence judgment module, which are connected in sequence. The input reading module is used to respectively transmit the parsed data of the information files of the two circuits to be verified for equivalence into the open-source tool ALSO, so as to obtain the parsed data of the two circuits. Among them, the two circuits are respectively represented by aig files storing circuit information. The Miter circuit building module is used to respectively build circuit networks according to the parsed data of the two circuits obtained by the input reading module, connect the output ends of the circuit networks corresponding to the two circuits with XOR gates respectively, and then connect all the XOR gates with an OR gate to build a Miter circuit, and use the output end of the OR gate as the total output end of the Miter circuit. The circuit structure conversion module is used to convert the built Miter circuit into an XMG network structure. The constant substitution algorithm module is used to perform constant substitution on the internal XOR nodes in the Miter circuit of the XMG network structure and output the substituted XMG network. The equivalence judgment module is used to judge the equivalence of the two circuits according to the number of XOR nodes in the finally output XMG network.

2. An equivalence verification method based on an XMG combinational circuit, characterized in that, It includes the following steps: 1) The input reading module reads the information files of the two circuits and transmits them into the open-source tool ALSO to obtain the parsed data of the two circuits. 2) The Miter circuit building module respectively builds circuit networks according to the parsed data of the two circuits obtained by the input reading module, connects the output ends of the circuit networks corresponding to the two circuits with XOR gates respectively, and then connects all the XOR gates with an OR gate to build a Miter circuit, and uses the output end of the OR gate as the total output end of the Miter circuit. 3) The circuit structure conversion module converts the built Miter circuit into an XMG network structure. 4) The constant substitution algorithm module performs constant substitution on the internal XOR nodes in the Miter circuit of the XMG network structure and outputs the substituted XMG network. 5) The equivalence judgment module judges the equivalence of the two circuits according to the number of XOR nodes in the finally output XMG network.

3. The equivalence verification method based on an XMG combinational circuit according to claim 2, characterized in that, The specific process of step 1) is as follows: The input reading module reads and stores the aig file containing the information of the two circuits to obtain the dataset of the AIG-network. The dataset of the AIG-network includes all types of nodes of the two circuits, the connection relationships between each node, and the number of original input ends and original output ends of the two circuits.

4. The equivalence verification method based on an XMG combinational circuit according to claim 2, characterized in that, The specific process of step 3) is as follows: The circuit structure conversion module first converts the built Miter circuit into a LUT network structure, and equivalently converts the LUT network structure into an XMG network structure by querying the optimal logical expression in the logical expression library of XMG.

5. The equivalence verification method based on an XMG combinational circuit according to claim 2, characterized in that, The specific process of step 4) is as follows: Traverse the internal XOR nodes in the Miter circuit of the XMG network structure. Treat each XOR node and its child nodes as a Miter circuit unit, convert it into CNF and hand it over to the SAT solver for solution. If it is SAT, jump to the next XOR node. If it is UNSAT, replace the current XOR node with the constant 0. Finally, output the replaced XMG network.

6. The equivalence verification method based on an XMG combinational circuit according to claim 2, characterized in that, The specific process of step 5) is as follows: Judge whether the number of XOR nodes in the finally output XMG network after traversing the XOR nodes is 0. If the number of nodes is 0, judge that the two circuits are equivalent. If the number of nodes is not 0, continue to hand it over to the SAT solver for solution and judge whether the two circuits are equivalent.

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