A SPICE model building method for superjunction MOSFET with limited safe operating area

Abstract

This invention discloses a method for establishing a superjunction MOSFET SPICE model with a safe operating area (SOA) limit, applicable to the field of electronic component modeling. Conventional power MOSFET SPICE models only use a reverse-biased diode to simulate fixed-value breakdown, thereby limiting the device's operating range. Based on the unique superposition electric field model of superjunction MOSFETs, this invention proposes a superjunction MOSFET SPICE model capable of simulating breakdown and thermal failure, helping to confirm whether superjunction MOSFET devices operate within their SOA range. Furthermore, the model can simulate device avalanche and short-circuit characteristics near the SOA boundary, accommodating superjunction MOSFET model verification and application circuit simulation under extreme electrical stress conditions.

Description

Technical Field

[0001] The present invention belongs to the field of electronic component modeling, and in particular relates to a method for establishing a super junction MOSFET SPICE model with a limited working area. Background Art

[0002] SPICE-based computer-aided design enables extensive virtual experimentation and testing, predicting the operating conditions of devices, circuits, and systems, and assisting in the development and design of circuit systems, achieving greater cost-effectiveness and shortening development cycles. High-precision SPICE device models are crucial for improving the design efficiency and applicability of application circuits.

[0003] Compared to traditional vertical power MOSFETs, superjunction MOSFET devices offer an optimized trade-off between withstand voltage and on-resistance due to their unique drift region structure featuring a periodic arrangement of PN columns. This uniqueness also makes the device mechanism and behavioral description unique, requiring the use of dedicated superjunction MOSFET SPICE models to accurately predict circuit and system behavior. As power management modules become increasingly complex and system integration increases, SPICE system simulations are increasingly demanding in terms of reliability and resistance to extreme stress environments. Superjunction MOSFET SPICE models, including reliability simulation design, will assist circuit designers in identifying design errors early in the simulation phase, enabling more rational device design and selection, and minimizing the need for reliability issues that can be introduced into manufacturing and lead to more costly consequences.

[0004] In actual engineering applications, it is necessary to define the SOA (safe operating area) to ensure that the device will never operate outside the defined limit limits, otherwise it will be impossible to achieve a reliable circuit design. Especially in typical switching power supply circuit applications, the power MOSFET will pass through the saturation region and withstand high voltage and current pulses in each switching cycle. When the switching frequency is reduced to achieve lower EMI, a longer pulse length will make the SOA limit range smaller. The means of confirming the applicability of power MOSFETs is mainly to collect and analyze device data from system simulation or plate making tests to determine whether each test item is within the maximum rating range, compare the SOA chart to determine whether the thermal stability limit and the maximum current limit of the package are exceeded, and confirm whether the average power consumption of the device under continuous pulses is within the rated range. The superjunction MOSFET device models currently provided by device manufacturers mainly serve to simulate circuits that maintain normal operation of the superjunction MOSFET. This basic model only reflects the blocking characteristics of the device using a reverse-biased diode, thereby limiting the device's operating range. This is far from sufficient to confirm whether the device is safe and reliable in circuit system simulations. At the same time, since this model does not describe the special electrical characteristics of the superjunction MOSFET near the SOA boundary, it limits the simulation of device application circuits under extreme electrical stress conditions, such as the verification of the avalanche and short-circuit characteristics of the superjunction MOSFET. Summary of the Invention

[0005] To address the above technical issues, the present invention proposes a method for establishing a superjunction MOSFET SPICE model with a limited safe operating area. In application circuit simulation, equivalent breakdown occurs when the operating current and voltage of the superjunction MOSFET exceed the maximum rating, allowable power, or thermal stability limit, thereby limiting the normal operating range of the device to within the SOA. This method also enables superjunction MOSFET model verification and application circuit simulation under extreme electrical stress conditions near the SOA boundary.

[0006] The technical solution adopted in the present invention is:

[0007] A method for establishing a super-junction MOSFET SPICE model with limited safe operating area includes the following steps:

[0008] S1. Take the super-junction MOSFET device product for which SPICE model development is to be performed. Confirm the absolute maximum ratings of the device under certain ambient temperature and pulse width operating conditions by testing and consulting the product manual. These include the maximum drain-source voltage, the maximum current capability determined by the package, and the maximum operating junction temperature. Also obtain the device's output characteristics, third-quadrant conduction characteristics, capacitance characteristics, and equivalent thermal network.

[0009] S2. Reversely extract the superjunction MOSFET cell structure and process parameters based on DC and capacitance test data;

[0010] S3. Based on the charge and electric field superposition model of the superjunction MOSFET, a calculation model for the relationship between the primary breakdown voltage and the secondary breakdown voltage and the drain-source current is established, as well as a calculation model for the relationship between the drain current and the drain-source voltage in the voltage range of the two breakdowns;

[0011] S4. Based on the physical breakdown model of superjunction MOSFET, establish a superjunction MOSFET equivalent circuit model that limits the safe operating area (SOA). With the DC conduction branch or the existing conventional superjunction MOSFET equivalent circuit as the core, design a circuit topology with the ability to limit the safe operating area (SOA) at the periphery, including the primary breakdown current and limiting branch, the secondary breakdown limiting branch, and the power limiting branch; establish a coupled thermal network circuit and a judgment circuit.

[0012] S5. Determine circuit parameters of the DC conduction branch, the primary breakdown current branch, the maximum drain-source voltage limiting branch, the secondary breakdown limiting branch, the power limiting branch, the determination circuit, and the equivalent thermal network based on the data from step S1 and the model calculation results from step S3;

[0013] S6. Determine the components, functions, and model parameters required in the SPICE model, write and package related branches as needed, and ultimately obtain a super-junction MOSFET module with a limited safe operating area (SOA) or a peripheral sub-circuit module with a limited safe operating area (SOA) that can be directly called in the SPICE simulator.

[0014] As a preferred embodiment, the process of reversely extracting the superjunction MOSFET cell structure and process parameters in step S2 is as follows:

[0015] Assume that the object of process parameter extraction is an ideal superjunction MOSFET device with charge balance, the PN column width pitch is W, the PN column extension or groove depth is L, the PN column doping concentration is N, the cell parallel length is Z; the product blocking voltage is BV DSS , the critical electric field is E c , according to the rectangular electric field distribution:

[0016] BV DSS ≈E C L Formula (1)

[0017] For the output capacitor C oss , at high drain-source voltage V h It gradually approaches a stable value, and the dielectric constant is ε. At this time, the superjunction drift region is almost fully depleted, and the value is approximately:

[0018]

[0019] For the Miller capacitance C rss , take Crss -V DS The turning voltage where the slope of the curve suddenly changes is the pinch-off voltage V pin , the depletion region formed by mutual depletion of PN columns is pinched off, and the elementary charge is q. The relationship between this voltage and column width and doping concentration is:

[0020]

[0021] Assuming the mobility is μ, the resistance Ron is approximately:

[0022]

[0023] The L, W, N, and Z of the superjunction MOSFET are extracted from equations (1)(2)(3)(4).

[0024] As a preferred method, the drift region of the superjunction MOSFET is assumed to be an ideal PN column with charge balance achieved by doping. As the drain current increases, the free electrons cause the equivalent concentration of the N column to decrease. At this time, the equivalent unbalanced PN column can be regarded as the superposition of a balanced PN column and a P-type semiconductor. Assume that the electron saturation velocity is v sat , the dielectric constant is ε, the saturation current I Dsat , electron current density J n for:

[0025]

[0026] The doping of P / N columns is N, and the equivalent N column concentration is N Deff , then the equilibrium PN column concentration N in the superposition model pn for:

[0027]

[0028] The superimposed P-type semiconductor concentration N pcon for:

[0029]

[0030] The voltage applied to the drift region balance PN column is the drain-source voltage V DS , P formed by superimposing P-type semiconductor + PN + The voltage difference between the two ends of the diode is 0, and the electric field peak E is formed at the bottom. peak for:

[0031]

[0032] When the electric field peak E peak Reaching the critical electric field E c A breakdown occurs, and the breakdown voltage BV1 decreases with the saturated drain current I Dsat Linear decrease:

[0033]

[0034] Avalanche multiplication generates a large number of electron-hole pairs at the N+N junction, and the generated electrons flow directly out of the drain; the generated hole current density J p Then the free electrons in the N column are compensated by the source contact hole through the P column and the P-body region, while the maximum electric field strength is maintained at the critical value E c Nearby, the relationship between hole current density and voltage in this stage is:

[0035]

[0036] Drain-source current I DS and drain-source voltage V DS The relationship is:

[0037]

[0038] When holes flow in the P-body base region parasitic resistance R pb When the voltage drop generated on the NPN junction exceeds the built-in potential of the PN junction, the parasitic NPN transistor turns on, electrons begin to be injected, and the current continues to increase. The area under the electric field distribution curve decreases, and the voltage drops rapidly, resulting in a negative differential resistance effect and secondary breakdown. At this time:

[0039] 0.6=ZWJ P R pb =R pb (I DS -I Dsat ) Formula (12)

[0040] The second breakdown voltage is BV2, which satisfies:

[0041]

[0042] It can be seen that the voltage BV2 has the same variation pattern as BV1, and decreases linearly with the drain current.

[0043] As a preferred embodiment, the super-junction MOSFET equivalent circuit model for limiting SOA in step S4 is specifically:

[0044] The DC conduction branch includes a first voltage-controlled current source G1, a second voltage-controlled current source G2, a first resistor R1 and a first voltage source V1, wherein G1, G2 and V1 are connected in series, and G2 is connected in parallel with R1; the primary breakdown current branch includes a first diode D1, a first current-controlled current source F1, a second voltage source V2, and a second resistor R2, wherein V2 is connected in series with R2 and then in parallel with F1, and the cathode of D1 is connected to the positive electrode of F1 and the anode of V2; the primary breakdown limiting branch includes a second diode D2; the secondary breakdown limiting branch is a third diode D3, a fourth diode D4 connected in series with the first current-controlled voltage source H1, wherein D3 and D4 are connected in reverse series; the power limiting branch is a fifth diode D5, a sixth diode D6 and a sixth diode D7. D6 is connected in series with the first current-controlled voltage source E1, wherein D5 and D6 are connected in reverse series; the anode of D1, the cathode of D2, the cathode of D3, and the cathode of D5 are connected to the positive electrode of G1 and are led out as the drain D; the negative electrode of V1, the negative electrode of F1, the anode of D2, the anode of H1, and the anode of E1 are connected, and the connection point is connected to the positive electrode of the third voltage source V3, and the negative electrode of V3 is led out as the source S; the first end of the third resistor R3 is led out as the gate G, and the second end is connected to the second end of R1; the judgment circuit is a second voltage-controlled voltage source E2, whose positive electrode is led out as the judgment terminal Judge, the negative electrode is grounded, its first end is led out as the judgment port, and the second end is led out to the ground; the thermal network is a universal multi-order Kaul network, the input of the Kaul network is the third voltage-controlled current source G3, and the negative electrode of G3 is led out as the junction temperature terminal T j ;

[0045] The superjunction MOSFET equivalent circuit model with limited safe operating area SOA includes the following internal circuit nodes: the connection point dc1 between G1 and G2, the connection point between G2 and R1 is dc2, the connection point between V1 and V3 is s0, the connection point between D1 and F1 is br1, the connection point between V2 and R2 is br2, the connection point between D3 and D4 is br21, the connection point between D4 and H1 is br22, the connection point between D5 and D6 is p1, and the connection point between D6 and E1 is p2.

[0046] As a preferred embodiment, step S5 is specifically as follows:

[0047] S51. Extract parameters of the first and third quadrant DC conduction characteristics based on the Simulink tool to determine the circuit parameters of the DC conduction branch:

[0048] The first voltage-controlled voltage source G1 characterizes the inherent MOSFET characteristics. Assume that the gain factor is β, the subthreshold coefficient ζ, n, and the threshold voltage is V TH , the effective drain-source voltage is V ds,eff , the gate-source voltage is V GS , the internal drain-source voltage is V Ds0 , the thermal voltage is V T , the overdrive voltage is Vdsat , the DC equation for the superjunction MOSFET used is:

[0049]

[0050] in

[0051]

[0052] The second voltage-controlled voltage source G2 characterizes the resistance characteristics of the drift region. The voltage across the drift region is V dc1_dc2 , the drift region resistance coefficients are r1 and r0:

[0053]

[0054] The first resistor R1 is a large resistor to increase convergence; the first voltage source V1 is 0V, used to read and call the DC conduction branch current value in SPICE; the third resistor R3 is a large resistor with the gate grounded. A DC conduction branch circuit is constructed in the Simulink tool. Using roughly extracted device parameters from the test data, a model calculation result of the device output characteristics is obtained through systematic calculation. The model parameters are fine-tuned and corrected until the model calculation result displayed on the oscilloscope substantially coincides with the test data, completing the parameter extraction of the DC conduction branch. Alternatively, an existing conventional superjunction MOSFET model can be directly used.

[0055] S52. Determine the parameters of the primary breakdown current branch circuit:

[0056] The first current-controlled current source F1 is used to introduce channel current. F1(X) indicates that the controlled source F1 is an electrical signal function controlled by X. I(X) represents the magnitude of the current flowing through the X element:

[0057] F1(I(V1))=I(V1) Formula (17)

[0058] The second resistor R2 is set to:

[0059]

[0060] The second voltage source V2 is set to:

[0061] V2=BV DSS Formula (19)

[0062] The first diode D1 acts as a clamp and its reverse bias withstand voltage is set to at least BV DSS , when VDS <BV1,V DS0 is the voltage difference between D and s0, satisfying the following relationship

[0063]

[0064] At this time, the first diode D1 is reverse biased, and the current can only flow in the loop composed of H1, V2, and R2. The diode reverse bias voltage V br1_D for:

[0065] V br1D =-I Ds0 R2-V Ds0 +BV DSS ≤BV DSS Formula (21)

[0066] When VDS>BV1, the first diode D1 is turned on, and the total current passing through F1, V2, and R2 is:

[0067]

[0068] Satisfy the relationship between drain current and drain-source voltage after primary breakdown;

[0069] S53. Determine the circuit parameters of the maximum drain-source voltage limiting branch:

[0070] The second diode D2 represents the body diode characteristics, and the reverse saturation current Is and parasitic resistance Rs parameters are extracted from the test data; the reverse bias withstand voltage is set to BV DSS ;

[0071] S54. Determine the parameters of the secondary breakdown limiting branch circuit:

[0072] The first current-controlled voltage source H1 is used to introduce a function related to the channel current. H1(X) indicates that the controlled source H1 is an electrical signal function controlled by X:

[0073]

[0074] The third diode D3 and the fourth diode D4 are connected in reverse series. Assume that the breakdown voltage of D3 and D4 is BV DSS , V br21D is the voltage between br21 and D. When the drain-source voltage of the device reaches or crosses the secondary breakdown point, the voltage across D3 is:

[0075]

[0076] The third diode D3 breaks down, and the fourth diode D4 provides a forward path for the large current. At the same time, it acts as a voltage divider when the source and drain of the device are forward biased, preventing current from passing through this branch.

[0077] S55. Determine the parameters of the device power consumption limiting branch circuit:

[0078] T j The voltage from the terminal to ground is V Tj, E1(X) indicates that the controlled source E1 is an electrical signal function controlled by X, and the first voltage-controlled voltage source E1 is set to:

[0079]

[0080] The fifth diode D5 and the sixth diode D6 are connected in series in reverse order. The maximum operating junction temperature is set to V Tj_max , V p1D The voltage difference between p1 and D is set, and the breakdown voltage of D5 and D6 is set to V Tj_max , when the device reaches or exceeds the maximum junction temperature, the voltage across D5 is:

[0081] V p1D =V Ds0 -(V Ds0 -V Tj )≥V Tj_max Formula (26)

[0082] The fifth diode D5 breaks down, and the sixth diode D6 provides a forward path for the large current. At the same time, it acts as a voltage divider when the source and drain of the device are forward biased, preventing current from passing through this branch.

[0083] S56, determining the parameters of the judgment circuit:

[0084] Assume the maximum current determined by the package is I max , E2(X) indicates that the controlled source E2 is an electrical signal function controlled by X, and the second voltage-controlled voltage source E2 is set to:

[0085] E2(V Ds0 ,V br21D ,V p1D ,I(V3))=(V Ds0 >BV DSS )(V br21D >BV DSS )(V p1D >V Tjmax )(I(V3)>I max )

[0086] Formula (27)

[0087] When the node output port voltage is 0, it means that the device working state has exceeded the safe working area;

[0088] S57. Determine the thermal network circuit parameters:

[0089] The capacitors and resistors in the multi-order Kaul network are matched one-to-one with the thermal capacitance and thermal resistance values ​​of the same-order Kaul network automatically calculated by the thermal test instrument in step S1; the input current source G3 of the Kaul network is:

[0090] G3=I(V3)VDs0 Formula (28)

[0091] Complete coupling with the electrical characteristic network.

[0092] The established computational models for the relationship between the primary and secondary breakdown voltages and the drain-source current, as well as the analytical model for the relationship between the drain current and the drain-source voltage within the voltage range of the two breakdowns, are based on the principle of electric field superposition in the superjunction drift region. Verified by TCAD simulation, they have clear physical meanings and can be used to roughly predict and pre-select the device's operating state before simulation.

[0093] The established superjunction MOSFET SPICE model for limiting SOA will cause the corresponding limiting branch to break down when the operating current and voltage exceed the maximum rating, allowable power or thermal stability limit, allowing the device to pass a rapidly increasing large current; the equivalent breakdown point is expressed as BV DSS Calculated for the reference point, and BV DSS The same is the safety limit for allowing work, which does not coincide with the test data of the actual breakdown point, but the margin between the test value and BV DSS The margin to the actual blocking voltage remains the same;

[0094] The core MOSFET conventional working equivalent circuit in the established SOA-limited superjunction MOSFET SPICE model can be the DC conduction branch of the coupling capacitor model, or a packaged complete superjunction MOSFET SPICE model that includes DC and AC models. The primary breakdown current and limiting branch, secondary breakdown limiting branch and power limiting branch, coupled thermal network circuit and judgment circuit can be packaged together with the superjunction MOSFET conventional model as required, or they can be used only as peripheral circuits for reliability limitation.

[0095] The established super-junction MOSFET SPICE model for limiting SOA defaults to room temperature as the working environment. When the working environment temperature changes or a dynamic thermal model needs to be coupled, equations (14) to (28) should be adjusted according to the temperature variation relationship of the device's electrical characteristics, thus completing the SOA rating adjustment process. SOAs with different pulse widths are also different. When performing repeated pulse simulation experiments, the average applied power must be within the corresponding thermal and temperature stability limits.

[0096] Compared with the prior art, the method for establishing a super-junction MOSFET SPICE model with limited SOA described in the present invention has the following advantages: the present invention can implement SOA limitation on the device operating range in SPICE simulation. When the operating current and voltage of the super-junction MOSFET exceed the maximum rating, allowable power or thermal stability limit, equivalent breakdown will occur, causing the device to flow a rapidly increasing large current, making the system unable to operate normally. At the same time, a judgment level can be used to prompt the designer that the device is at risk of failure; the present invention will assist R&D personnel in avoiding more design errors during the SPICE simulation design stage and save R&D costs; the present invention establishes a calculation model for the relationship between the primary breakdown voltage and the secondary breakdown voltage as a inverse of the drain-source current, as well as a calculation model for the relationship between the drain current and the drain-source voltage within the voltage range of the two breakdowns. The above analytical models are all obtained based on the physical principles of the device, and the corresponding topological model establishment and circuit parameter acquisition methods are highly portable and applicable to conventional super-junction MOSFET products; the super-junction MOSFET model described in the present invention can adapt to super-junction MOSFET model verification and application circuit simulation under extreme electrical stress conditions, such as simulating the avalanche and short-circuit characteristics of devices near the SOA boundary. BRIEF DESCRIPTION OF THE DRAWINGS

[0097] Figure 1 A flow chart of a method for establishing a superjunction MOSFET model for limiting SOA according to the present invention;

[0098] Figure 2(a)-Figure 2(d) The basic electrical characteristics of the super-junction MOSFET product of the embodiment are shown in Figure 2(a) output characteristic diagram, Figure 2(b) third quadrant conduction characteristic, Figure 2(c) capacitance characteristic, and Figure 2(d) equivalent thermal network.

[0099] Figure 3 It is a charge-balanced superjunction MOSFET cell structure;

[0100] Figure 4 It is the charge and electric field superposition model of superjunction MOSFET;

[0101] Figure 5 Schematic diagram of the IV output characteristics of a super-junction MOSFET simulated by the super-junction MOSFET simulation of the present invention;

[0102] Figure 6 The first quadrant IV characteristics of the superjunction MOSFET in a wide voltage range obtained by TCAD simulation in the embodiment, including the primary breakdown and secondary breakdown critical lines;

[0103] Figure 7 Schematic diagram of SOA of superjunction MOSFET;

[0104] Figure 8The equivalent circuit topology of the superjunction MOSFET model for limiting SOA of the present invention;

[0105] Figure 9 Content of the SOA-limited superjunction MOSFET SPICE model written for the embodiment;

[0106] Figure 10 The SOA-limited superjunction MOSFET SPICE model established for the embodiment simulates the IV characteristics of the superjunction MOSFET over a wide voltage range in the LTspice simulator. DETAILED DESCRIPTION

[0107] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0108] Example 1

[0109] This embodiment provides a method for establishing a superjunction MOSFET SPICE model with limited safe operating area, including the following steps:

[0110] S1. Take the super-junction MOSFET device product for which SPICE model development is to be performed. Confirm the absolute maximum ratings of the device under certain ambient temperature and pulse width operating conditions by testing and consulting the product manual. These include the maximum drain-source voltage, the maximum current capability determined by the package, and the maximum operating junction temperature. Also obtain the device's output characteristics, third-quadrant conduction characteristics, capacitance characteristics, and equivalent thermal network.

[0111] S2. Reversely extract the superjunction MOSFET cell structure and process parameters based on DC and capacitance test data;

[0112] S3. Based on the charge and electric field superposition model of the superjunction MOSFET, a calculation model for the relationship between the primary breakdown voltage and the secondary breakdown voltage and the drain-source current is established, as well as a calculation model for the relationship between the drain current and the drain-source voltage in the voltage range of the two breakdowns;

[0113] S4. Based on the physical breakdown model of superjunction MOSFET, establish a superjunction MOSFET equivalent circuit model that limits the safe operating area (SOA). With the DC conduction branch or the existing conventional superjunction MOSFET equivalent circuit as the core, design a circuit topology with the ability to limit the safe operating area (SOA) at the periphery, including the primary breakdown current and limiting branch, the secondary breakdown limiting branch, and the power limiting branch; establish a coupled thermal network circuit and a judgment circuit.

[0114] S5. Determine circuit parameters of the DC conduction branch, the primary breakdown current branch, the maximum drain-source voltage limiting branch, the secondary breakdown limiting branch, the power limiting branch, the determination circuit, and the equivalent thermal network based on the data from step S1 and the model calculation results from step S3;

[0115] S6. Determine the components, functions, and model parameters required in the SPICE model, write and package related branches as needed, and ultimately obtain a super-junction MOSFET module with a limited safe operating area (SOA) or a peripheral sub-circuit module with a limited safe operating area (SOA) that can be directly called in the SPICE simulator.

[0116] Example 2

[0117] like Figure 1 As shown, this embodiment provides a method for establishing a super junction MOSFET SPICE model with limited safe operating area, including the following steps:

[0118] S1. Take a super-junction MOSFET device product for SPICE model development. Assume that the operating temperature of the simulation setting is room temperature (25°C). Confirm the absolute maximum ratings of the product at this temperature by testing and consulting the product manual. The maximum drain-source voltage is 650V, the maximum current capability determined by the package is 70A, and the maximum operating junction temperature is 150°C. At the same time, obtain the output characteristics of the device (Figure 2(a), the third quadrant conduction characteristics (Figure 2(b), the capacitance characteristics (Figure 2(c), and the equivalent thermal network (Figure 2(d)).

[0119] S2. Based on the DC and capacitance test data, reversely extract the super-junction MOSFET cell structure and process parameters:

[0120] Approximate the product as Figure 3 The ideal superjunction MOSFET device with charge balance shown in the figure has a PN column width of W (cm), a PN column extension or a groove depth of L (cm), and a PN column doping concentration of N ( / cm -3 ), the parallel length of the cells is Z (cm); the product blocking voltage is BV DSS =650V, the critical electric field is E c =2×10 5 V / cm, from the rectangular electric field distribution:

[0121] BV DSS ≈E c L = 2 × 10 5 L=650V Formula (1)

[0122] For the output capacitor C oss , at high drain-source voltage V hIt gradually approaches a stable value, and the dielectric constant is ε is 1×10 - 12 F / cm, at this time the super junction drift region is almost fully depleted, and the value is approximately:

[0123]

[0124] For the Miller capacitance C rss , take C rss -V DS The turning voltage where the slope of the curve suddenly changes is the pinch-off voltage V pin , the depletion region formed by mutual depletion of PN columns is pinched off, and the elementary charge q is 1.6×10 -19 C, the relationship between this voltage and column width and doping concentration is:

[0125]

[0126] Assuming the mobility is μ, the resistance Ron is approximately:

[0127]

[0128] The superjunction MOSFET is extracted from equations (1)(2)(3)(4) with L=32.5um, W=6.79um, and N=2.55×10 15 cm -3 , Z=293cm;

[0129] S3. Based on Figure 4 The charge and electric field superposition model of the superjunction MOSFET is used to establish the calculation model of the relationship between the primary breakdown voltage and the secondary breakdown voltage as a function of the drain-source current, as well as the calculation model of the relationship between the drain current and the drain-source voltage in the voltage range of the two breakdowns: Specifically, it is assumed that the drift region of the superjunction MOSFET is an ideal PN column that is charge balanced by doping. As the drain current increases, the free electrons cause the equivalent concentration of the N column to decrease. At this time, the equivalent unbalanced PN column can be regarded as the superposition of a balanced PN column and a P-type semiconductor. Assume that the electron saturation velocity is v sat 1.05×10 7 cm / s, dielectric constant ε, saturation current I Dsat , electron current density J n for:

[0130]

[0131] The doping of P / N columns is N, and the equivalent N column concentration is N Deff , then the equilibrium PN column concentration N pn for:

[0132]

[0133] The superimposed P-type semiconductor concentration N pcon for:

[0134]

[0135] The voltage applied to the drift region balance PN column is the drain-source voltage V DS , P formed by superimposing P-type semiconductor + PN + The voltage difference between the two ends of the diode is 0, and the electric field peak E is formed at the bottom. peak for:

[0136]

[0137] When the saturated drain current density is Jn(cm --3 ), the peak value of the cell electric field E peak Reaching the critical electric field E c A breakdown occurs, and the breakdown voltage BV1 decreases with the saturation drain current I Dsat As increases , decreases linearly:

[0138]

[0139] Avalanche multiplication in N + A large number of electron-hole pairs are generated at the N junction, and the generated electrons flow directly out of the drain; the generated hole current density J p Then the free electrons in the N column are compensated by the source contact hole through the P column and the P-body region, while the maximum electric field strength is maintained at the critical value E c Nearby, the relationship between hole current density and voltage in this stage is:

[0140]

[0141] Drain-source current after breakdown I DS and drain-source voltage V DS The relationship is:

[0142]

[0143] When the voltage drop generated by the hole flow on the parasitic resistance of the P-body base region exceeds the built-in potential of the PN junction, the parasitic NPN transistor is turned on, electrons begin to be injected, and the current continues to increase. The area under the electric field distribution curve decreases, and the voltage drops rapidly, resulting in a negative differential resistance effect and secondary breakdown. pb =0.001Ω, then the secondary breakdown voltage is:

[0144] 0.6=ZWJ P R pb =R pb (IDS -I Dsat )=0.001(I DS -I Dsat ) Formula (12)

[0145] The second breakdown voltage is BV2, which satisfies:

[0146]

[0147] It can be seen that the voltage BV2 has the same change pattern as BV1, and decreases linearly with the drain current.

[0148] The schematic diagram of the IV output characteristics of the superjunction MOSFET simulated by this calculation model is shown in the figure below. Figure 5 As shown in the figure, after the primary breakdown, the drain current increases linearly until it reaches the secondary breakdown point and then breaks down. In fact, snap-back will occur after the secondary breakdown, which is easy to make the circuit simulation non-convergent in SPICE simulation. Therefore, it is assumed that after the secondary breakdown, the device will also pass a rapidly increasing large current, making the device no longer in normal working state. The S2 step is used to roughly extract the obtained superjunction cell parameters for TCAD simulation, and the first quadrant IV characteristics in a large voltage range are obtained as shown in the figure. Figure 6 As shown, it includes the primary breakdown and secondary breakdown critical lines;

[0149] S4, SOA diagram of super junction MOSFET is as follows Figure 7 As shown in Figure 1, to ensure reliable operation of the device, the current-voltage relationship should be limited to the region surrounded by the on-resistance, maximum package current, maximum power, thermal stability limit, and maximum inter-electrode voltage. Based on the physical breakdown model of the superjunction MOSFET obtained in step S3, a circuit topology with SOA limitation is designed as follows: Figure 8As shown, it includes establishing a DC conduction branch, a primary breakdown current and limiting branch, a secondary breakdown limiting branch and a power limiting branch; establishing a coupled thermal network circuit and a judgment circuit; the DC conduction branch includes a first voltage-controlled current source G1, a second voltage-controlled current source G2, a first resistor R1 and a first voltage source V1, wherein G1, G2 and V1 are connected in series, and G2 is connected in parallel with R1; the primary breakdown current branch includes a first diode D1, a first current-controlled current source F1, a second voltage source V2, and a second resistor R2, wherein V2 is connected in series with R2 and then in parallel with F1, and the cathode of D1 is connected to the positive electrode of F1 and the anode of V2; the primary breakdown limiting branch includes a second diode D2; the secondary breakdown limiting branch is a third diode D3, a fourth diode D4 connected in series with the first current-controlled voltage source H1, wherein D3, D 4 is connected in reverse series; the power limiting branch is a fifth diode D5, a sixth diode D6 connected in series with a first current-controlled voltage source E1, wherein D5 and D6 are connected in reverse series; the anode of D1, the cathode of D2, the cathode of D3, and the cathode of D5 are connected to the positive electrode of G1 and are led out as the drain D; the negative electrode of V1, the negative electrode of F1, the anode of D2, the anode of H1, and the anode of E1 are connected, and the connection point is connected to the positive electrode of the third voltage source V3, and the negative electrode of V3 is connected to the first end of the third resistor and led out as the source S; the second end of the third resistor R3 is led out as the gate G; the determination circuit is a second voltage-controlled voltage source E2, whose positive electrode is led out as the judgment terminal Judge, the negative electrode is grounded, its first end is led out as the judgment port, and the second end is led out to ground; the thermal network is a universal multi-order Kaul network, the input of the Kaul network is the third voltage-controlled current source G3, and the negative electrode of G3 is led out as the junction temperature terminal Tj;

[0150] The superjunction MOSFET equivalent circuit model with limited safe operating area SOA includes the following internal circuit nodes: the connection point dc1 between G1 and G2, the connection point dc2 between G2 and R1, the connection point s0 between V1 and V3, the connection point br1 between D1 and F1, the connection point br2 between V2 and R2, the connection point br21 between D3 and D4, the connection point br22 between D4 and H1, the connection point p1 between D5 and D6, and the connection point p2 between D6 and E1;

[0151] S5. Determine circuit parameters of the DC conduction branch, the primary breakdown current branch, the maximum drain-source voltage limiting branch, the secondary breakdown limiting branch, the power limiting branch, the determination circuit, and the equivalent thermal network based on the data from step S1 and the model calculation results from step S3;

[0152] S51. Extract the parameters of the first-quadrant output characteristics of the superjunction product using tools such as Simulink to determine the circuit parameters of the DC conduction branch:

[0153] The first voltage-controlled voltage source G1 characterizes the inherent MOSFET characteristics. Assume that the gain factor is β, the subthreshold coefficient ζ, n, and the threshold voltage is V TH , the effective drain-source voltage is V ds,eff , the gate-source voltage is V GS , the internal drain-source voltage is V Ds0 , the thermal voltage is V T The second voltage-controlled voltage source G2 characterizes the resistance characteristics of the drift region, and the voltage across the drift region is V dc1_dc2 , the drift region resistance coefficients are r1 and r0: the first resistor R1 is set to 10KΩ, which is a large resistor to increase convergence; the third resistor R3 is set to 1GΩ; the first voltage source V1 is 0V, used to read and call the DC conduction branch current value in SPICE; the DC conduction branch circuit is built in tools such as Simulink, using the device parameters roughly extracted from the test data, and the model calculation results of the device output characteristics are obtained through systematic calculation. The model parameters are fine-tuned and corrected until the model calculation results displayed on the oscilloscope basically coincide with the test data, completing the parameter extraction of the DC conduction branch. The DC equation of the superjunction MOSFET used by the first voltage-controlled voltage source G1 is finally obtained:

[0154]

[0155] in,

[0156] The second voltage-controlled voltage source G2 characterizes the resistance characteristics of the drift region. The voltage across the drift region is V dc1_dc2 , the drift region resistance coefficients are r1 and r0:

[0157]

[0158] The first resistor R1 is a large resistor to increase convergence; the first voltage source V1 is 0V, used to read and call the DC conduction branch current value in SPICE; the third resistor R3 is a large resistor with the gate grounded. A DC conduction branch circuit is constructed in a tool such as Simulink. Using roughly extracted device parameters from test data, a model calculation result of the device output characteristics is obtained through systematic calculation. The model parameters are fine-tuned and corrected until the model calculation result displayed on the oscilloscope substantially coincides with the test data, completing the parameter extraction of the DC conduction branch. Alternatively, an existing conventional superjunction MOSFET model can be directly used.

[0159] S52. Determine the parameters of the primary breakdown current branch circuit:

[0160] The first current-controlled current source F1 is used to introduce channel current. F1(X) indicates that the controlled source F1 is an electrical signal function controlled by X. I(X) represents the magnitude of the current flowing through the X element:

[0161] F1(I(V1)) = I(V1)) Equation (17)

[0162] The second resistor R2 is set to:

[0163]

[0164] The second voltage source V2 is set to:

[0165] V2 = BV DSS = 650V Equation (19)

[0166] The first diode D1 functions as a clamp, and its reverse bias breakdown voltage is set to at least BV DSS = 650V;

[0167] When VDS < BV1, the voltage difference VDS0 between D and s0 satisfies the following relationship:

[0168]

[0169] At this time, the first diode D1 is reverse biased, and the current can only flow in the loop composed of H1, V2, and R2. The reverse bias voltage V of the diode br1_D is:

[0170]

[0171] When VDS > BV1, at this time the first diode D1 conducts, and the total current passing through F1, V2, and R2 is:

[0172]

[0173] Satisfies the relationship between the drain current and the drain-source voltage after the first breakdown;

[0174] S53. Determine the circuit parameters of the maximum drain-source voltage limiting branch:

[0175] The second diode D2 characterizes the body diode characteristics. The reverse saturation current Is = 0.81A and the parasitic resistance Rs = 0.02Ω are extracted from the test data; the reverse bias breakdown voltage is set to BV DSS = 650V;

[0176] S54. Determine the circuit parameters of the secondary breakdown limiting branch:

[0177] The first current-controlled voltage source H1 is used to introduce a function related to the channel current. H1(X) represents that the controlled source H1 is an electrical signal function controlled by X:

[0178]

[0179] The third diode D3 and the fourth diode D4 are connected in reverse series. Assume that the breakdown voltage of D3 and D4 is BVDSS, Vbr21D is the voltage between br21 and D. When the drain-source voltage of the device reaches or crosses the secondary breakdown point, the voltage across D3 is:

[0180]

[0181] The third diode D3 breaks down, and the fourth diode D4 provides a forward path for the large current. At the same time, it acts as a voltage divider when the source and drain of the device are forward biased, preventing current from passing through this branch.

[0182] S55. Determine the parameters of the secondary breakdown limiting branch circuit:

[0183] The voltage between Tj and ground is V Tj , E1(X) indicates that the controlled source E1 is an electrical signal function controlled by X, and the first voltage-controlled voltage source E1 is set to:

[0184]

[0185] The fifth diode D5 and the sixth diode D6 are connected in series in reverse order. The maximum operating junction temperature is set to V Tj_max , V p1D is the voltage difference between p1 and D, and the maximum operating junction temperature is V Tj_max =150℃, set the breakdown voltage of D5 and D6 to V Tj_max , when the device reaches or exceeds the maximum junction temperature, the voltage across D5 is:

[0186] V p1D =V Ds0 -(V Ds0 -V Tj )≥V Tj_max =150℃ Formula (26)

[0187] The fifth diode D5 breaks down, and the sixth diode D6 provides a forward path for the large current. At the same time, it acts as a voltage divider when the source and drain of the device are forward biased, preventing current from passing through this branch.

[0188] S56, determining the parameters of the judgment circuit:

[0189] Assume the maximum current determined by the package is I max , E2(X) indicates that the controlled source E2 is an electrical signal function controlled by X, and the second voltage-controlled voltage source E2 is set to:

[0190] E2(V Ds0 ,V br21D ,V p1D ,I(V3))=(V Ds0 >BV DSS )(Vbr21D >BV DSS )(V p1D >V Tjmax )(I(V3)>I max )=(V Ds0 >650)(V br21D >650)(V p1D >150)(I(V3)>70)

[0191] Formula (27)

[0192] When the node output port voltage is 0, it means that the device working state has exceeded the safe working area;

[0193] S57. Determine the thermal network circuit parameters:

[0194] The capacitors and resistors in the multi-order Kaul network are matched one-to-one with the thermal capacitance and thermal resistance values ​​of the same-order Kaul network automatically calculated by the thermal test instrument in step S1; the input current source G3 of the Kaul network is:

[0195] G3=I(V3)V Ds0 Formula (28)

[0196] Complete coupling with the electrical characteristic network;

[0197] S6. Determine the components, functions, and model parameters to be used in the SPICE model, write and package the relevant branches as required, and finally obtain the SOA-limited superjunction MOSFET module that can be directly called in the SPICE simulator. Figure 9 As shown, or limit the peripheral sub-circuit modules of SOA. The simulation effect of the super-junction MOSFET SPICE model that limits SOA on the IV characteristics of super-junction MOSFET in a large voltage range in the LTspice simulator is shown as follows: Figure 10 shown.

[0198] In summary, the present invention provides a method for establishing a super-junction MOSFET SPICE model that limits SOA, which has the following advantages: the present invention can implement SOA limitation on the operating range of the device in SPICE simulation. When the operating current and voltage of the super-junction MOSFET exceed the maximum rating, allowable power or thermal stability limit, equivalent breakdown will occur, causing the device to flow a rapidly increasing large current, making the system unable to work normally. At the same time, a judgment level can be used to prompt the designer that the device is at risk of failure; the present invention will assist R&D personnel in avoiding more design errors in the SPICE simulation design stage and save R&D costs; the present invention establishes a calculation model for the relationship between the primary breakdown voltage and the secondary breakdown voltage as the drain-source current, and a calculation model for the relationship between the drain current and the drain-source voltage in the voltage range of the secondary breakdown. The above analytical models are all obtained based on the physical principles of the device, and the corresponding topological model establishment and circuit parameter acquisition methods are highly portable and applicable to conventional super-junction MOSFET products; the super-junction MOSFET model described in the present invention can adapt to super-junction MOSFET model verification and application circuit simulation under extreme electrical stress conditions, such as simulating the primary breakdown effect near the SOA boundary and the device avalanche and short-circuit characteristics outside the SOA region. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0199] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for establishing a superjunction MOSFET SPICE model with limited safe operating area, characterized in that The steps include: S1. Take the super-junction MOSFET device product for which SPICE model development is to be performed. Confirm the absolute maximum ratings of the device under certain ambient temperature and pulse width operating conditions by testing and consulting the product manual. These include the maximum drain-source voltage, the maximum current capability determined by the package, and the maximum operating junction temperature. Also obtain the device's output characteristics, third-quadrant conduction characteristics, capacitance characteristics, and equivalent thermal network. S2. Reversely extract the superjunction MOSFET cell structure and process parameters based on DC and capacitance test data; S3. Based on the charge and electric field superposition model of the superjunction MOSFET, a calculation model for the relationship between the primary breakdown voltage and the secondary breakdown voltage and the drain-source current is established, as well as a calculation model for the relationship between the drain current and the drain-source voltage in the voltage range of the two breakdowns; S4. Based on the physical breakdown model of superjunction MOSFET, establish a superjunction MOSFET equivalent circuit model that limits the safe operating area (SOA). With the DC conduction branch or the existing conventional superjunction MOSFET equivalent circuit as the core, design a circuit topology with the ability to limit the safe operating area (SOA) at the periphery, including the primary breakdown current and limiting branch, the secondary breakdown limiting branch, and the power limiting branch; establish a coupled thermal network circuit and a judgment circuit. S5. Determine circuit parameters of the DC conduction branch, the primary breakdown current branch, the maximum drain-source voltage limiting branch, the secondary breakdown limiting branch, the power limiting branch, the determination circuit, and the equivalent thermal network based on the data from step S1 and the model calculation results from step S3; S6. Determine the components, functions, and model parameters required in the SPICE model, write and package related branches as needed, and ultimately obtain a super-junction MOSFET module with a limited safe operating area (SOA) or a peripheral sub-circuit module with a limited safe operating area (SOA) that can be directly called in the SPICE simulator.

2. A method for establishing a superjunction MOSFET SPICE model with limited safe operating area according to claim 1, characterized in that The process of reversely extracting the superjunction MOSFET cell structure and process parameters in step S2 is as follows: Assume that the object of process parameter extraction is an ideal superjunction MOSFET device with charge balance, the PN column width pitch is W, the PN column extension or groove depth is L, the PN column doping concentration is N, the cell parallel length is Z; the product blocking voltage is BV DSS , the critical electric field is E c , according to the rectangular electric field distribution: BV DSS ≈E C L Formula (1) For the output capacitor C oss , at high drain-source voltage V h It gradually approaches a stable value, and the dielectric constant is ε. At this time, the superjunction drift region is almost fully depleted, and the value is approximately: For the Miller capacitance C rss , take C rss -V DS The turning voltage where the slope of the curve suddenly changes is the pinch-off voltage V pin , the depletion region formed by mutual depletion of PN columns is pinched off, and the elementary charge is q. The relationship between this voltage and column width and doping concentration is: Assuming the mobility is μ, the resistance Ron is approximately: The L, W, N, and Z of the superjunction MOSFET are extracted from equations (1)(2)(3)(4).

3. A method for establishing a superjunction MOSFET SPICE model with limited safe operating area according to claim 2, characterized in that Step S3 is as follows: Assume that the drift region of the superjunction MOSFET is an ideal PN column that is charge balanced by doping. As the drain current increases, the free electrons cause the equivalent concentration of the N column to decrease. The equivalent unbalanced PN column at this time can be regarded as the superposition of a balanced PN column and a P-type semiconductor. Assume that the electron saturation velocity is v sat , the dielectric constant is ε, the saturation current I Dsat , electron current density J n for: The doping of P / N columns is N, and the equivalent N column concentration is N Deff , then the equilibrium PN column concentration N in the superposition model pn for: The superimposed P-type semiconductor concentration N pcon for: The voltage applied to the drift region balance PN column is the drain-source voltage V DS , P formed by superimposing P-type semiconductor + PN + The voltage difference between the two ends of the diode is 0, and the electric field peak E is formed at the bottom. peak for: When the electric field peak E peak Reaching the critical electric field E c A breakdown occurs, and the breakdown voltage BV1 decreases with the saturated drain current I Dsat Linear decrease: Avalanche multiplication generates a large number of electron-hole pairs at the N+N junction, and the generated electrons flow directly out of the drain; the generated hole current density J p Then the free electrons in the N column are compensated by the source contact hole through the P column and the P-body region, while the maximum electric field strength is maintained at the critical value E c Nearby, the relationship between hole current density and voltage in this stage is: Drain-source current I DS and drain-source voltage V DS The relationship is: When holes flow in the P-body base region parasitic resistance R pb When the voltage drop generated on the NPN junction exceeds the built-in potential of the PN junction, the parasitic NPN transistor turns on, electrons begin to be injected, and the current continues to increase. The area under the electric field distribution curve decreases, and the voltage drops rapidly, resulting in a negative differential resistance effect and secondary breakdown. At this time: 0.6=ZWJ P R pb =R pb (I DS -I Dsat ) Formula (12) The second breakdown voltage is BV2, which satisfies: It can be seen that the voltage BV2 has the same variation pattern as BV1, and decreases linearly with the drain current.

4. The method for establishing a super-junction MOSFET SPICE model with limited safe operating area according to claim 3, wherein: The equivalent circuit model of the superjunction MOSFET for limiting the safe operating area SOA in step S4 is specifically: The DC conduction branch includes a first voltage-controlled current source G1, a second voltage-controlled current source G2, a first resistor R1 and a first voltage source V1, wherein G1, G2 and V1 are connected in series, and G2 is connected in parallel with R1; the primary breakdown current branch includes a first diode D1, a first current-controlled current source F1, a second voltage source V2, and a second resistor R2, wherein V2 is connected in series with R2 and then in parallel with F1, and the cathode of D1 is connected to the positive electrode of F1 and the anode of V2; the primary breakdown limiting branch includes a second diode D2; the secondary breakdown limiting branch is a third diode D3, a fourth diode D4 connected in series with the first current-controlled voltage source H1, wherein D3 and D4 are connected in reverse series; the power limiting branch is a fifth diode D5, a sixth diode D6 and a sixth diode D7. D6 is connected in series with the first current-controlled voltage source E1, wherein D5 and D6 are connected in reverse series; the anode of D1, the cathode of D2, the cathode of D3, and the cathode of D5 are connected to the positive electrode of G1 and are led out as the drain D; the negative electrode of V1, the negative electrode of F1, the anode of D2, the anode of H1, and the anode of E1 are connected, and the connection point is connected to the positive electrode of the third voltage source V3, and the negative electrode of V3 is led out as the source S; the first end of the third resistor R3 is led out as the gate G, and the second end is connected to the second end of R1; the judgment circuit is a second voltage-controlled voltage source E2, whose positive electrode is led out as the judgment terminal Judge, the negative electrode is grounded, its first end is led out as the judgment port, and the second end is led out to the ground; the thermal network is a universal multi-order Kaul network, the input of the Kaul network is the third voltage-controlled current source G3, and the negative electrode of G3 is led out as the junction temperature terminal T j ; The superjunction MOSFET equivalent circuit model with limited safe operating area SOA includes the following internal circuit nodes: the connection point dc1 between G1 and G2, the connection point between G2 and R1 is dc2, the connection point between V1 and V3 is s0, the connection point between D1 and F1 is br1, the connection point between V2 and R2 is br2, the connection point between D3 and D4 is br21, the connection point between D4 and H1 is br22, the connection point between D5 and D6 is p1, and the connection point between D6 and E1 is p2.

5. The method for establishing a super junction MOSFET SPICE model with limited safe operating area according to claim 4, wherein: Step S5 is specifically as follows: S51. Extract parameters of the first and third quadrant DC conduction characteristics based on the Simulink tool to determine the circuit parameters of the DC conduction branch: The first voltage-controlled voltage source G1 characterizes the inherent MOSFET characteristics. Assume that the gain factor is β, the subthreshold coefficient ζ, n, and the threshold voltage is V TH , the effective drain-source voltage is V ds,eff , the gate-source voltage is V GS , the internal drain-source voltage is V Ds0 , the thermal voltage is V T , the overdrive voltage is V dsat , the DC equation for the superjunction MOSFET used is: in The second voltage-controlled voltage source G2 characterizes the resistance characteristics of the drift region. The voltage across the drift region is V dc1_dc2 , the drift region resistance coefficients are r1 and r0: The first resistor R1 is a large resistor to increase convergence; the first voltage source V1 is 0V, which is used to read and call the DC conduction branch current value in SPICE; The third resistor R3 is a large resistor that connects the gate to ground. A DC conduction branch circuit is constructed in the Simulink tool. Using roughly extracted device parameters from the test data, a systematic calculation is performed to obtain a model calculation result of the device output characteristics. The model parameters are fine-tuned and corrected until the model calculation result displayed on the oscilloscope substantially matches the test data, completing the parameter extraction of the DC conduction branch. Alternatively, an existing conventional superjunction MOSFET model can be directly used. S52. Determine the parameters of the primary breakdown current branch circuit: The first current-controlled current source F1 is used to introduce channel current. F1(X) indicates that the controlled source F1 is an electrical signal function controlled by X. I(X) represents the magnitude of the current flowing through the X element: F1(I(V1))=I(V1) Formula (17) The second resistor R2 is set to: The second voltage source V2 is set to: V2=BV DSS Formula (19) The first diode D1 acts as a clamp and its reverse bias withstand voltage is set to at least BV DSS , when VDS <BV1,V DS0 is the voltage difference between D and s0, satisfying the following relationship At this time, the first diode D1 is reverse biased, and the current can only flow in the loop composed of H1, V2, and R2. The diode reverse bias voltage V br1_D for: V br1D =-I Ds0 R2-V Ds0 +BV DSS ≤BV DSS Formula (21) When VDS>BV1, the first diode D1 is turned on, and the total current passing through F1, V2, and R2 is: Satisfy the relationship between drain current and drain-source voltage after primary breakdown; S53. Determine the circuit parameters of the maximum drain-source voltage limiting branch: The second diode D2 represents the body diode characteristics, and the reverse saturation current Is and parasitic resistance Rs parameters are extracted from the test data; the reverse bias withstand voltage is set to BV DSS ; S54. Determine the parameters of the secondary breakdown limiting branch circuit: The first current-controlled voltage source H1 is used to introduce a function related to the channel current. H1(X) indicates that the controlled source H1 is an electrical signal function controlled by X: The third diode D3 and the fourth diode D4 are connected in reverse series. Assume that the breakdown voltage of D3 and D4 is BV DSS , V br21D is the voltage between br21 and D. When the drain-source voltage of the device reaches or crosses the secondary breakdown point, the voltage across D3 is: The third diode D3 breaks down, and the fourth diode D4 provides a forward path for the large current. At the same time, it acts as a voltage divider when the source and drain of the device are forward biased, preventing current from passing through this branch. S55. Determine the parameters of the device power consumption limiting branch circuit: T j The voltage from the terminal to ground is V Tj , E1(X) indicates that the controlled source E1 is an electrical signal function controlled by X, and the first voltage-controlled voltage source E1 is set to: The fifth diode D5 and the sixth diode D6 are connected in series in reverse order. The maximum operating junction temperature is set to V Tj_max , V p1D The voltage difference between p1 and D is set, and the breakdown voltage of D5 and D6 is set to V Tj_max , when the device reaches or exceeds the maximum junction temperature, the voltage across D5 is: V p1D = V Ds0 -(V Ds0 - V Tj ) ≥ V Tj_max Formula (26) The fifth diode D5 breaks down, and the sixth diode D6 provides a forward path for the large current. At the same time, it acts as a voltage divider when the source and drain of the device are forward biased, preventing current from passing through this branch. S56, determining the parameters of the judgment circuit: Assume the maximum current determined by the package is I max , E2(X) indicates that the controlled source E2 is an electrical signal function controlled by X, and the second voltage-controlled voltage source E2 is set to: E2(V Ds0 ,V br21D ,V p1D ,I(V3))=(V Ds0 >BV DSS )(V br21D >BV DSS )(V p1D >V Tjmax )(I(V3)>I max ) Formula (27) When the node output port voltage is 0, it means that the device working state has exceeded the safe working area; S57. Determine the thermal network circuit parameters: The capacitors and resistors in the multi-order Kaul network are matched one-to-one with the thermal capacitance and thermal resistance values ​​of the same-order Kaul network automatically calculated by the thermal test instrument in step S1; the input current source G3 of the Kaul network is: G3=I(V3)V Ds0 Formula (28) Complete the coupling with the electrical characteristic network.

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