A hardware implementation method for reducing the number of pulse neural network neuron calculations

Abstract

The application discloses a hardware implementation method for reducing the calculation times of neurons in a spiking neural network, which can be used for hardware implementation of neuron circuits in the spiking neural network. When a digital circuit processes an input pulse signal, the method first judges whether a connection weight value is less than or equal to a fixed threshold value, and if the connection weight value is less than or equal to the fixed threshold value, the corresponding neuron will not update its membrane voltage. The method reduces the calculation times of neurons, reduces the access times of the membrane voltage in the memory, and reduces the hardware power consumption. The application discloses a hardware implementation method for reducing the calculation times of neurons in a spiking neural network, which is directed to neural network hardware acceleration, reduces the use times of a circuit memory, reduces the calculation times of neurons, improves the calculation efficiency, and has the characteristics of low power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to a method for reducing the number of neuron membrane voltage access times in a pulse neural network digital circuit, belonging to the field of digital integrated circuit design. The present application is mainly used for the digital circuit of the pulse neural network. BACKGROUND

[0002] Convolutional neural networks are an efficient way to solve computer vision tasks, but they require a large number of multiply-accumulate operations due to their frame-driven convolution operations and complex computing units, resulting in high power consumption. The third generation of artificial neural networks, called spiking neural networks, has greatly reduced operation and hardware power consumption due to their sparse pulse transmission and brain-like computing operations. The structure of the spiking convolutional neural network is similar to that of the convolutional neural network, but the basic computing unit and the data transmitted between the computing units use brain-like neurons and unit pulse data of the spiking neural network.

[0003] Many researchers at home and abroad have conducted a series of research on the processor of the spiking neural network. According to the implementation method of the spiking neural network circuit, it can be divided into digital circuit and analog circuit. The BrainScaleS chip and the SpiNNaker chip in Europe are based on analog circuit chips. The TrueNorth chip of IBM and the "Darwin" chip of Zhejiang University belong to chips implemented by digital circuit. According to the processing method of data, it can be divided into frame-driven spiking neural network processor and event-driven spiking convolutional neural network processor. For frame-driven spiking neural network processors, the Neurogrid chip of Stanford University and the Loihi chip of Intel are both support configurable architecture to implement real-time processing of visual sensor information, and they can support interconnection of millions of neurons. Ju of Sichuan University developed a multi-layer spiking neural network architecture and implemented handwriting digit recognition on a programmable logic array. For event-driven spiking convolutional neural network processors, Serrano designed an event-driven digital-analog hybrid chip to process 16x16 pixel images, which can implement single-channel convolution operation. Tapiador-Morales designed a fully digital spiking convolutional structure and implemented it on an FPGA, which can support up to 64-channel convolution processing.

[0004] The number of neurons in the spiking neural network is huge, and the calculation of the neurons is mainly the calculation of the membrane voltage of the neurons. In the digital circuit of the spiking neural network, the storage space required by the membrane voltage of the neurons is large, and the membrane voltage is generally stored in a storage (such as a register group, a random access memory, etc.). When the membrane voltage needs to be calculated, the stored membrane voltage needs to be read out, and after calculation, the updated membrane voltage value is written back to the storage. The calculation of the neurons requires a large number of operations on the storage, resulting in high power consumption. Therefore, a hardware implementation method for reducing the number of neuron calculations in the spiking neural network is proposed, which reduces the number of neuron updates, the number of accesses to the membrane voltage, and the power consumption of the neuron calculation unit. SUMMARY

[0005] The purpose of the present application is to reduce the power consumption of the digital circuit of the spiking neural network by reducing the number of neuron calculations.

[0006] A hardware implementation method for reducing the number of neuron calculations in the spiking neural network includes the following steps:

[0007] S1: Set the weight threshold k th , set the neuron threshold v th , set the leakage value v leak . Set the timer, and when the digital circuit starts to work, the timer works.

[0008] S2: Determine whether the timer has increased by a fixed value. If yes, jump to S13, otherwise jump to S3.

[0009] S3: Input a presynaptic neuron pulse signal to the digital circuit of the spiking neural network.

[0010] S4: According to the connection relationship of the spiking neural network, calculate the connection weight values of the presynaptic neuron and N post-synaptic neurons stored in the address of the storage, and calculate the membrane voltage of the N post-synaptic neurons stored in the address of the storage.

[0011] S5: Take out N connection weight values according to the address calculated in step four.

[0012] S6: Compare the N connection weight values with the set weight threshold k th , and obtain an N-bit masking signal data. If one of the connection weight values is less than or equal to the weight threshold, the value at the corresponding position of the masking signal data is 1, otherwise the value at the corresponding position is 0. The number of 1s in the masking signal data is represented by M.

[0013] S7: If all the connection weight values in step six are less than or equal to the weight threshold, jump to S4.

[0014] S8: the membrane voltage of the last N post-synaptic neurons is calculated and stored in the address of the memory.

[0015] S9: the connection weight value taken out in S5 and the membrane voltage value taken out in S8 are added according to the corresponding relationship to obtain N-M calculation results.

[0016] S10: the N-M calculation results in S9 are compared with the neuron threshold value respectively, if the membrane voltage is greater than or equal to the neuron threshold value, the membrane voltage is reset to the reset value v reset , otherwise the membrane voltage value remains unchanged.

[0017] S11: according to the address calculated in S4, the new calculation result in S10 is written into the memory at the address.

[0018] S12: it is judged whether the D neurons have completed the update of the membrane voltage, if yes, jump to S2, otherwise, jump to S4.

[0019] S13: the leak operation is implemented on the neuron membrane voltage, all the membrane voltages in the memory are taken out, the membrane voltage value is subtracted by the fixed leak value v leak , and the leaked membrane voltage is written back to the memory.

[0020] The connection relationship between the neurons in the application is that each pre-synaptic neuron is connected with D post-synaptic neurons, and D≥1.

[0021] The neuron model described in the application is an integral leaky firing neuron model (LIF neuron model), the adjustment of the neuron membrane voltage and the firing of the pulse are in a functional relationship with whether the pre-synaptic neuron generates a pulse and the size of the connection weight, and the typical integral leaky neuron model function is as follows:

[0022]

[0023] V i (t)=v reset and S i (t)=1, if V i (t)≥V th

[0024] Wherein, V i (t) is the membrane voltage of neuron i at time t, S j (t) represents whether neuron j generates a pulse at time t, and S jThe value of (t) has two possibilities: 1 or 0. If it is 1, it means that neuron j generated one pulse at time t; if it is 0, it means that neuron j did not generate a pulse at time t. ij This represents the connection weight between neuron i and neuron j. leak This indicates the leakage value that a neuron needs to leak after fixed time intervals. It represents the membrane voltage V at time t for neuron i. i (t) is greater than or equal to a fixed neuron threshold V th At that time, neuron i generates a pulse S. i (t), and its membrane voltage is reset to the reset value v. reset .

[0025] Compared with the prior art, the present invention has the following beneficial effects: The present invention is a hardware implementation method for reducing the number of calculations of neurons in a spiking neural network. This technology is geared towards hardware acceleration of neural networks, reduces the number of times circuit memory is used, improves computational efficiency, and has the characteristics of low power consumption. Attached Figure Description

[0026] Figure 1 This diagram illustrates the specific implementation steps of the hardware implementation method for reducing the number of computations by neurons in a spiking neural network, as designed in this invention. Detailed Implementation

[0027] The present invention will be further described below with reference to embodiments, and the embodiments of the present invention include, but are not limited to, the following embodiments.

[0028] Example:

[0029] In this embodiment, the neuronal connectivity is assumed to be one presynaptic neuron connected to nine postsynaptic neurons. The neuronal membrane voltage calculation method designed in this invention includes the following specific steps:

[0030] S1: Set the weight threshold k th Set the neuron threshold v th Set the leakage value v leak The timer is set to start operating when the digital circuit begins working.

[0031] S2: Determine if the timer has increased by a fixed value of 1ms. If yes, proceed to step S13; otherwise, proceed to step S3.

[0032] S3: Input the pulse signal of the presynaptic neuron into the spiking neural network digital circuit. This presynaptic neuron is connected to 9 postsynaptic neurons.

[0033] S4: Based on the connection relationship of the spiking neural network, calculate the connection weight values ​​of the presynaptic neuron and the three postsynaptic neurons and store them in the memory address. At the same time, calculate the membrane voltage of the three postsynaptic neurons and store it in the memory address.

[0034] S5: Extract 3 connection weight values ​​based on the address calculated in S4.

[0035] S6: Combine the three connection weight values ​​with the set weight threshold k. th The comparison yields a 3-bit shielding signal data. If any connection weight value is less than or equal to the weight threshold, the corresponding position in the shielding signal data is set to 1; otherwise, the corresponding position is set to 0. The number of 1s in the shielding signal data is denoted by M, where (0 ≤ M ≤ 3).

[0036] S7: If all connection weights in S6 are less than or equal to the weight threshold, i.e., M=3, jump to S12.

[0037] S8: Calculate the membrane voltages of the last three synaptic neurons and store them in memory. Based on the masking signal data generated in S6, if a certain bit is 1, the corresponding membrane voltage value will not be read from memory; otherwise, the membrane voltage at the corresponding position needs to be read. Therefore, the number of membrane voltages read is 3-M.

[0038] S9: Add the connection weight values ​​taken from S5 and the membrane voltage values ​​taken from S8 according to the corresponding relationship to obtain 3-M calculation results.

[0039] S10: Compare the 3-M calculation results from S9 with the neuron threshold. If the membrane voltage is greater than or equal to the neuron threshold, reset the membrane voltage to the reset value v. reset Otherwise, the membrane voltage value remains unchanged.

[0040] S11: Based on the address calculated in S4, write the new calculation result in S10 into the memory at that address.

[0041] S12: Determine if all 9 neurons have completed the membrane voltage update. If yes, jump to S2; otherwise, jump to S4.

[0042] S13: Retrieve the membrane voltage from the memory and subtract the fixed leakage value v from the membrane voltage value. leak The leaked membrane voltage is then rewritten into memory.

[0043] In traditional neuron calculation methods for spiking neural networks, neuron calculation requires simultaneously retrieving the neuron membrane voltage and connection weights from memory, adding them together, subtracting the value the neuron needs to leak from the result, and then rewriting the calculated neuron membrane voltage back into memory. The calculation method of this invention first determines whether the connection weight value is less than or equal to a fixed weight threshold. If a connection weight value is less than or equal to the fixed threshold, the corresponding neuron membrane voltage will not be retrieved from memory, and the corresponding neuron calculation unit will not perform the calculation. This method reduces the number of neuron calculations, thereby reducing hardware power consumption.

Claims

1. A hardware implementation method for reducing the number of computations by neurons in a spiking neural network, characterized in that, The implementation method includes the following steps: S1: Set the weight threshold k th Set the neuron threshold v th Set the leakage value v leak The timer is set, and the connection weight value and membrane voltage value are stored in the memory of the hardware circuit. The timer starts working when the digital circuit starts working. S2: Determine if the timer has increased by a fixed value. If yes, jump to S13; otherwise, jump to S3. S3: Input pulse data of a presynaptic neuron into the digital circuit of the spiking neural network; S4: Based on the connection relationship of the spiking neural network, calculate the connection weight values ​​of the presynaptic neuron and N postsynaptic neurons and store them in the memory address. At the same time, calculate the membrane voltage of the N postsynaptic neurons and store it in the memory address. S5: Extract N connection weight values ​​based on the addresses calculated in step 4; S6: Combine the N connection weight values ​​with the set weight threshold k. th The comparison yields an N-bit shielded signal data. If any connection weight value is less than or equal to the weight threshold, the value at the corresponding position in the shielded signal data is 1; otherwise, the value at the corresponding position is 0. The number of 1s in the shielded signal data is represented by M. S7: If all connection weight values ​​in step 6 are less than or equal to the weight threshold, jump to S4; S8: Calculate the membrane voltage of the last N synaptic neurons and store it in the memory address. According to the shielding signal data generated in S6, if a certain bit is 1, the corresponding membrane voltage value will not be read from the memory. Otherwise, the membrane voltage at the corresponding position needs to be read. Therefore, the number of membrane voltages read is NM. S9: Add the connection weight values ​​taken from S5 and the membrane voltage values ​​taken from S8 according to the corresponding relationship to obtain NM calculation results; S10: Compare the NM calculation results from S9 with the neuron threshold. If the membrane voltage is greater than or equal to the neuron threshold, reset the membrane voltage to the reset value v. reset Otherwise, the membrane voltage remains unchanged; S11: Based on the address calculated in S4, write the new calculation result in S10 into the memory at that address; S12: Determine whether all D neurons have completed the membrane voltage update. If yes, jump to S2; otherwise, jump to S4. S13: Perform a leakage operation on the neuron membrane voltage, retrieve all membrane voltages from memory, and subtract a fixed leakage value v from the membrane voltage value. leak The leaked membrane voltage is then rewritten into the memory.

2. The hardware implementation method for reducing the number of computations by neurons in a spiking neural network according to claim 1, characterized in that, The connections between neurons are as follows: each presynaptic neuron is connected to D postsynaptic neurons.

3. The hardware implementation method for reducing the number of computations by neurons in a spiking neural network according to claim 2, characterized in that, In the connections between neurons, the number of postsynaptic neurons D ≥ 1.

4. The hardware implementation method for reducing the number of computations by neurons in a spiking neural network according to claim 1, characterized in that, The neuron model used is the Integral Leakage Ignition (LIF) neuron model. The adjustment of neuronal membrane voltage and the firing of impulses are functionally related to whether the presynaptic neuron generates impulses and the magnitude of connection weights. A typical Integral Leakage neuron model function is shown below: V i (t)=v reset and S i (t)=1,if V i (t)≥V th Where: V i (t) represents the membrane voltage of neuron i at time t, S j (t) indicates whether neuron j generates a pulse at time t, S j The value of (t) has two possibilities: 1 or 0. If it is 1, it means that neuron j generated one pulse at time t; if it is 0, it means that neuron j did not generate a pulse at time t. ij v represents the connection weight between neuron i and neuron j. leak V represents the leakage value that a neuron needs to leak after fixed intervals. th S represents the threshold of a neuron. i (t) indicates whether neuron i fires a pulse at time t, v reset It is the reset value of the membrane voltage after the neuron fires a pulse.

5. The hardware implementation method for reducing the number of computations by neurons in a spiking neural network according to claim 1, characterized in that, In step S1, the connection weight value and the membrane voltage value are both stored in the memory of the hardware circuit. The memory is a register group, RAM, or ROM.

6. The hardware implementation method for reducing the number of computations by neurons in a spiking neural network according to claim 1, characterized in that, Before reading the neuronal membrane voltage from memory, it is first determined whether the connection weight is less than or equal to the weight threshold k. th If the weight of a connection is less than or equal to the weight threshold k th If so, the corresponding neuron membrane voltage does not need to be calculated for that input pulse.

7. The hardware implementation method for reducing the number of computations by neurons in a spiking neural network according to claim 1, characterized in that, The leakage operation of neurons is achieved by periodically subtracting a fixed value from the membrane voltage in the memory.

8. The hardware implementation method for reducing the number of computations by neurons in a spiking neural network according to claim 1, characterized in that, In step S3, the pulse data of the presynaptic neuron input to the spiking neural network digital circuit is the position information of the presynaptic neuron.

9. The hardware implementation method for reducing the number of computations by neurons in a spiking neural network according to claim 1, characterized in that, The spiking neural network connections in step S4 are either fully connected or convolutional.

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