Display device

Abstract

The present invention relates to a display device. The display device includes: a display panel including a plurality of sub-pixels configured to emit light of different colors; a data driver configured to output data voltages to the plurality of sub-pixels via a plurality of data lines; and a timing controller configured to output a plurality of power control signals for controlling a driving current for driving the data driver, the data driver including a plurality of source driver integrated circuits, each of the plurality of source driver integrated circuits including: a plurality of power control circuits configured to generate a driving current according to each of the plurality of power control signals; and a plurality of amplifiers configured to be applied with the driving current to output the data voltages to each of the plurality of data lines, and among the plurality of amplifiers, the plurality of amplifiers connected to any one of the plurality of data lines are connected to the same one of the plurality of power control circuits to be applied with the same power control signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2021 - 0086039, filed with the Korean Intellectual Property Office on June 30, 2021, the disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device, and more particularly, to a display device capable of controlling a driving current. Background art

[0004] As display devices for monitors of computers, televisions, or cellular phones, there are organic light - emitting display devices (OLEDs) as self - emitting devices and liquid - crystal display devices (LCDs) that require a separate light source.

[0005] Among various display devices, an organic light - emitting display device includes a display panel having a plurality of sub - pixels and a driver for driving the display panel. The driver includes a gate driver configured to provide a gate voltage to the display panel and a data driver configured to provide a data voltage. When a gate voltage and a data voltage are provided to the sub - pixels of the organic light - emitting display device, the sub - pixels emit light with a brightness corresponding to a driving current to display an image.

[0006] The data driver includes a plurality of source - driver integrated circuits (SDICs), and each of the plurality of source - driver integrated circuits (SDICs) provides a data voltage to an active area via a plurality of data lines.

[0007] In addition, the plurality of source - driver integrated circuits (SDICs) can control a driving current according to a power control signal PWRC. However, all the source - driver integrated circuits SDICs connected to one data driver are applied with the same power control signal PWRC.

[0008] The power control signal PWRC is determined by the load of the display panel (panel load) and the worst - power - consumption mode, such that the power control signal PWRC may be over - set.

[0009] Therefore, the driving current may be output excessively to each of the plurality of source - driver integrated circuits SDICs, such that there is a problem in that the power consumption of the organic light - emitting display device increases unnecessarily. Summary of the invention

[0010] An object to be achieved by the present disclosure is to provide a display device that optimizes the power control signal PWRC for each source - driver integrated circuit SDIC to optimize power consumption.

[0011] Another object to be achieved by the present disclosure is to provide a display device that controls a power control signal PWRC to optimize a driving current according to color.

[0012] Still another object to be achieved by the present disclosure is to provide a display device that controls a power control signal PWRC to optimize a driving current for each channel.

[0013] The objects of the present disclosure are not limited to the above-mentioned objects, and those skilled in the art can clearly understand other objects not mentioned above according to the following description.

[0014] To achieve the above object, according to an aspect of the present disclosure, a display device includes: a display panel including a plurality of sub-pixels configured to emit light having different colors; a data driver configured to output data voltages to the plurality of sub-pixels via a plurality of data lines; and a timing controller configured to output a plurality of power control signals for controlling a driving current for driving the data driver, the data driver including a plurality of source driver integrated circuits connected to the plurality of data lines to output data voltages to the plurality of data lines, each of the plurality of source driver integrated circuits including: a plurality of power control circuits configured to generate a driving current according to each of the plurality of power control signals; and a plurality of amplifiers configured to be applied with the driving current to output a data voltage to each of the plurality of data lines, and among the plurality of amplifiers, the plurality of amplifiers connected to any one of the plurality of first data lines, the plurality of second data lines, the plurality of third data lines, and the plurality of fourth data lines are connected to the same power control circuit among the plurality of power control circuits to be applied with the same power control signal.

[0015] According to another aspect of the present disclosure, a display device includes: a display panel including a plurality of pixels; a data driver configured to output data voltages to the plurality of pixels via a plurality of data lines; and a timing controller configured to output a plurality of power control signals for controlling a driving current for driving the data driver, the data driver including a plurality of source driver integrated circuits connected to the plurality of data lines to output data voltages to the plurality of data lines, each of the plurality of source driver integrated circuits including: a power control signal distributor configured to output each of the plurality of power control signals to each of the plurality of selectors; a plurality of selectors configured to select one of the plurality of driving currents according to each of the plurality of power control signals; and a plurality of amplifiers configured to be applied with the driving current from each of the plurality of selectors to output a data voltage to each of the plurality of data lines.

[0016] According to another aspect of the present disclosure, a display device includes: a display panel including a plurality of pixels; a data driver configured to output data voltages to the plurality of pixels via a plurality of data lines; and a timing controller configured to output a plurality of power control signals for controlling a driving current driving the data driver, wherein the data driver includes a plurality of source driver integrated circuits connected to the plurality of data lines to output data voltages to the plurality of data lines, and each of the plurality of source driver integrated circuits includes: a power control signal distributor configured to output each of the plurality of power control signals to each of a plurality of selectors; the plurality of selectors configured to select one of a plurality of driving currents according to each of the plurality of power control signals; and a plurality of amplifiers configured to be applied with a driving current from each of the plurality of selectors to output data voltages to each of the plurality of data lines.

[0017] According to another aspect of the present disclosure, a display device includes: a display panel including a plurality of sub-pixels configured to emit light of different colors; a data driver configured to output data voltages to the plurality of sub-pixels via a plurality of data lines; and a timing controller configured to output a plurality of power control signals for controlling a driving current driving the data driver, the data driver including: a plurality of power control circuits configured to generate driving currents according to each of the plurality of power control signals; and a plurality of amplifiers configured to be applied with driving currents to output data voltages to each of the plurality of data lines, and among the plurality of amplifiers, a plurality of amplifiers connected to a plurality of data lines connected to a plurality of sub-pixels emitting light of the same color are connected to the same power control circuit to be applied with the same power control signal.

[0018] Other matters of the exemplary embodiments are included in the detailed description and the drawings.

[0019] According to the present disclosure, power control signals are provided for each color to drive the source driver integrated circuits, so that power consumption can be effectively reduced in an image with high data transitions.

[0020] According to the present disclosure, the driving current is set individually according to the transition level of the data voltage applied to the plurality of data lines to more finely optimize the driving current of the source driver integrated circuits.

[0021] According to the present disclosure, power consumption is reduced to ensure driving stability by an increased expected lifetime and minimized heat generation.

[0022] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0024] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0025] Figure 2 is a view for explaining a timing controller of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 3 is a view for explaining the operation of a data comparator of a display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 4 is a view showing a look-up table (LUT) of a power control signal generator of a display device according to an exemplary embodiment of the present disclosure;

[0028] Figure 5 is a view for explaining a data packet transmitted through an EPI interface of a timing controller of a display device according to an exemplary embodiment of the present disclosure;

[0029] Figure 6 is a block diagram schematically illustrating a source driver integrated circuit of a display device according to an exemplary embodiment of the present disclosure;

[0030] Figure 7 is a block diagram for explaining the connection relationship between a power control circuit and an amplifier of a display device according to an exemplary embodiment of the present disclosure;

[0031] Figure 8 is a circuit diagram for explaining a power control circuit and a plurality of amplifiers of a display device according to an exemplary embodiment of the present disclosure;

[0032] Figure 9 is a graph showing the power consumption of a display device according to an exemplary embodiment of the present disclosure;

[0033] Figure 10 is a view for explaining a timing controller of a display device according to an exemplary embodiment of the present disclosure;

[0034] Figure 11 is a view for explaining the operation of a data comparator of a display device according to another exemplary embodiment of the present disclosure;

[0035] Figure 12 is a view for explaining data packets transmitted through an EPI interface of a timing controller of a display device according to another exemplary embodiment of the present disclosure;

[0036] Figure 13 is a block diagram schematically illustrating a source driver integrated circuit of a display device according to another exemplary embodiment of the present disclosure;

[0037] Figure 14 is a block diagram for explaining a power control signal distributor of a display device according to another exemplary embodiment of the present disclosure; and

[0038] Figure 15 is a block diagram for explaining a connection relationship between a selector and an amplifier according to another exemplary embodiment of the present disclosure. Detailed Description of the Embodiment

[0039] Advantages and features of the present disclosure and methods for achieving these advantages and features will become clear by referring to the exemplary embodiments described in detail below and the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure content and scope of the present disclosure. Therefore, the present disclosure will be defined only by the scope of the appended claims.

[0040] Shapes, sizes, ratios, angles, numbers, etc. shown in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally indicate the same elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having", and "consisting of" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise explicitly stated.

[0041] Even if not explicitly stated, components are interpreted to include an ordinary error range.

[0042] When using terms such as "on", "above", "below", and "next to" to describe the positional relationship between two components, one or more components may be located between the two components, unless these terms are used together with the terms "immediately" or "directly".

[0043] When an element or layer is disposed "on" another element or layer, the other layer or the other element can be directly disposed on the other element or disposed therebetween.

[0044] Although terms such as "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Thus, the first component mentioned below can be the second component in the technical concept of the present disclosure.

[0045] Throughout the specification, the same reference numerals generally denote the same elements.

[0046] For ease of description, the dimensions and thicknesses of each component shown in the drawings are illustrated, and the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0047] The features of the various embodiments of the present disclosure can be partially or completely adhered to or combined with each other and can be interlocked and operated in technically different ways, and the embodiments can be executed independently of each other or in association with each other.

[0048] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Referring to Figure 1 , the display device 100 includes a display panel 110, a gate driver 120, a data driver 130, and a timing controller 140.

[0049] The display panel 110 is a panel for displaying an image. The display panel 110 may include various circuits, wirings, and light emitting diodes disposed on a substrate. The display panel 110 is divided by a plurality of data lines DL and a plurality of gate lines GL that cross each other, and may include a plurality of pixels PX connected to the plurality of data lines DL and the plurality of gate lines GL.

[0050] The display panel 110 may include a plurality of active regions AA defined by a plurality of pixels PX and a non-active region NA in which various signal lines or pads are formed.

[0051] Each of the plurality of pixels PX may include a plurality of sub-pixels. The plurality of sub-pixels may be sub-pixels that emit different color lights. For example, the plurality of sub-pixels SP may be a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W, but is not limited thereto. The plurality of sub-pixels may configure one pixel PX. For example, the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the white sub-pixel W may configure one pixel PX. In other words, the display panel 110 may include a plurality of red sub-pixels R, a plurality of green sub-pixels G, a plurality of blue sub-pixels B, and a plurality of white sub-pixels W.

[0052] In addition, a plurality of red sub-pixels R arranged in a column are connected to a red data line to be applied with a red data voltage. In addition, a plurality of green sub-pixels G arranged in a column are connected to a green data line to be applied with a green data voltage. A plurality of blue sub-pixels B arranged in a column are connected to a blue data line to be applied with a blue data voltage. A plurality of white sub-pixels W arranged in a column are connected to a white data line to be applied with a white data voltage.

[0053] For ease of description, the red sub-pixel R may be referred to as the first sub-pixel, the green sub-pixel G may be referred to as the second sub-pixel, the blue sub-pixel B may be referred to as the third sub-pixel, and the white sub-pixel W may be referred to as the fourth sub-pixel. In addition, the red data line may be referred to as the first data line, the green data line may be referred to as the second data line, the blue data line may be referred to as the third data line, and the white data line may be referred to as the fourth data line.

[0054] However, although the display device according to the exemplary embodiment of the present disclosure is configured by the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the white sub-pixel W, the present disclosure is not limited thereto. Thus, the display device may include only the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B excluding the white sub-pixel W. Therefore, in the display panel of the display device according to the exemplary embodiment of the present disclosure, only the red data line, the green data line, and the blue data line excluding the white data line may be provided.

[0055] Meanwhile, the display panel 110 may be implemented by a display panel 110 used in various display devices such as a liquid crystal display device, an organic light emitting display device, or an electrophoretic display device.

[0056] The timing controller 140 may receive timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a data clock signal DCLK via a receiving circuit connected to a host system such as an LVDS or TMDS interface. The timing controller 140 generates control signals DCS or GCS for controlling the data driver 130 and the gate driver 120 based on the input timing signals.

[0057] For example, in order to control the gate driver 120, the timing controller 140 outputs various gate control signals GCS including a gate start pulse, a gate shift clock, and a gate output enable signal.

[0058] Here, the gate start pulse controls the operation start timing of the gate driver 120. The gate shift clock is a clock signal commonly input to one or more gate circuits and controls the shift timing of the gate voltage. The gate output enable signal specifies the output timing information of the gate driver 120.

[0059] In addition, to control the data driver 130, the timing controller 140 outputs various data control signals DCS including a source start pulse, a source sampling clock, and a source output enable signal.

[0060] Here, the source start pulse controls the data sampling start timing of one or more source driver integrated circuits SDICs configuring the data driver 130. The source sampling clock is a clock signal that controls the sampling timing of data in each data circuit. The source output enable signal controls the output timing of the data driver 130.

[0061] In addition, the timing controller 140 sends digital video data Data to the data driver 130. The digital video data Data is converted into an analog data voltage in the data driver 130 to be output to each pixel PX provided in the active area AA.

[0062] In addition, the timing controller 140 outputs a power control signal PWRC to the data driver 130. The drive current of one or more source driver integrated circuits SDICs configuring the data driver 130 can be controlled by the power control signal PWRC.

[0063] Meanwhile, the timing controller 140 is an embedded clock point-to-point interface (EPI) that sends / receives data in the form of a differential swing-level voltage and sends the data control signal DCS, the video data Data, and the power control signal PWRC to the data driver 130.

[0064] The gate driver 120 provides a gate voltage to a plurality of pixels PX. The gate driver 120 may be configured by a plurality of stages that shift and output the gate voltage in response to a gate control signal GSC. The plurality of stages included in the gate driver 120 may sequentially output the gate voltage to the plurality of pixels PX via gate lines GL. The gate driver 120 may be a gate driver integrated circuit GDIC formed in the non-active area NA of the display panel 110 by an on-panel gate (GIP) method, but is not limited thereto.

[0065] The data driver 130 provides a data voltage to a plurality of pixels PX. The data driver 130 may include a plurality of source driver integrated circuits (SDICs). For example, as Figure 1 shown, the data driver 130 may include a first source driver integrated circuit SDIC#1, a second source driver integrated circuit SDIC#2,..., and an m-th source driver integrated circuit SDIC#m. Here, m is a natural number of 1 or greater.

[0066] Multiple source driver integrated circuits SDIC#1, SDIC#2, ……, and SDIC#m can be provided with digital video data Data, data control signal DCS, and power control signal PWRC from a timing controller 140. Each of the multiple source driver integrated circuits SDIC#1, SDIC#2, ……, and SDIC#m generates a data voltage from the digital video data Data using an analog gamma voltage in response to the data control signal DCS. In addition, each of the multiple source driver integrated circuits SDIC#1, SDIC#2, ……, and SDIC#m can output the data voltage to multiple pixels PX via data lines DL by a driving current determined by the power control signal PWRC.

[0067] The multiple source driver integrated circuits SDIC#1, SDIC#2, ……, and SDIC#m can be connected to the data lines DL of the display panel 110 through a chip on glass (COG) process or a tape automated bonding (TAB) process. In addition, the multiple source driver integrated circuits SDIC#1, SDIC#2, ……, and SDIC#m are formed on the display panel 110, or can be formed on a separate PCB substrate to be connected to the display panel 110.

[0068] Figure 2 is a view of a timing controller of a display device for illustrating an exemplary embodiment according to the present disclosure.

[0069] Referring to Figure 2 , the timing controller 140 includes a data enable signal generator 141, a data delay unit 142, multiple data comparators 143 (RED DATA_Comp, GREEN DATA_Comp, BLUE DATA_Comp, and WHITE DATA_Comp), and multiple power control signal generators 144 (RED PWRC_Gen, GREEN PWRC_Gen, BLUE PWRC_Gen, and WHITE PWRC_Gen).

[0070] The data enable signal generator 141 synchronizes with a data enable signal DE and a data clock signal DCLK to output a sub - data enable signal SDE to each of the multiple data comparators 143.

[0071] Specifically, the sub - data enable signal SDE is a signal that determines the timing at which each of the first source driver integrated circuit SDIC#1 to the mth source driver integrated circuit SDIC#m outputs the data voltage to the active area AA.

[0072] For example, since the data voltage is applied to one pixel row during one horizontal period, the sub - data enable signal SDE can be output at a high level, which is a conduction level, during one horizontal period.

[0073] The data delay unit 142 is applied with video data Data to delay the video data by one horizontal period, and then outputs the delayed video data.

[0074] The data delay unit 142 stores the video data Data in an internal memory and delays the video data by one horizontal period, and then outputs the delayed video data D_Data to each of the plurality of data comparators 143.

[0075] For example, the data delay unit 142 stores the video data Data corresponding to the (n - 1)-th row in the (n - 1)-th horizontal period, and then outputs the delayed video data D_Data corresponding to the (n - 1)-th row in the n-th horizontal period.

[0076] Specifically, the video data Data includes red data Red Data, green data Green Data, blue data Blue Data, and white data White Data, such that the delayed video data D_Data can be data obtained by delaying the data. For example, the delayed video data D_Data includes delayed red data D_Red Data, delayed green data D_Green Data, delayed blue data D_Blue Data, and delayed white data D_WhiteData.

[0077] Figure 3 is a view for explaining the operation of a data comparator of a display device according to an exemplary embodiment of the present disclosure.

[0078] In addition, each of the plurality of data comparators 143 compares the video data Data and the delayed video data D_Data when the plurality of sub-data enable signals SDE are at a conductive level to generate a plurality of comparison data CD. In addition, each of the plurality of data comparators 143 outputs the comparison data CD to the power control signal generator 144. In other words, the above-mentioned comparison data CD may refer to the maximum data transition value of adjacent pixel rows (the (N - 1)-th row and the N-th row) in each of the plurality of active regions AA.

[0079] More specifically, referring to Figure 3 , the first data comparator 143-1 compares the red data Red Data of the current pixel row (the N-th row) and the delayed red data D_Red Data of the previous pixel row (the (N - 1)-th row) when the sub-data enable signal SDE is at a conductive level, and outputs a plurality of red comparison data CD_R(1), CD_R(2), and CD_R(3) to the first power control signal generator 144-1.

[0080] When the sub-data enable signal SDE is at a conductive level, the second data comparator 143-2 compares the green data of the current pixel row (the Nth row) with the delayed green data D_Green Data of the previous pixel row (the (N-1)th row), so as to output a plurality of green comparison data CD_G(1), CD_G(2) and CD_G(3) to the second power control signal generator 144-2.

[0081] When the sub-data enable signal SDE is at a conductive level, the third data comparator 143-3 compares the blue data of the current pixel row (the Nth row) with the delayed blue data D_Blue Data of the previous pixel row (the (N-1)th row), so as to output a plurality of blue comparison data CD_B(1), CD_B(2) and CD_B(3) to the third power control signal generator 144-3.

[0082] When the sub-data enable signal SDE is at a conductive level, the fourth data comparator 143-4 compares the white data of the current pixel row (the Nth row) with the delayed white data D_White Data of the previous pixel row (the (N-1)th row), so as to output a plurality of white comparison data CD_W(1), CD_W(2) and CD_W(3) to the fourth power control signal generator 144-4.

[0083] For ease of description, the red comparison data CD_R can be referred to as the first comparison data, the green comparison data CD_G can be referred to as the second comparison data, the blue comparison data CD_B can be referred to as the third comparison data, and the white comparison data CD_W can be referred to as the fourth comparison data.

[0084] Figure 4 is a view showing a look-up table (LUT) of a power control signal generator of a display device according to an exemplary embodiment of the present disclosure.

[0085] The power control signal generator 144 generates a power control signal PWRC using a plurality of comparison data CD.

[0086] Specifically, each power control signal generator 144 applies the maximum value among the applied plurality of comparison data CD to the look-up table LUT to set the power control signal PWRC.

[0087] Refer to Figures 2 to 4, the first power control signal generator 144-1 compares the maximum value among multiple red comparison data CD_R(1), CD_R(2), and CD_R(3) with multiple thresholds stored in the LUT to generate a red power control signal PWRC_R. In addition, the second power control signal generator 144-2 compares the maximum value among multiple green comparison data CD_G(1), CD_G(2), and CD_G(3) with multiple thresholds stored in the LUT to generate a green power control signal PWRC_G. In addition, the third power control signal generator 144-3 compares the maximum value among multiple blue comparison data CD_B(1), CD_B(2), and CD_B(3) with multiple thresholds stored in the LUT to generate a blue power control signal PWRC_B. The fourth power control signal generator 144-4 compares the maximum value among multiple white comparison data CD_W(1), CD_W(2), and CD_W(3) with multiple thresholds stored in the LUT to generate a white power control signal PWRC_W.

[0088] For ease of description, the red power control signal PWRC_R is referred to as the first power control signal, the green power control signal PWRC_G is referred to as the second power control signal, the blue power control signal PWRC_B is referred to as the third power control signal, and the white power control signal PWRC_W is referred to as the fourth power control signal.

[0089] For example, when the comparison data CD is equal to or lower than the first threshold Th1, the power control signal PWRC is set to P0 (LLL), and when the comparison data CD exceeds the first threshold Th1 and is equal to or lower than the second threshold Th2, the power control signal PWRC is set to P1 (LLH). When the comparison data CD exceeds the second threshold Th2 and is equal to or lower than the third threshold Th3, the power control signal PWRC is set to P2 (LHL), and when the comparison data CD exceeds the third threshold Th3 and is equal to or lower than the fourth threshold Th4, the power control signal PWRC is set to P3 (LHH). When the comparison data CD exceeds the fourth threshold Th4 and is equal to or lower than the fifth threshold Th5, the power control signal PWRC is set to P4 (HLL), and when the comparison data CD exceeds the fifth threshold Th5 and is equal to or lower than the sixth threshold Th6, the power control signal PWRC is set to P5 (HLH). When the comparison data CD exceeds the sixth threshold Th6 and is equal to or lower than the seventh threshold Th7, the power control signal PWRC is set to P6 (HHL), and when the comparison data CD exceeds the seventh threshold Th7, the power control signal PWRC is set to P7 (HHH).

[0090] The first threshold Th1 to the seventh threshold Th7 are stored in the memory of the power control signal generator 144 and can be changed according to settings.

[0091] Figure 5 is a view for explaining data packets transmitted by the EPI interface of the timing controller of a display device according to an exemplary embodiment of the present disclosure.

[0092] Meanwhile, the timing controller 140 is an embedded clock point-to-point interface (EPI) that transmits / receives data in the form of differential swing-level voltages and sends the data control signal DCS, video data Data, and power control signal PWRC to the data driver 130.

[0093] Specifically, as Figure 5 shown, data packets for EPI interface transmission can be configured by a first phase Phase-I, a second phase Phase-II, and a third phase Phase-III.

[0094] The first phase Phase-I may include a clock signal such as a data clock signal DCLK, the second phase Phase-II may include a data control signal DCS and a power control signal PWRC, and the third phase Phase-III may include video data Data.

[0095] In a display device according to an exemplary embodiment of the present disclosure, instead of converting all of the plurality of comparison data CDs into a power control signal PWRC, the maximum value of the plurality of comparison data CDs having the same color is converted into a power control signal PWRC. Therefore, the data volume of the power control signal PWRC is not large, such that the power control signal PWRC can be included in the second phase Phase-II. For example, the power control signal PWRC can be sent to the previous phase of the video data Data.

[0096] Figure 6 is a block diagram for schematically explaining a source driver integrated circuit of a display device according to an exemplary embodiment of the present disclosure.

[0097] Referring to Figure 6 , each of the plurality of source driver integrated circuits SDICs includes a shift register 131, a latch 132, a digital-to-analog converter (DAC) 133, an amplifier 134, and a power control circuit 135.

[0098] The shift register 131 receives a data control signal DCS including a source start pulse and a source sampling clock from the timing controller 140 to determine sequential data sampling timing.

[0099] The latch 132 sequentially latches the red, green, blue, and white digital video data Data transmitted from the timing controller 140 in response to the sampling signal transmitted from the shift register 131, and outputs the red, green, blue, and white digital video data simultaneously.

[0100] The digital-to-analog converter 133 converts the red, green, blue, and white digital video data Data from the latch 132 into an analog data voltage Vdata using an analog gamma voltage.

[0101] The amplifier 134 can output the analog data voltage Vdata transmitted from the digital-to-analog converter 133 to the data line.

[0102] The power control circuit (PWRC circuit) 135 is switched according to the power control signal PWRC transmitted from the timing controller 140 to control the amount of current applied to the amplifier 134, thereby controlling the power consumption of the data driver.

[0103] Generally, the power control circuit 135 may be embedded in each of the plurality of source driver integrated circuits SDICs, but the present disclosure is not limited thereto. Accordingly, the power control circuit 135 may be provided in various positions, such as on a printed circuit board or a chip-on-film (COF) outside the plurality of source driver integrated circuits SDICs.

[0104] Figure 7 is a block diagram for explaining the connection relationship between the power control circuit and the amplifier of the display device according to an exemplary embodiment of the present disclosure.

[0105] The amplifier 134 may include a first amplifier 134-1 connected to the first data line DL_R, a second amplifier 134-2 connected to the second data line DL_G, a third amplifier 134-3 connected to the third data line DL_B, and a fourth amplifier 134-4 connected to the fourth data line DL_W.

[0106] For example, referring to Figure 7, Three first amplifiers 134-1 are connected to three first data lines DL_R, such that each of the plurality of first amplifiers 134-1 outputs a red data voltage to each first data line DL_R. In addition, three second amplifiers 134-2 are connected to three second data lines DL_G, such that each of the plurality of second amplifiers 134-2 outputs a green data voltage to each second data line DL_G. In addition, three third amplifiers 134-3 are connected to three third data lines DL_B, such that each of the plurality of third amplifiers 134-3 outputs a blue data voltage to each third data line DL_B. In addition, three fourth amplifiers 134-4 are connected to three fourth data lines DL_W, such that each of the plurality of fourth amplifiers 134-4 outputs a white data voltage to each fourth data line DL_W.

[0107] In addition, the power control circuit 135 includes: a first power control circuit 135-1 (red PWRC circuit) configured to output a drive current according to a first power control signal PWRC_R; a second power control circuit 135-2 (green PWRC circuit) configured to output a drive current according to a second power control signal PWRC_G; a third power control circuit 135-3 (blue PWRC circuit) configured to output a drive current according to a third power control signal PWRC_B; and a fourth power control circuit 135-4 (white PWRC circuit) configured to output a drive current according to a fourth power control signal PWRC_W.

[0108] In addition, all of the plurality of first amplifiers 134-1 are connected to one first power control circuit 135-1. Thus, all of the plurality of first amplifiers 134-1 can be applied with the same first power control signal PWRC_R from one first power control circuit 135-1. In addition, all of the plurality of second amplifiers 134-2 are connected to one second power control circuit 135-2. Thus, all of the plurality of second amplifiers 134-2 can be applied with the same second power control signal PWRC_G from one second power control circuit 135-2. In addition, all of the plurality of third amplifiers 134-3 are connected to one third power control circuit 135-3. Thus, all of the plurality of third amplifiers 134-3 can be applied with the same third power control signal PWRC_B from one third power control circuit 135-3. All of the plurality of fourth amplifiers 134-4 are connected to one fourth power control circuit 135-4. Thus, all of the plurality of fourth amplifiers 134-4 can be applied with the same fourth power control signal PWRC_W from one fourth power control circuit 135-4.

[0109] For example, in a driving integrated circuit of a display device according to an exemplary embodiment of the present disclosure, all of the plurality of amplifiers configured to output data voltages having the same color may be connected to one power control circuit to be applied with the same power control signal.

[0110] Figure 8 is a circuit diagram for explaining a power control circuit and a plurality of amplifiers of a display device according to an exemplary embodiment of the present disclosure.

[0111] Specifically, Figure 8 shows a plurality of amplifiers 134 connected to one of the plurality of power control circuits 135.

[0112] Referring to Figure 8 , each of the plurality of amplifiers 134 may be configured by at least one operational amplifier and may be set to correspond to each of the plurality of data lines DL.

[0113] The plurality of data lines DL may be any one of the plurality of first data lines DL_R, the plurality of second data lines DL_G, the plurality of third data lines DL_B, and the plurality of fourth data lines DL_W as described in Figure 7 .

[0114] Each of the plurality of amplifiers 134 amplifies and outputs an analog data voltage Vdata received through the non-inverting input terminal (+). The inverting input terminal (-) of each of the plurality of amplifiers 134 is connected to the data line DL connected to the output terminal, the VCC terminal of each of the plurality of amplifiers 134 is connected to the driver supply voltage VDD, and the terminal VEE is connected to the power control circuit 135.

[0115] The power control circuit 135 determines the intensity of the drive current I SUM applied to each of the plurality of amplifiers 134.

[0116] The PWRC control circuit 135 includes: a plurality of current sources I 1 , ……, I 7 , I 8 ; a plurality of switches SW1, ……, SW7, SW8; and a first mirror transistor MT1 and a second mirror transistor MT2 configuring a current mirror circuit.

[0117] Each of the plurality of switches SW1, ……, SW7, SW8 and each of the plurality of current sources I 1 , ……, I 7 , I 8 are connected in series. In addition, the plurality of switches SW1, ……, SW7, SW8 connected in series and the plurality of current sources I 1, ……, I 7 , I 8 are connected in parallel. In addition, a plurality of switches SW1, ……, SW7, SW8 connected in parallel and a plurality of current sources I 1 , ……, I 7 , I 8 are connected in series to a current mirror circuit. Therefore, the drive current I output to the current mirror circuit is determined according to the on states of the plurality of switches SW1, ……, SW7, SW8 SUM .

[0118] The first mirror transistor MTl and the second mirror transistor MT2 configure a current mirror circuit.

[0119] The gate electrode and the source electrode of the first mirror transistor MTl are connected to the plurality of switches SW1, ……, SW7, SW8 to be applied with the drive current I SUM .

[0120] In addition, the gate electrode of the second mirror transistor MT2 is connected to the gate electrode of the first mirror transistor MTl, and the drain electrode of the second mirror transistor MT2 is connected to the terminal V of the amplifier 134 EE .

[0121] Therefore, the source-drain current of the second mirror transistor MT2 is determined as the drive current I SUM . In addition, the drive current I output by the second mirror transistor MT2 SUM is output to the terminal V of the amplifier 134 EE .

[0122] Therefore, the power control circuit 135 controls the magnification of each of the plurality of amplifiers 134 to control the power consumption of each of the plurality of amplifiers 134.

[0123] Figure 9 is a diagram showing the power consumption of a display device according to an exemplary embodiment of the present disclosure.

[0124] In particular, Figure 9 shows the power consumption of each of the images Image I, Image II, and Image III in the comparative example and the example.

[0125] According to the comparative example, instead of providing a power control signal for each sub-pixel, one power control signal is applied to one source driver integrated circuit to be driven. In addition, according to the example, as described in the exemplary embodiment of the present disclosure, a power control signal is provided for a plurality of data lines connected to sub-pixels having the same color.

[0126] In addition, the first image Image I refers to an image that mainly implements one color, the second image Image II refers to an image that simply implements a few dynamic images, and the third image Image III refers to an image that simply implements more dynamic images.

[0127] For example, the data transition of the second image Image II is greater than that of the first image Image I, and the data transition of the third image Image III is greater than that of the second image Image II.

[0128] Therefore, as Figure 9 shown, the power consumption of the second image Image II is higher than that of the first image Image I, and the power consumption of the third image Image III is higher than that of the second image Image II.

[0129] However, by providing a power control signal for each color, the power consumption of the embodiment can be reduced more compared to that of the comparative example.

[0130] Therefore, as Figure 9 shown, the power consumption reduction of the second image Image II is higher than that of the first image Image I, and the power consumption reduction of the third image Image III is higher than that of the second image Image II.

[0131] For example, the display device according to the present disclosure provides a power control signal for each color to drive the source driver integrated circuit, so that the power consumption can be effectively reduced in an image with a high data transition.

[0132] Therefore, the display device according to the exemplary embodiment of the present disclosure reduces the power consumption, so that the lifespan is also increased according to the reduced heat generation.

[0133] Hereinafter, a display device according to another exemplary embodiment of the present disclosure will be described in detail. The only difference between the display device according to another exemplary embodiment of the present disclosure and the display device according to the exemplary embodiment of the present disclosure lies in the configuration and operation of the timing controller and the data driver, so this difference will be mainly described.

[0134] Figure 10 is a view for illustrating the timing controller of the display device according to the exemplary embodiment of the present disclosure.

[0135] The timing controller 240 includes a data enable signal generator 241 (GE_Gen), a data delay unit 242 (DATA_Delay), a plurality of data comparators 243 (DATA_Comp_1, DATA_Comp_2, and DATA_Comp_3), and a plurality of power control signal generators 244 (PWRC_Gen_1, PWRC_Gen_2, and PWRC_Gen_3).

[0136] The data enable signal generator 241 synchronizes with the data enable signal DE and the data clock signal DCLK to output a sub-data enable signal SDE to each of the plurality of data comparators 243.

[0137] Specifically, the sub-data enable signal SDE is a signal that determines the timing at which each of the first source driver integrated circuit SDIC#1 to the m-th source driver integrated circuit SDIC#m outputs a data voltage to the active region AA.

[0138] For example, since a data voltage is applied to one pixel row during one horizontal period, the sub-data enable signal SDE can be output at a high level, which is a conductive level, during one horizontal period.

[0139] The data delay unit 242 is applied with video data Data to delay the video data by one horizontal period, and then outputs the delayed video data.

[0140] The data delay unit 242 stores the video data Data in an internal memory, delays the video data by one horizontal period, and then outputs the delayed video data D_Data to each of the plurality of data comparators 243.

[0141] For example, the data delay unit 242 stores the video data Data corresponding to the (n - 1)-th row in the (n - 1)-th horizontal period, and then outputs the delayed video data D_Data corresponding to the (n - 1)-th row in the n-th horizontal period.

[0142] Figure 11 is a view illustrating the operation of a data comparator of a display device according to an exemplary embodiment of the present disclosure.

[0143] In addition, each of the plurality of data comparators 243 compares the video data Data and the delayed video data D_Data when the plurality of sub-data enable signals SDE are at a conductive level to generate a plurality of comparison data CD. In addition, each of the plurality of data comparators 243 outputs the comparison data CD to the power control signal generator 244. In other words, the above comparison data CD may refer to the maximum data transition value of adjacent pixel rows (the (N - 1)-th row and the N-th row) in each of the plurality of active regions AA.

[0144] More specifically, referring to Figure 11, when the sub-data enable signal SDE is at a conductive level, the first data comparator 243-1 compares the video data Data of the current pixel row (the Nth row) and the delayed video data D_Data of the previous pixel row (the (N-1)th row) based on the first data line, so as to output the first comparison data CD1 to the first power control signal generator 244-1.

[0145] , when the sub-data enable signal SDE is at a conductive level, the second data comparator 243-2 compares the video data Data of the current pixel row (the Nth row) and the delayed video data D_Data of the previous pixel row (the (N-1)th row) based on the second data line, so as to output the second comparison data CD2 to the second power control signal generator 244-2.

[0146] , when the sub-data enable signal SDE is at a conductive level, the third data comparator 243-3 compares the video data Data of the current pixel row (the Nth row) and the delayed video data D_Data of the previous pixel row (the (N-1)th row) based on the third data line, so as to output the third comparison data CD3 to the third power control signal generator 244-3.

[0147] The power control signal generator 244 generates a power control signal PWRC using a plurality of comparison data CDs.

[0148] Specifically, each power control signal generator 244 applies the applied comparison data CD to a look-up table LUT to set the power control signal PWRC.

[0149] Refer to Figure 10 and Figure 4 , the first power control signal generator 244-1 compares the first comparison data CD1 with a plurality of thresholds stored in the LUT to generate a first power control signal PWRC1. In addition, the second power control signal generator 244-2 compares the second comparison data CD2 with a plurality of thresholds stored in the LUT to generate a second power control signal PWRC2. In addition, the third power control signal generator 244-3 compares the third comparison data CD3 with a plurality of thresholds stored in the LUT to generate a third power control signal PWRC3.

[0150] For example, when the comparison data CD is equal to or lower than the first threshold Th1, the power control signal PWRC is set to P0 (LLL), and when the comparison data CD exceeds the first threshold Th1 and is equal to or lower than the second threshold Th2, the power control signal PWRC is set to P1 (LLH). When the comparison data CD exceeds the second threshold Th2 and is equal to or lower than the third threshold Th3, the power control signal PWRC is set to P2 (LHL), and when the comparison data CD exceeds the third threshold Th3 and is equal to or lower than the fourth threshold Th4, the power control signal PWRC is set to P3 (LHH). When the comparison data CD exceeds the fourth threshold Th4 and is equal to or lower than the fifth threshold Th5, the power control signal PWRC is set to P4 (HLL), and when the comparison data CD exceeds the fifth threshold Th5 and is equal to or lower than the sixth threshold Th6, the power control signal PWRC is set to P5 (HLH). When the comparison data CD exceeds the sixth threshold Th6 and is equal to or lower than the seventh threshold Th7, the power control signal PWRC is set to P6 (HHL), and when the comparison data CD exceeds the seventh threshold Th7, the power control signal PWRC is set to P7 (HHH).

[0151] The first threshold Th1 to the seventh threshold Th7 are stored in the memory of the power control signal generator 244 and can be changed according to the settings.

[0152] Figure 12 is a view for explaining a data packet transmitted by the EPI interface of a timing controller of a display device according to another exemplary embodiment of the present disclosure.

[0153] The timing controller 240 is an embedded clock point-to-point (EPI) interface that transmits / receives data in the form of differential swing-level voltages and sends the data control signal DCS, video data Data, and power control signal PWRC to the data driver 230.

[0154] Specifically, as Figure 12 shown, the data packet for EPI interface transmission can be configured by a first phase Phase-I, a second phase Phase-II, a third phase Phase-III, and a fourth phase Phase-IV.

[0155] The first phase Phase-I may include a clock signal such as a data clock signal DCLK, the second phase Phase-II may include a data control signal DCS, the third phase Phase-III may include video data Data, and the fourth phase Phase-IV may include a power control signal PWRC.

[0156] In a display device according to another exemplary embodiment of the present disclosure, all of the plurality of comparison data CDs are converted into a power control signal PWRC. Accordingly, the amount of data of the power control signal PWRC is large such that the power control signal PWRC can be included in the fourth phase Phase-IV. For example, the power control signal PWRC may be sent to a phase that follows the transmission of video data Data.

[0157] Figure 13 is a block diagram for schematically illustrating a source driver integrated circuit of a display device according to another exemplary embodiment of the present disclosure.

[0158] Referring to Figure 13 , each of the plurality of source driver integrated circuits SDICs includes a shift register 231, a latch 232, a digital-to-analog converter (DAC) 233, an amplifier 234, a power control signal distributor (PWRC distributor) 235, a plurality of drive current sources 236, and a plurality of selectors (MUX) 237.

[0159] The shift register 231 receives a data control signal DCS including a source start pulse and a source sampling clock from the timing controller 240 to determine sequential data sampling timing.

[0160] The latch 232 sequentially latches red, green, blue, and white digital video data Data sent from the timing controller 240 in response to a sampling signal sent from the shift register 231 to output the red, green, blue, and white digital video data Data simultaneously.

[0161] The digital-to-analog converter 233 converts the red, green, blue, and white digital video data Data from the latch 232 into an analog data voltage Vdata using an analog gamma voltage.

[0162] The amplifier 234 may output the analog data voltage Vdata sent from the digital-to-analog converter 233 to a data line.

[0163] The power control signal distributor 235 outputs the plurality of power control signals PWRC sent from the timing controller 240 to each of the plurality of selectors 237.

[0164] The plurality of drive current sources 236 may output currents having different intensities. The plurality of drive current sources 236 may be constant current sources, but are not limited thereto, and may be current mirror circuits configured to output a plurality of currents. For example, as will be described in Figure 15 , the plurality of drive current sources 236 may include a total current source HH, a half current source HL, a quarter current source LH, and a zero current source LL.

[0165] Each of the plurality of selectors 237 selects one of the plurality of currents applied from the plurality of drive current sources 236 according to the transmitted power control signal PWRC, and outputs the selected current as a drive current to each of the plurality of amplifiers 234.

[0166] In addition, each of the plurality of amplifiers 234 is applied with a drive current from each of the plurality of selectors 237 to output a data voltage Vdata to each of the plurality of data lines.

[0167] Figure 14 is a block diagram illustrating a power control signal distributor of a display device according to another exemplary embodiment of the present disclosure.

[0168] As Figure 13 and Figure 14 shown, the power control signal distributor 235 may include: a shift register 235-1 configured to sequentially shift a plurality of power control signals PWRC; and a plurality of latches 235-2 configured to align the shifted plurality of power control signals PWRC.

[0169] Referring to Figure 10 and Figure 14 , the shift register 235-1 is applied with a plurality of power control signals PWRC from a plurality of power control signal generators 244, and sequentially shifts the plurality of power control signals to store the plurality of power control signals in the plurality of latches 235-2 respectively.

[0170] Referring to Figure 13 and Figure 14 , each of the plurality of latches 235-2 sequentially latches each of the plurality of power control signals PWRC to output the power control signals to the plurality of selectors 237 simultaneously.

[0171] Therefore, the plurality of power control signals PWRC can be simultaneously distributed to the plurality of selectors 237 by the power control signal distributor 235.

[0172] Figure 15 is a block diagram illustrating the connection relationship between a selector and an amplifier according to another exemplary embodiment of the present disclosure.

[0173] The plurality of amplifiers 234 may include a first amplifier 234-1 connected to a first data line DL1, a second amplifier 234-2 connected to a second data line DL2,..., a (k-1)th amplifier 234-(k-1) connected to a (k-1)th data line DL(k-1), and a kth amplifier 234-k connected to a kth data line DL(k). In this case, k is a natural number of 3 or more.

[0174] In addition, the plurality of selectors 237 may include a first selector 237-1 connected to the first amplifier 234-1, a second selector 237-2 connected to the second amplifier 234-2, ……, a (k-1)th selector 237-(k-1) connected to the (k-1)th amplifier 234-(k-1), and a kth selector 237-(k) connected to the kth amplifier 234-(k).

[0175] Accordingly, the first selector 237-1 selects at least one of the currents output from the plurality of drive current sources HH, HL, LH, and LL according to the first power control signal PWRC1, and outputs the selected current as a drive current. In addition, the first amplifier 234-1 outputs a data voltage to the first data line DL1 using the drive current applied from the first selector 237-1. In addition, the second selector 237-2 selects at least one of the currents output from the plurality of drive current sources HH, HL, LH, and LL according to the second power control signal PWRC2, and outputs the selected current as a drive current. In addition, the second amplifier 234-2 outputs a data voltage to the second data line DL2 using the drive current applied from the second selector 237-2. In addition, the (k-1)th selector 237-(k-1) selects at least one of the currents output from the plurality of drive current sources HH, HL, LH, and LL according to the (k-1)th power control signal PWRC(k-1), and outputs the selected current as a drive current. In addition, the (k-1)th amplifier 234-(k-1) outputs a data voltage to the (k-1)th data line DL(k-1) using the drive current applied from the (k-1)th selector 237-(k-1). In addition, the kth selector 237-(k) selects at least one of the currents output from the plurality of drive current sources HH, HL, LH, and LL according to the kth power control signal PWRC(k), and outputs the selected current as a drive current. In addition, the kth amplifier 234-(k) outputs a data voltage to the kth data line DL(k) using the drive current applied from the kth selector 237-(k).

[0176] As described above, the display device according to another exemplary embodiment of the present disclosure may apply different drive currents to each of the plurality of amplifiers 234 via the plurality of selectors 237. For example, the display device according to another exemplary embodiment of the present disclosure individually sets the power control signal according to the transition level of the data voltage applied to the plurality of data lines, and may individually set the drive current according to the individually set power control signal.

[0177] Accordingly, the drive current of the source driver integrated circuit of the display device according to another exemplary embodiment of the present disclosure is more finely optimized to minimize power consumption.

[0178] Therefore, a display device according to another exemplary embodiment of the present disclosure has lower power consumption to ensure driving stability by an increased expected lifespan and minimized heat generation.

[0179] The exemplary embodiments of the present disclosure may also be described as follows:

[0180] According to an aspect of the present disclosure, a display device includes: a display panel including a plurality of sub-pixels configured to emit light of different colors; a data driver configured to output data voltages to the plurality of sub-pixels via a plurality of data lines; and a timing controller configured to output a plurality of power control signals for controlling a driving current for driving the data driver, the data driver including a plurality of source driver integrated circuits connected to the plurality of data lines to output data voltages to the plurality of data lines, each of the plurality of source driver integrated circuits including: a plurality of power control circuits configured to generate a driving current according to each of the plurality of power control signals; and a plurality of amplifiers configured to be applied with the driving current to output data voltages to each of the plurality of data lines, and among the plurality of amplifiers, the plurality of amplifiers connected to any one of the plurality of first data lines, the plurality of second data lines, the plurality of third data lines, and the plurality of fourth data lines are connected to any one of the plurality of power control circuits to be applied with the same power control signal.

[0181] The plurality of sub-pixels may include: a plurality of first sub-pixels configured to emit first color light; a plurality of second sub-pixels configured to emit second color light; a plurality of third sub-pixels configured to emit third color light; and a plurality of fourth sub-pixels configured to emit fourth color light. The plurality of first data lines are connected to the plurality of first sub-pixels to be applied with a first data voltage, the plurality of second data lines are connected to the plurality of second sub-pixels to be applied with a second data voltage, the plurality of third data lines are connected to the plurality of third sub-pixels to be applied with a third data voltage, and the plurality of fourth data lines are connected to the plurality of fourth sub-pixels to be applied with a fourth data voltage.

[0182] The timing controller may include: a data enable signal generator configured to generate a sub-data enable signal determining a timing for outputting data voltages to the plurality of sub-pixels; a data delay unit configured to delay video data by one horizontal period to output the delayed video data; a data comparator configured to compare the video data and the delayed video data to generate comparison data; and a power control signal generator configured to generate a power control signal using the comparison data.

[0183] The video data may include first video data corresponding to the gray levels of a first color, second video data corresponding to the gray levels of a second color, third video data corresponding to the gray levels of a third color, and fourth video data corresponding to the gray levels of a fourth color.

[0184] The data comparison unit may include: a first data comparator configured to compare the first video data and the delayed first video data to generate first comparison data; a second data comparator configured to compare the second video data and the delayed second video data to generate second comparison data; a third data comparator configured to compare the third video data and the delayed third video data to generate third comparison data; and a fourth data comparator configured to compare the fourth video data and the delayed fourth video data to generate fourth comparison data.

[0185] The power control signal generator may include: a first power control signal generator configured to generate a first power control signal using the first comparison data; a second power control signal generator configured to generate a second power control signal using the second comparison data; a third power control signal generator configured to generate a third power control signal using the third comparison data; and a fourth power control signal generator configured to generate a fourth power control signal using the fourth comparison data.

[0186] The data comparator may compare the video data and the delayed video data to generate a plurality of comparison data when the sub-data enable signal is at a conductive level.

[0187] The timing controller may send the video data and the power control signal in the form of an embedded clock point-to-point interface (EPI), and the power control signal may be sent to the previous stage of the video data.

[0188] Each of the plurality of source driver integrated circuits may further include: a shift register configured to sequentially determine the data sampling timing according to a data control signal; a latch configured to sequentially align the digital video data according to the data sampling timing; and a digital-to-analog converter configured to convert the digital video data into a data voltage using an analog gamma voltage.

[0189] The power control circuit may include: a first power control circuit configured to provide a drive current according to the first power control signal; a second power control circuit configured to provide a drive current according to the second power control signal; a third power control circuit configured to provide a drive current according to the third power control signal; and a fourth power control circuit configured to provide a drive current according to the fourth power control signal.

[0190] A plurality of amplifiers may include a plurality of first amplifiers connected to a plurality of first data lines, a plurality of second amplifiers connected to a plurality of second data lines, a plurality of third amplifiers connected to a plurality of third data lines, and a plurality of fourth amplifiers connected to a plurality of fourth data lines, and the plurality of first amplifiers may be connected only to a first power control circuit, the plurality of second amplifiers may be connected only to a second power control circuit, the plurality of third amplifiers may be connected only to a third power control circuit, and the plurality of fourth amplifiers may be connected only to a fourth power control circuit.

[0191] The power control circuit may include: a plurality of current sources; a plurality of switches connected to the plurality of current sources to control the plurality of current sources; and a current mirror circuit configured to output a drive current determined according to an on-state of the plurality of switches to the amplifier.

[0192] According to another aspect of the present disclosure, a display device includes: a display panel including a plurality of pixels; a data driver configured to output data voltages to the plurality of pixels via a plurality of data lines; and a timing controller configured to output a plurality of power control signals for controlling a drive current driving the data driver, the data driver including a plurality of source driver integrated circuits connected to the plurality of data lines to output data voltages to the plurality of data lines, each of the plurality of source driver integrated circuits including: a power control signal distributor configured to output each of the plurality of power control signals to each of a plurality of selectors; a plurality of selectors configured to select one of a plurality of drive currents according to each of the plurality of power control signals; and a plurality of amplifiers configured to be applied with a drive current from each of the plurality of selectors to output data voltages to each of the plurality of data lines.

[0193] The power control signal distributor may include: a shift register configured to sequentially shift the plurality of power control signals; and a latch configured to align the shifted plurality of power control signals.

[0194] The timing controller may include: a data enable signal generator configured to generate a sub-data enable signal determining a timing of outputting data voltages to the plurality of pixels; a data delay unit configured to delay video data by one horizontal period to output the delayed video data; a data comparator configured to compare the video data and the delayed video data to generate comparison data; and a power control signal generator configured to generate a power control signal using the comparison data.

[0195] The timing controller may transmit video data and power control signals in the form of an embedded clock point-to-point interface (EPI), and the power control signal may be transmitted to the next stage of the video data.

[0196] According to another aspect of the present disclosure, a display device includes: a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, the plurality of first sub-pixels, the plurality of second sub-pixels, and the plurality of third sub-pixels emitting different color lights; a plurality of first data lines connected to the plurality of first sub-pixels; a plurality of second data lines connected to the plurality of second sub-pixels; a plurality of third data lines connected to the plurality of third sub-pixels; a timing controller configured to output a plurality of power control signals for controlling a driving current; a plurality of power control circuits configured to generate a driving current according to each of the plurality of power control signals; and a plurality of amplifiers configured to be applied with the driving current to output a data voltage to the plurality of first data lines, the plurality of second data lines, and the plurality of third data lines, and among the plurality of amplifiers, the plurality of amplifiers connected to any one of the plurality of first data lines, the plurality of second data lines, and the plurality of third data lines are connected to any one of the plurality of power control circuits to be applied with the same power control signal.

[0197] The timing controller may include: a data comparator configured to compare video data of a corresponding horizontal period with video data of a previous horizontal period to generate comparison data; and a power control signal generator configured to generate a power control signal using the comparison data.

[0198] The power control signal generator may include: a first power control signal generator configured to generate a first power control signal based on the comparison data corresponding to the plurality of first sub-pixels; a second power control signal generator configured to generate a second power control signal based on the comparison data corresponding to the plurality of second sub-pixels; and a third power control signal generator configured to generate a third power control signal based on the comparison data corresponding to the plurality of third sub-pixels.

[0199] The plurality of power control circuits may include: a first power control circuit configured to provide a driving current to the plurality of amplifiers connected to the plurality of first data lines based on the first power control signal; a second power control circuit configured to provide a driving current to the plurality of amplifiers connected to the plurality of second data lines based on the second power control signal; and a third power control circuit configured to provide a driving current to the plurality of amplifiers connected to the plurality of third data lines based on the third power control signal.

[0200] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the provision of the exemplary embodiments of the present disclosure is for illustrative purposes only and is not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The protection scope of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the scope of their equivalents should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: a display panel including a plurality of sub-pixels configured to emit light of different colors; a data driver configured to output data voltages to the plurality of sub-pixels via a plurality of data lines; and a timing controller configured to output a plurality of power control signals for controlling a drive current driving the data driver, wherein the plurality of data lines include a plurality of first data lines, a plurality of second data lines, a plurality of third data lines, and a plurality of fourth data lines, and each of the plurality of first data lines, each of the plurality of second data lines, each of the plurality of third data lines, and each of the plurality of fourth data lines are sequentially arranged, the data driver includes a plurality of source driver integrated circuits connected to the plurality of data lines to output data voltages to each of the plurality of data lines, each of the plurality of source driver integrated circuits includes: a plurality of power control circuits configured to generate drive currents according to each of the plurality of power control signals; and a plurality of amplifiers configured to be applied with drive currents to output data voltages to each of the plurality of data lines, and among the plurality of amplifiers, the plurality of amplifiers connected to any one of the plurality of first data lines, the plurality of second data lines, the plurality of third data lines, and the plurality of fourth data lines are connected to the same power control circuit among the plurality of power control circuits to be applied with the same power control signal.

2. The display device according to claim 1, wherein, the plurality of sub-pixels include: a plurality of first sub-pixels configured to emit light of a first color; a plurality of second sub-pixels configured to emit light of a second color; a plurality of third sub-pixels configured to emit light of a third color; and a plurality of fourth sub-pixels configured to emit light of a fourth color; the plurality of first data lines are connected to the plurality of first sub-pixels to be applied with first data voltages, the plurality of second data lines are connected to the plurality of second sub-pixels to be applied with second data voltages, the plurality of third data lines are connected to the plurality of third sub-pixels to be applied with third data voltages, and the plurality of fourth data lines are connected to the plurality of fourth sub-pixels to be applied with fourth data voltages.

3. The display device according to claim 2, wherein, the timing controller includes: a data enable signal generator configured to generate a sub-data enable signal determining a timing for outputting data voltages to the plurality of sub-pixels; a data delay unit configured to delay video data by one horizontal period to output the delayed video data; a data comparator configured to compare the video data and the delayed video data to generate comparison data; and a power control signal generator configured to generate the power control signals using the comparison data.

4. The display device according to claim 3, wherein, The video data includes first video data corresponding to the gray level of a first color, second video data corresponding to the gray level of a second color, third video data corresponding to the gray level of a third color, and fourth video data corresponding to the gray level of a fourth color.

5. The display device according to claim 4, wherein, the data comparator includes: a first data comparator configured to compare the first video data and the delayed first video data to generate first comparison data; a second data comparator configured to compare the second video data and the delayed second video data to generate second comparison data; a third data comparator configured to compare the third video data and the delayed third video data to generate third comparison data; and a fourth data comparator configured to compare the fourth video data and the delayed fourth video data to generate fourth comparison data.

6. The display device according to claim 5, wherein, the power control signal generator includes: a first power control signal generator configured to generate a first power control signal using the first comparison data; a second power control signal generator configured to generate a second power control signal using the second comparison data; a third power control signal generator configured to generate a third power control signal using the third comparison data; and a fourth power control signal generator configured to generate a fourth power control signal using the fourth comparison data.

7. The display device according to claim 6, wherein, the first power control signal generator generates the first power control signal using the maximum value among a plurality of the first comparison data; the second power control signal generator generates the second power control signal using the maximum value among a plurality of the second comparison data; the third power control signal generator generates the third power control signal using the maximum value among a plurality of the third comparison data; and the fourth power control signal generator generates the fourth power control signal using the maximum value among a plurality of the fourth comparison data.

8. The display device according to claim 3, wherein, the data comparator compares the video data and the delayed video data to generate a plurality of comparison data when the sub-data enable signal is at a conductive level.

9. The display device according to claim 1, wherein, the timing controller transmits the video data and the power control signal in the form of an embedded clock point-to-point interface (EPI), and the power control signal is transmitted to the previous stage of the video data.

10. The display device according to claim 1, wherein, each of the plurality of source driver integrated circuits further includes: a shift register configured to sequentially determine data sampling timings according to a data control signal; a latch configured to sequentially align digital video data according to the data sampling timings; and a digital-to-analog converter configured to convert the digital video data into a data voltage using an analog gamma voltage.

11. The display device according to claim 6, wherein, the plurality of power control circuits include: a first power control circuit configured to provide a driving current according to the first power control signal; a second power control circuit configured to provide a driving current according to the second power control signal; a third power control circuit configured to provide a driving current according to the third power control signal; and a fourth power control circuit configured to provide a driving current according to the fourth power control signal.

12. The display device according to claim 11, wherein, the plurality of amplifiers include a plurality of first amplifiers connected to the plurality of first data lines, a plurality of second amplifiers connected to the plurality of second data lines, a plurality of third amplifiers connected to the plurality of third data lines, and a plurality of fourth amplifiers connected to the plurality of fourth data lines, and the plurality of first amplifiers are only connected to the first power control circuit, the plurality of second amplifiers are only connected to the second power control circuit, the plurality of third amplifiers are only connected to the third power control circuit, and the plurality of fourth amplifiers are only connected to the fourth power control circuit.

13. The display device according to claim 1, wherein, each of the plurality of power control circuits includes: a plurality of current sources; a plurality of switches connected to the plurality of current sources to control the plurality of current sources; and a current mirror circuit configured to output a driving current determined according to the on states of the plurality of switches to the amplifier.

14. A display device, comprising: a display panel including a plurality of pixels; a data driver configured to output data voltages to the plurality of pixels via a plurality of data lines; and a timing controller configured to output a plurality of power control signals for controlling a driving current for driving the data driver, wherein the data driver includes a plurality of source driver integrated circuits connected to the plurality of data lines to output data voltages to the plurality of data lines, and each of the plurality of source driver integrated circuits includes: a power control signal distributor configured to output each of the plurality of power control signals to each of a plurality of selectors; the plurality of selectors configured to select one of a plurality of driving currents according to each of the plurality of power control signals; and a plurality of amplifiers configured to be applied with a driving current from each of the plurality of selectors to output data voltages to each of the plurality of data lines.

15. The display device according to claim 14, wherein, the power control signal distributor includes: a shift register configured to sequentially shift the plurality of power control signals; and a latch configured to align the shifted plurality of power control signals.

16. The display device according to claim 14, wherein, the timing controller includes: A data enable signal generator configured to generate a sub-data enable signal determining a timing for outputting a data voltage to the plurality of pixels; A data delay unit configured to delay video data by one horizontal period to output the delayed video data; A data comparator configured to compare the video data and the delayed video data to generate comparison data; and A power control signal generator configured to generate the power control signal using the comparison data.

17. The display device according to claim 14, wherein, the timing controller is configured to transmit the video data and the power control signal in the form of an embedded clock point-to-point interface (EPI), and the power control signal is transmitted to the next stage of the video data.

18. A display device, comprising: A plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, the plurality of first sub-pixels, the plurality of second sub-pixels, and the plurality of third sub-pixels emitting different color lights; A plurality of first data lines connected to the plurality of first sub-pixels; A plurality of second data lines connected to the plurality of second sub-pixels; A plurality of third data lines connected to the plurality of third sub-pixels; A timing controller configured to output a plurality of power control signals for controlling drive currents; A plurality of power control circuits configured to generate drive currents according to each of the plurality of power control signals; and A plurality of amplifiers configured to be applied with drive currents to output data voltages to the plurality of first data lines, the plurality of second data lines, and the plurality of third data lines, and wherein, among the plurality of amplifiers, the plurality of amplifiers connected to any one of the plurality of first data lines, the plurality of second data lines, and the plurality of third data lines are connected to the same power control circuit among the plurality of power control circuits to be applied with the same power control signal.

19. The display device according to claim 18, wherein, the timing controller includes: A data comparator configured to compare video data of a corresponding horizontal period with video data of a previous horizontal period to generate comparison data; and A power control signal generator configured to generate the plurality of power control signals using the comparison data.

20. The display device according to claim 19, wherein, the power control signal generator includes: A first power control signal generator configured to generate a first power control signal based on the comparison data corresponding to the plurality of first sub-pixels; A second power control signal generator configured to generate a second power control signal based on the comparison data corresponding to the plurality of second sub-pixels; and A third power control signal generator configured to generate a third power control signal based on the comparison data corresponding to the plurality of third sub-pixels.

21. The display device according to claim 20, wherein, the plurality of power control circuits include: A first power control circuit configured to provide drive currents to the plurality of amplifiers connected to the plurality of first data lines based on the first power control signal; A second power control circuit configured to provide a drive current to a plurality of amplifiers connected to the plurality of second data lines based on the second power control signal; and A third power control circuit configured to provide a drive current to a plurality of amplifiers connected to the plurality of third data lines based on the third power control signal.

22. A display device,[[]]END]] comprising:[[]]END]] A display panel including a plurality of sub-pixels configured to emit light of different colors; A data driver configured to output data voltages to the plurality of sub-pixels via a plurality of data lines; and A timing controller configured to output a plurality of power control signals for controlling a drive current for driving the data driver, wherein the data driver includes:[[]]END]] A plurality of power control circuits configured to generate a drive current according to each of the plurality of power control signals; and A plurality of amplifiers configured to be applied with a drive current to output a data voltage to each of the plurality of data lines, and Among the plurality of amplifiers, a plurality of amplifiers connected to a plurality of data lines connected to a plurality of sub-pixels emitting light of the same color are connected to the same power control circuit to be applied with the same power control signal.

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