Method for improving wafer dicing performance and wafer structure

Abstract

The application provides a wafer cutting performance improving method and wafer structure, the method comprises the following steps: providing a wafer provided with a plurality of semiconductor chips, the wafer comprises a substrate layer, a medium layer and a device layer from bottom to top; a cutting path is arranged between adjacent semiconductor chips, a groove structure is formed in the device layer along the cutting path; the position corresponding to the groove structure of the substrate layer is cut from the back surface, and the medium layer is guided to crack along the groove structure to improve the cutting yield. According to the application, the groove structure is formed in the device layer along the cutting path, so that when the position corresponding to the groove structure of the substrate layer is cut from the back surface subsequently, the medium layer is guided to crack along the groove structure, which is beneficial to reduce abnormal phenomena such as cross-section delamination and serpentine, thereby reducing the process difficulty and improving the wafer cutting yield.

Description

Technical Field

[0001] This invention relates to a method for improving wafer dicing performance and a wafer structure. Background Technology

[0002] In the integrated circuit manufacturing process, multiple semiconductor chips (such as image sensor chips and LCD driver chips) are formed on the same wafer. Cutting tracks are set between adjacent semiconductor chips. In the wafer dicing process, the chips are cut along the cutting tracks to form individual semiconductor chips.

[0003] The existing wafer dicing channel designs, both domestically and internationally, generally adopt the following schemes: such as Figure 1 , Figure 2 As shown, a plurality of semiconductor chips 110 are formed on the wafer 100. Four semiconductor chips 110a, 110b, 110c, and 110d are shown as examples. A dicing channel 111 is provided between adjacent semiconductor chips 110a, 110b, 110c, and 110d. The wafer 100 includes a substrate layer 101, a dielectric layer 102, and a device layer 103 from bottom to top. Preferably, a laser dicing method is used to cut all or part of the thickness of the substrate layer 101 from the back side of the wafer along the dicing channel 111. Then, film expansion and dicing are performed so that the dielectric layer 102 and the device layer 103 are correspondingly diced, thereby forming individual semiconductor chips 110a, 110b, 110c, and 110d respectively. As semiconductor process nodes continue to decrease, the dielectric layer 102 is preferably made of a material with a lower dielectric constant (low-K), and multiple metal layers may be disposed in the low dielectric constant material. As the circuit density increases and the number of metal layers increases, the delamination phenomenon between the metal layers and the low dielectric constant material becomes more and more serious. Therefore, in the actual production cutting and dicing process, it is difficult to control the fracture position of the dielectric layer 102, and abnormalities such as cross-sectional delamination and serpentine shape are prone to occur, which in turn affects the cutting yield. Summary of the Invention

[0004] The purpose of this invention is to provide a method and wafer structure for improving wafer dicing performance, reducing abnormal phenomena such as cross-sectional delamination and serpentine patterns, reducing process difficulty, and improving wafer dicing yield.

[0005] To address the aforementioned technical problems, one aspect of the present invention provides a method for improving wafer dicing performance, comprising: providing a wafer having a plurality of semiconductor chips disposed thereon, the wafer comprising, from bottom to top, a substrate layer, a dielectric layer, and a device layer; having dicing channels disposed between adjacent semiconductor chips, and forming a trench structure in the device layer along the dicing channels; dicing the substrate layer at positions corresponding to the trench structure from the back side, and guiding the dielectric layer to cleave along the trench structure to improve dicing yield.

[0006] Preferably, the trench structure is filled with silicide to ensure wafer surface flatness and cleanliness.

[0007] Preferably, the trench structure is formed by dry etching or wet etching.

[0008] Preferably, the trench structure has a depth of more than 2 / 3 of the thickness of the device layer.

[0009] Preferably, the trench structure is continuously or discontinuously arranged along the length direction of the scribe lane, and the total length of the trench structure covers more than 1 / 2 of the total length of the scribe lane.

[0010] Preferably, the trench structure is arranged in the middle region of the scribe lane in the width direction.

[0011] Preferably, when the ratio of the trench structure width to the scribe lane width is greater than or equal to a threshold value, the trench structure can be arranged in the non-middle region of the scribe lane in the width direction.

[0012] Preferably, the substrate layer is cut from the back by laser scribing or mechanical cutting to a full or partial thickness.

[0013] Preferably, the device layer includes semiconductor material and metal test pads, and the trench structure is formed in both the semiconductor material and the metal test pads.

[0014] Preferably, the device layer further includes a metrology structure located on one side or both sides of the trench structure.

[0015] Preferably, metal vias are formed on both sides of the trench structure, and the metal vias connect multiple layers of metal test pads.

[0016] Another aspect of the present application provides a wafer structure for improving wafer cutting performance, wherein the wafer provided with a plurality of semiconductor chips includes, from bottom to top, a substrate layer, a dielectric layer, and a device layer; a scribe lane is arranged between adjacent semiconductor chips, and a trench structure is arranged in the device layer along the scribe lane, so that when the substrate layer is subsequently cut from the back at a position corresponding to the trench structure, the dielectric layer is guided to crack along the trench structure, thereby improving the cutting yield.

[0017] Preferably, the trench structure is filled with silicide to ensure wafer surface flatness and cleanliness.

[0018] Preferably, the trench structure has a depth of more than 2 / 3 of the thickness of the device layer.

[0019] Preferably, the trench structure is continuously or discontinuously arranged along the length direction of the scribe lane, and the total length of the trench structure covers more than 1 / 2 of the total length of the scribe lane.

[0020] Preferably, the groove structure is disposed in the middle region of the width direction of the cutting channel.

[0021] Preferably, when the ratio of the width of the groove structure to the width of the cutting channel is greater than or equal to a threshold, the groove structure can be set in a non-middle region in the width direction of the cutting channel.

[0022] Preferably, the device layer includes semiconductor material and metal test pads, and the trench structure is provided in both the semiconductor material and the metal test pads.

[0023] Preferably, the device layer further includes a measurement structure located on one or both sides of the trench structure.

[0024] Preferably, the trench structure has metal through holes on both sides, and the metal through holes connect to multiple layers of metal test pads.

[0025] The present invention provides a method and wafer structure for improving wafer dicing performance. By forming a trench structure in the device layer along the dicing path, the dielectric layer is guided to split along the trench structure when the substrate layer is subsequently diced from the back side to the position corresponding to the trench structure. This helps to reduce abnormal phenomena such as cross-sectional delamination and serpentine patterns, thereby reducing process difficulty and improving wafer dicing yield. Attached Figure Description

[0026] Figure 1 This is a partial schematic diagram of a wafer structure based on existing technology;

[0027] Figure 2 For along Figure 1 Schematic diagram of the cross section of line AA;

[0028] Figure 3 This is a partial schematic diagram of a wafer structure according to an embodiment of the present invention;

[0029] Figure 4 , Figure 5 For along Figure 3 Schematic diagram of the cross section of the middle BB line;

[0030] Figure 6 for Figure 3 Enlarged view of region C in the middle;

[0031] Figure 7 For along Figure 6 Schematic diagram of cross section of the DD line.

[0032] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation

[0033] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without the specific details set forth in this description. In other instances, well-known methods have not been described in detail in order not to unnecessarily obscure aspects of the present application.

[0034] Secondly, the present application is described in detail by using schematic diagrams, which are only examples for the purpose of illustration and should not limit the scope of protection of the present application.

[0035] In order to make the above objectives, features and advantages of the present application more apparent and comprehensible, the present application is described in detail below in combination with the drawings.

[0036] The present application provides a method for improving wafer cutting performance, comprising: providing a wafer provided with a plurality of semiconductor chips, the wafer comprising a substrate layer, a dielectric layer and a device layer from bottom to top; a cutting lane is arranged between adjacent semiconductor chips, a groove structure is formed in the device layer along the cutting lane; the substrate layer is cut from the back surface at a position corresponding to the groove structure, and the dielectric layer is guided to crack along the groove structure to improve the cutting yield.

[0037] Figure 3 、 Figure 4 、 Figure 5 A wafer structure according to a preferred embodiment of the present application is shown, in which a plurality of semiconductor chips 210 are formed on a wafer 200, four semiconductor chips 210a, 210b, 210c, 210d are shown as examples, and a cutting lane 211 is arranged between adjacent semiconductor chips 210a, 210b, 210c, 210d. The wafer 200 comprises a substrate layer 201, a dielectric layer 202 and a device layer 203 from bottom to top, wherein the substrate layer 201 is preferably silicon, the dielectric layer 202 is preferably a low dielectric constant material such as silicon oxide, silicon nitride, silicon oxynitride, and the device layer 203 is preferably silicon.

[0038] According to the method for improving wafer cutting performance of the present application, a groove structure 212 is formed in the device layer 203 along the cutting lane 211, preferably, a dry or wet etching process can be used to form the groove structure 212 (as shown in Figure 4 Further preferably, a silicide can be filled in the groove structure 212 (as shown in Figure 5As shown, this ensures the flatness and cleanliness of the wafer surface. Therefore, in subsequent steps, the substrate layer 201 corresponding to the trench structure 212 can be cut from the back of the wafer (for example, by using laser slicing or mechanical cutting to cut all or part of the thickness of the substrate layer 201 from the back of the wafer), guiding the dielectric layer 202 to split along the trench structure 212. This helps reduce abnormal phenomena such as cross-sectional delamination and serpentine patterns, thereby reducing process difficulty and improving wafer cutting yield.

[0039] exist Figure 4 , Figure 5 In the preferred embodiment shown, the trench structure 212 extends through the entire thickness of the device layer 203. In other preferred embodiments not shown, the depth of the trench structure 212 is at least 2 / 3 of the device layer thickness, thus achieving the purpose of guiding the dielectric layer 202 to split along the trench structure 212.

[0040] Furthermore, those skilled in the art will understand that the groove structure 212 can be continuously or discontinuously arranged along the length of the cutting channel. Preferably, the total length of the groove structure 212 covers more than 1 / 2 of the total length of the cutting channel 211 to ensure a better guiding effect of the medium layer 202 cracking along the groove structure 212.

[0041] Figure 6 for Figure 3 An enlarged schematic diagram of region C in this preferred embodiment shows that the groove structure 212 is along the length direction of the cutting path (i.e., Figure 6 The groove structure 212 is discontinuously arranged in the Y-direction and is located in the width direction of the cutting path (i.e., in the Y-direction). Figure 6 The middle region in the X direction. In other preferred embodiments not shown, when the ratio of the groove structure width W1 to the cutting track width W2 is greater than or equal to a threshold (e.g., greater than 1:3), the groove structure 212 may also be located in a non-middle region in the cutting track width direction.

[0042] like Figure 6 , Figure 7 As shown, the semiconductor material (e.g., silicon) 215 of the device layer 203 has a plurality of metal test pads 213. Preferably, trench structures 212 are formed in both the semiconductor material 215 and the metal test pads 213. Furthermore, the device layer 203 may also include a plurality of measurement structures 214. Preferably, the measurement structures 214 are distributed on one or both sides of the trench structures 212, and are arranged to avoid overlapping with the trench structures 212 as much as possible to avoid affecting the signal lines during cutting. More preferably, metal vias 216 may be formed on both sides of the trench structures 212. These metal vias 216 connect the multilayer metal test pads 213 and also reinforce the trench structures 212 to better control the cracking direction and reduce serpentine phenomena.

[0043] To sum up, the method for improving wafer cutting performance and wafer structure of the present application form a trench structure in the device layer along the cutting path, so that when the substrate layer is subsequently cut from the back surface at the position corresponding to the trench structure, the dielectric layer is guided to crack along the trench structure, which is advantageous to reduce abnormal phenomena such as cross-section delamination and serpentine, thereby reducing the process difficulty and improving the cutting yield of the wafer.

[0044] Although the present application has been disclosed with the above preferred embodiments, it is not intended to limit the present application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the present application by using the disclosed methods and technical contents without departing from the spirit and scope of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, which does not deviate from the technical solutions of the present application, shall fall within the protection scope of the technical solutions of the present application.

Claims

1. A method of improving wafer dicing performance, characterized by, The application relates to a wafer structure for improving wafer cutting performance. The wafer provided with a plurality of semiconductor chips comprises, from bottom to top, a substrate layer, a medium layer and a device layer; A cutting channel is arranged between adjacent semiconductor chips, and a groove structure is formed in the device layer along the cutting channel, the device layer comprising semiconductor material and a metal test pad, and the groove structure being formed in the semiconductor material and the metal test pad; The substrate layer is cut from the back surface at a position corresponding to the groove structure, and the medium layer is guided to crack along the groove structure to improve the cutting yield; The device layer further comprises a measurement structure located on one side or both sides of the groove structure.

2. The method of improving wafer dicing performance according to claim 1, wherein, The groove structure is filled with silicide to ensure wafer surface flatness and cleanliness.

3. The method of claim 1, wherein the wafer dicing performance is improved by the step of: The groove structure is formed by dry etching or wet etching.

4. The method of claim 1, wherein the wafer dicing performance is improved by the step of: The depth of the groove structure is more than 2 / 3 of the thickness of the device layer. ​ 5. The method of claim 1, wherein the wafer dicing performance is improved by the step of: The groove structure is continuously arranged or discontinuously arranged along the length direction of the cutting channel, and the total length of the groove structure covers more than 1 / 2 of the total length of the cutting channel. ​ 6. The method of claim 1, wherein the wafer dicing performance is improved by the step of: The groove structure is arranged in the middle region of the cutting channel in the width direction.

7. The method of claim 1, wherein the wafer dicing performance is improved by the step of: When the ratio of the width of the groove structure to the width of the cutting channel is greater than or equal to a threshold value, the groove structure is arranged in a non-middle region of the cutting channel in the width direction. ​ 8. The method of claim 1, wherein the wafer dicing performance is improved by the step of: The substrate layer is cut from the back surface by laser hidden cutting or mechanical cutting.

9. The method of claim 1, wherein the wafer dicing performance is improved by the step of: Metal through holes are formed on both sides of the groove structure, and the metal through holes connect the metal test pads of multiple layers. ​ 10. A wafer structure for improving wafer cutting performance, characterized in that The wafer provided with a plurality of semiconductor chips comprises, from bottom to top, a substrate layer, a medium layer and a device layer; A cutting channel is arranged between adjacent semiconductor chips, and a groove structure is formed in the device layer along the cutting channel, the device layer comprising semiconductor material and a metal test pad, and the groove structure being formed in the semiconductor material and the metal test pad; The substrate layer is cut from the back surface at a position corresponding to the groove structure, and the medium layer is guided to crack along the groove structure to improve the cutting yield; 11. The wafer structure for improving wafer dicing performance according to claim 10, wherein, The device layer further comprises a measurement structure located on one side or both sides of the groove structure.

12. The wafer structure for improving wafer dicing performance according to claim 10, wherein, The groove structure is filled with silicide to ensure wafer surface flatness and cleanliness.

13. The wafer structure for improving wafer dicing performance according to claim 10, wherein The depth of the groove structure is more than 2 / 3 of the thickness of the device layer.

14. The wafer structure for improving wafer dicing performance according to claim 10, wherein, The groove structure is continuously arranged or discontinuously arranged along the length direction of the cutting channel, and the total length of the groove structure covers more than 1 / 2 of the total length of the cutting channel.

15. The wafer structure for improving wafer dicing performance according to claim 10, wherein The groove structure is arranged in the middle region of the cutting channel in the width direction.

16. The wafer structure for improving wafer dicing performance according to claim 10, wherein, When the ratio of the width of the groove structure to the width of the cutting channel is greater than or equal to a threshold value, the groove structure is arranged in a non-middle region of the cutting channel in the width direction. The groove structure is arranged in the middle region of the cutting channel in the width direction. Metal through holes are formed on both sides of the groove structure, and the metal through holes connect the metal test pads of multiple layers.

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