Memory subsystem fabrication mode

Abstract

A method includes enabling a manufacturing mode based at least in part on a first signal provided via one of a number of reserved pins of an interface connector. The method can further include providing a second signal to a memory component coupled to the interface connector via a number of other pins of the interface connector in response to enabling the manufacturing mode.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to memory subsystem manufacturing patterns. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof.

[0004] Figure 1 This describes an example computing system according to some embodiments of the present disclosure, which includes an interface connector coupled to a host system and a memory subsystem.

[0005] Figure 2 Examples of interface connectors according to some embodiments of this disclosure are described.

[0006] Figure 3 Examples of circuit systems including interface connectors for enabling / disabling manufacturing modes, according to some embodiments of this disclosure, are described.

[0007] Figure 4 A flowchart illustrating an example method of operating a memory component in a manufacturing mode according to some embodiments of the present disclosure.

[0008] Figure 5 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0009] Various aspects of this disclosure relate to circuit systems for operating a memory subsystem in a manufacturing process. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 And other examples of diagrams illustrating storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0010] Before a memory subsystem is available to a customer, the manufacturer (e.g., a supplier) may need to operate the memory subsystem to test and / or diagnose it, and / or provide the necessary software (e.g., firmware). To achieve this, the manufacturer may couple the memory subsystem to a manufacturer-prepared host system that can boot the memory subsystem into a manufacturing mode, during which the memory subsystem can be tested, diagnosed, and / or equipped with the necessary firmware (e.g., firmware images). More specifically, the manufacturer-prepared host system can boot an interface connector to provide specific signals to the memory subsystem controller, which enables the memory subsystem to be placed into manufacturing mode. The interface connector is used to couple the manufacturer-prepared host system to the memory subsystem.

[0011] Providing signals from the interface connector to the memory subsystem controller may involve utilizing several pins (e.g., pins of the interface connector), and typically, the complexity of enabling manufacturing modes for the memory subsystem can depend on the pin type and / or number of pins of the interface connector being utilized. For example, using more pins and / or different types of pins simultaneously can increase the complexity of the circuitry used to enable manufacturing modes, which can make the initialization or pre-initialization phase of the memory subsystem's manufacturing time-consuming and / or costly.

[0012] The aspects of this disclosure address the above and other drawbacks by providing a more efficient and / or flexible method for controlling the activation of manufacturing modes compared to prior methods. For example, embodiments may include controlling manufacturing modes via fewer pins (e.g., a single pin in some implementations) compared to conventional methods. In some embodiments, multiple pins of the same type, such as reserved pins that might not be used in prior methods, may be used to implement manufacturing modes. Thus, the embodiments described herein provide a less complex circuitry implementation, which can reduce the costs associated with manufacturing memory subsystems and / or result in less time-consuming manufacturing stages. Furthermore, since some embodiments described herein utilize pins not previously used for manufacturing modes (e.g., reserved pins), those pins previously used to enable manufacturing modes can be used for different operations and / or functions.

[0013] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such media.

[0014] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0015] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0016] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0017] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0018] In some embodiments, host system 120 may be a host system configured to (e.g., boot memory subsystem 110) test, diagnose, and / or provide firmware (e.g., firmware 105) to the manufacturer of memory subsystem 110. Firmware 105 to be provided to memory subsystem 110 may be manufacturing test firmware (e.g., manufacturing test firmware that allows testing and / or diagnosing memory subsystem 110), operating system firmware, and / or firmware that needs to be loaded into memory subsystem 110 (e.g., memory subsystem controller 115) before memory subsystem 110 becomes available to a customer (e.g., an entity purchasing the memory subsystem from the manufacturer).

[0019] Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0020] Computing system 100 may include an interface connector 112 coupled to a physical host interface. As used herein, the term "interface connector" refers to a physical connector implemented using a particular of various communication protocols (e.g., one of the communication protocols described above in conjunction with the physical host interface). Interface connector 112 may translate commands received from host system 120 into command instructions for accessing memory devices 130 and / or memory devices 140, and translate responses associated with memory devices 130 and / or memory devices 140 into information for host system 120. In some embodiments, interface connector 112 may be part of and / or embedded within memory subsystem 110.

[0021] In several embodiments, the interface connector 112 may include several pins and / or pins of different types for transmitting control, address, and / or data in other signals between the memory subsystem 110 and the host system 120. For example, the interface connector 112 may convert commands received from the host system 120 via several pins into command instructions (e.g., in the form of various signals) to access memory devices 130 and / or 140, and convert responses associated with memory devices 130 and / or 140 into information for the host system 120 (e.g., in the form of various signals) via several pins. Figure 2 and Figure 3 Further details are described regarding how several pins and different types of pins are used to facilitate communication between the memory subsystem 110 and the host system 120.

[0022] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0023] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, in contrast to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0024] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0025] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND-type memories (e.g., 2D NAND and 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0026] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (e.g., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. In some embodiments, the memory subsystem controller 115 may be configured to serve the memory subsystem 110 (e.g., host system 120 and / or memory devices 130 and / or 140) via an NVMe interface.

[0027] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0028] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) (e.g., boot ROM) for storing microcode and / or instructions that allow memory subsystem controller 115 to request firmware 105 from host system 102. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0029] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate those commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may also be responsible for other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130.

[0030] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access memory devices 130 and / or 140.

[0031] In some embodiments, memory device 130 includes a local media controller 135 that operates together with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0032] The memory subsystem controller 113 includes a manufacturing mode component 113, which can be configured to schedule and / or perform operations associated with manufacturing mode and / or enabling / disabling manufacturing mode. Although Figure 1 While not shown in the diagrams for the sake of clarity, the manufacturing mode component 113 may include various circuit systems to facilitate the operations described herein. For example, the manufacturing mode component 113 may include dedicated circuit systems in the form of an ASIC, FPGA, state machine, and / or other logic circuit systems that allow the manufacturing mode component 113 to arrange and / or perform the operations described herein.

[0033] Such as combination Figure 2 , Figure 3 and Figure 4 In more detail, the manufacturing mode component 113 can be configured to determine whether the memory subsystem 110 (e.g., memory subsystem controller 115) needs to be placed in manufacturing mode, which can be further determined based on whether the memory subsystem controller 115 currently contains firmware (e.g., firmware 105). In response to determining that the memory subsystem 110 does not contain firmware, the manufacturing mode component 113 can request to enable manufacturing mode, such that the memory subsystem controller 115 can be equipped with firmware during manufacturing mode. When the operations associated with manufacturing mode are completed (e.g., firmware 105 is received and stored in the memory subsystem controller 115), the manufacturing mode component 113 can further request to deactivate manufacturing mode.

[0034] In some embodiments, the operations performed by the manufacturing mode component 113 may be performed during the initialization or pre-initialization phase of the manufacture of the memory subsystem 110 and / or the memory subsystem controller 115. Therefore, in some embodiments, the manufacturing mode component 113 may perform the operations described herein during manufacturing and / or after the manufacture of the memory subsystem 110 but before packaging the memory subsystem 110. However, embodiments are not limited thereto, and in some embodiments, the manufacturing mode component 113 may perform the operations described herein during the operation phase of the memory subsystem 110 to, for example, request the provision of firmware 105 to the memory subsystem 110 and / or the memory subsystem controller 115.

[0035] In some embodiments, the memory subsystem controller 115 includes at least a portion of the manufacturing mode component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the manufacturing mode component 113 is part of the host system 110, an application, or an operating system.

[0036] Figure 2 Examples of interface connector 212 according to some embodiments of this disclosure are described. Interface connector 212 may be similar to... Figure 1 The interface connector 112 is described herein. Although the embodiments are not limited to utilizing a particular type of interface connector, Figure 2 The interface connector 212 described herein may be an SFF-8639 (also referred to as U.2) and / or an SFF-TA-1001 (also referred to as U.3) connector.

[0037] Interface connector 212 can be configured to communicate with a host system and / or device via several pins, such as Figure 2 As explained herein, the term "pin" refers to a physical interface that provides electrical terminals and enables communication with other devices. Figure 2 As illustrated in the non-limiting example, interface connector 212 includes pins S1, ..., S7 (230-1, ..., 230-7, respectively), E1, ..., E6 (232-1, ..., 232-6, respectively), P1, ..., P15 (236-1, ..., 236-15, respectively), E7, ..., E16 (232-7, ..., 232-16, respectively), S8, ..., S28 (230-8, ..., 230-28, respectively), and E17, ..., E25 (232-17, ..., 232-25, respectively). In several embodiments, commands, addresses, and / or data can be communicated in the form of signals via several pins of interface connector 212.

[0038] According to methods such as those defined by the Storage Networking Industry Association (SNIA) (formerly known as the Small Form Factor (SFF) Committee), interface connectors such as Interface Connector 212 can be configured to provide signals via pins S15 (e.g., pins 230-15, also referred to as Host Port Type (HPT) 0 pin), E16 (pins 232-16, also referred to as HPT 1 pin), and E25 (pins 232-25, also referred to as Dual Port Enable pin) to enable the manufacturing mode of the memory subsystem and / or memory component. These pins can be used to determine which type of slot the device (e.g., the memory subsystem) is compatible with, which type of host protocol the device is compatible with, and / or whether dual port mode is enabled. According to the SFF-TA-1001 specification, for example, pin S15 can be used to distinguish whether a device coupled to the host system via an interface connector (e.g., interface connector 212) is an SFF-8369SSD or an SFF-TA-1001SSD; pin E16 can be used to distinguish whether the host protocol coupled to the device via the interface connector is PCIe, Gen-Z, or an undefined host protocol; and pin E25 can be used to indicate whether dual-port mode should be enabled. The corresponding operating modes based on the combinations of values ​​indicated by pins S15, E16, and E25 (e.g., "high" corresponds to logic "1" and "low" corresponds to logic "0") are listed in Table 1 below:

[0039] S15 E16 E25 Device operation mode high high high 4 single-ended host ports Quad PCIe high high Low 2 dual-ended host ports Quad PCIe Low high high 4 single-ended host ports SFF-TA-1001 Low high Low 2 dual-ended host ports SFF-TA-1001 high Low high 4 single-ended Gen-z high Low Low 2 dual-ended Gen-Z Low Low high 4 single-ended undefined Low Low Low Manufacturing Model

[0040] Table 1: Operating Modes

[0041] For example, as described in Table 1, pins S15 and E16 can be confirmed as high and pin E25 can be confirmed as low, indicating that the host system is using the PCIe host protocol and that the memory subsystem coupled to the host system via the interface connector is an SFF-8639SDD without enabling single-port mode.

[0042] As further listed in Table 1, manufacturing mode can be enabled by utilizing all three S15, E16, and E25 pins. For example, interface pins S15, E16, and E25 can be confirmed as low (e.g., floating), which indicates the enablement of manufacturing mode according to SINA.

[0043] As described herein, enabling manufacturing modes using multiple pins of different types (e.g., S15, E16, and E25) can increase the complexity of the circuitry of a memory subsystem (e.g., memory subsystem 110). In contrast, the embodiments described herein can enable manufacturing modes using a single pin and / or multiple pins of the same type (e.g., reserved pins, such as reserved “P” pins), which can reduce the costs associated with manufacturing the memory subsystem and / or make the manufacturing phase of the memory subsystem less time-consuming. As used herein, a “reserved pin” refers to a pin that does not have a dedicated purpose assigned to it according to a particular specification or interface connector type. In particular, the embodiments described herein utilize at least one of the P7, P8, and / or P9 pins already used to provide a 5V supply voltage, which the SFF-8369 and SFF-TA-1001 interface connectors are incompatible with (e.g., because they are compatible with 3.3V and / or 12V). Therefore, by utilizing the P pins that are not yet used in the SFF-8369 and SFF-TA-1001 interface connectors, the embodiments described herein enable S15, E16, and E25 to be used for other operations and / or functionality, at least during manufacturing.

[0044] Figure 3 Examples of circuitry 316 comprising an interface connector 312 for enabling / disabling manufacturing modes, according to some embodiments of this disclosure, are described below. Circuitry 316 may be a memory subsystem (e.g., Figure 1 This is part of the memory subsystem described herein. Interface connector 312 may be similar to... Figure 2 and Figure 3 The interface connectors 112 and 212 described herein may be SFF-8639 (also referred to as U.2) and / or SFF-TA-1001 (also referred to as U.3) connectors, but the embodiments are not limited thereto. The example circuit system 316 may also include a memory subsystem controller 315 that may be similar to the memory subsystem controller 115.

[0045] exist Figure 3 In the embodiments described herein, logic gate 342 is coupled to memory subsystem controller 315 and to interface connector 312. In several embodiments, logic gate 342 may be configured to receive signals from interface connector 312 and memory subsystem controller 315. Signals transmitted between interface connector 312, logic gate 342, and memory subsystem controller 315 may be binary in nature. For example, signal 341 received from interface connector 312 at logic gate 342 may correspond to logic 1 (e.g., high) or logic 0 (e.g., low), where a binary value indicates enable (e.g., by...). Figure 1The host system 120 described herein enables manufacturing mode, while another binary value indicates that manufacturing mode is disabled. For example, signal 345 (MFG_MODE_EN), which is called the manufacturing mode enable signal received from the memory subsystem controller 315 at logic gate 342, can be switched high or low to indicate whether the memory subsystem controller 315 has requested manufacturing mode. Although the embodiment is not limited to this, in this example, logic gate 342 is an AND gate.

[0046] Signal 341 can be transmitted via several P pins of interface connector 312 (e.g. Figure 2 At least one of the pins 236-1 to 236-15 described herein is provided to logic gate 342. Several P-pins coupling interface connector 312 to logic gate 342 may include pin P7 (… Figure 2 The following are excerpts from 236-7 and P8. Figure 2 236-8) and / or P9 as described in the document Figure 2 (as described in 236-9). In response to receiving a command (e.g., enabling manufacturing mode), one of the P7, P8, and P9 pins can be confirmed high to provide a high signal to logic gate 342. However, the embodiments are not limited to this, and more than one of the P7, P8, and / or P9 pins can be used to provide a signal to logic gate 342. For example, two or all three of the P7, P8, and P9 pins can provide a corresponding signal to logic gate 342 to enable manufacturing mode.

[0047] In some embodiments, for example, pins P7, P8, and / or P9 can be used to provide a supply voltage such as 5V. For memory subsystems compatible with different (e.g., lower) supply voltages (e.g., 3.3V), an additional resistor / resistor 346 can be added to the signal line carrying signal 341 so that the signal 341 supplied to logic gate 342 and / or memory subsystem controller 315 does not exceed the corresponding voltage tolerance limit.

[0048] The logic value of the provided signal can be adjusted via an open / drain circuit system including a pull-up resistor 343, which is used to ensure the state of the signal is known. For example, in response to the open-drain circuit system being in the open state, the pull-up resistor 343 ensures that the signal 341 provided from the P pin is high (e.g., logic "1"), and in response to the open-drain circuit system being in the drain state, the pull-up resistor 343 ensures that the signal 341 provided from the P pin is low (e.g., logic "0").

[0049] In response to signals from both the memory subsystem controller 315 and the interface connector 312 indicating the enable of the manufacturing mode (e.g., high), logic gate 342 may provide a signal 347 (SIO_SELECT), referred to as a switch signal, to multiplexer 348. The state of signal 347 (e.g., high / low) indicates whether the manufacturing mode is enabled.

[0050] In response to receiving a switch signal 347 (e.g., a high signal) from logic gate 342, multiplexer 348 can be configured to couple interface connector 312 to memory subsystem controller 315. For example, multiplexer 348 can couple signal lines 349 and 340 (coupled to interface connector 312 via several E pins) to signal lines 342 and 344 (coupled to memory subsystem controller 315 via a Universal Asynchronous Receiver / Transmitter (UART)). Signals provided to memory subsystem controller 315 via signal lines 349 and 340 can be provided from interface connector 312 via several E pins, such as E23 and E24 pins (e.g., ...). Figure 2 Pins 232-23 and 232-24 are described in the document. When signal lines 342 and 344 are coupled to signal lines 349 and 340 respectively, the host system (e.g., Figure 1 The host system 120 described herein can transmit firmware (e.g., Figure 1 The firmware 105 described herein is provided to the memory subsystem controller 315 (e.g., via pins E23 and E24).

[0051] When manufacturing mode is disabled (e.g., signals 341 or 345 are low / deacknowledged, causing signal 347 to be low / deacknowledged), multiplexer 348 can be configured to couple (e.g., maintain coupling) signal lines 349 and 340 (e.g., coupled to interface connector 312 via E23 and E24 pins) to signal lines 343 and 347, which can be used as sideband channels, such as sideband channels implemented by the System Management Bus (SMB). For example, signal line 349 coupled to signal line 343, which serves as an SMB sideband channel, can be used to transmit data (e.g., ...). Figure 3 The signal line 340, coupled to the signal line 347 which serves as the SMB sideband channel, can be used to transmit clock signals (such as SMBDAT as described above). Figure 3 (SMBCLK as described in the document).

[0052] Figure 4 Flowchart 450 illustrates an example method of operating a memory component in a manufacturing mode according to some embodiments of the present disclosure. At block 452, it may be based at least in part on an interface connector (e.g., respectively at...) Figure 1 , Figure 2 and Figure 3 A first signal is provided by one of several reserved pins of the interface connectors 112, 212, and / or 312 described herein to enable the manufacturing mode. As described herein, the reserved pins may include several P pins (e.g., Figure 2 The P pins 236 described herein, such as P7, P8 and / or P9 pins (e.g., Figure 2 (Pin 236-7, 236-8, and / or 236-9 as illustrated). In contrast to some methods that enable manufacturing mode by utilizing host port configuration type pins (e.g., E16, S15, and / or E25 pins), at block 452, the interface connector can be configured to transmit a signal enabling manufacturing mode without utilizing host port configuration type pins.

[0053] At block 454, a second signal may be provided to a memory component coupled to an interface connector in response to enabling a manufacturing mode (e.g., based on a first signal). The memory component may resemble a memory subsystem (e.g., Figure 1 One of the components of the memory subsystem 110 described herein, such as the memory subsystem controller (e.g., in...). Figure 1 and Figure 2 The memory subsystem controllers 115 and / or 315 described herein). The second number of pins may include, for example, several E pins of an interface connector (e.g., Figure 2 The E pin 232 is described in the document.

[0054] In some embodiments, the second signal may include data to be transmitted to a memory component and / or a memory subsystem, and the data may include data from a host system (e.g., Figure 1 The firmware provided by the host system 110 described herein, such as manufacturing test firmware, operating system firmware, or any combination thereof.

[0055] Figure 5 An example machine is described as a computer system 541, within which a set of instructions is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 541 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations related to...). Figure 1(The operation corresponding to manufacturing mode component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, with the capabilities of a server or client machine in a client-server network environment.

[0056] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or another machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" should be considered to include a collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0057] Example computer system 541 includes a processing device 502, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0058] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 541 may further include a network interface device 508 for communication via network 520.

[0059] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more sets of instructions 526 or software embodying one or more of the methods or functions described herein are stored. The instructions 526 may also reside wholly or at least partially in main memory 504 and / or processing device 502 during execution by computer system 541, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0060] In one embodiment, instruction 526 includes instructions for implementing a computing component (e.g., Figure 1 The instructions may include functional instructions for the computing component 113. These instructions may include those for use with a manufacturing mode component (e.g., Figure 1 The manufacturing mode component 113 executes the operation-associated manufacturing mode instructions 513. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. It should also be considered that the term "machine-readable storage medium" includes media capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0061] Some parts of the previously described in detail have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented in a way that those skilled in the art of data processing can most effectively communicate the essence of their work to others skilled in the art. The algorithms in this paper generally refer to a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical control over a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for general reasons, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0062] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0063] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, disk types or media suitable for storing electronic instructions, each connected to a computer system bus, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards.

[0064] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. Structures for various such systems will be presented as described below. Furthermore, this disclosure is described without reference to a particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0065] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes mechanisms for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, and the like.

[0066] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the invention without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method for enabling a manufacturing mode, comprising: The manufacturing mode is enabled at least in part based on a first signal provided via one of several reserved pins of an interface connector, wherein the reserved pins are configured to provide a supply voltage compatible with a communication protocol of the first type; and In response to enabling the manufacturing mode, a second signal is provided via several other pins of the interface connector to a memory component that operates according to a second type of communication protocol and is coupled to the interface connector.

2. The method of claim 1, further comprising providing the first signal without using the host port configuration type pin of the interface connector.

3. The method of claim 1, further comprising providing the first signal without using several enable pins of the interface connector, wherein the interface connector corresponds to an SFF-8639 or SFF-TA-1001 interface connector.

4. The method according to any one of claims 1 to 3, further comprising providing data corresponding to firmware to the memory component via the second signal, wherein the firmware corresponds to at least one of the following: Manufacturing test firmware; Operating system firmware; or Any combination thereof.

5. A system for enabling a manufacturing mode, comprising: Interface connector; and A multiplexer coupled to the interface connector via logic gates; The interface connector is configured to provide a first signal to the logic gate via at least one of a plurality of reserved pins, including power supply pins of the interface connector corresponding to the SFF-8639 or SFF-TA-1001 interface connector, wherein a manufacturing mode is enabled at least in part based on the first signal provided via at least one of the plurality of reserved pins. The logic gates are configured to provide switching signals to the multiplexer based at least in part on the first signal; and The multiplexer is configured to couple the interface connector to the memory component, such that the interface connector is configured to provide a second signal to the memory component during the manufacturing mode.

6. The system of claim 5, wherein the second signal includes data corresponding to the manufacturing test firmware.

7. The system according to any one of claims 5 and 6, wherein: The interface connector includes several pins for transmitting system management bus data SMBDAT and system management bus clock signal SMBCLK; and The interface connector is configured to provide the second signal to the memory component via at least one of the plurality of pins during the manufacturing mode.

8. The system of claim 7, wherein the plurality of pins includes a plurality of enable pins of the interface connector corresponding to the SFF-8639 or SFF-TA-1001 interface connector.

9. The system of claim 7, wherein the multiplexer is configured to couple the interface connector to the memory component to initiate the manufacturing mode, such that a Universal Asynchronous Receiver / Transmitter (UART) transmit signal and a UART receive signal are transmitted from the interface connector to the memory component.

10. The system according to any one of claims 5 and 6, wherein the multiplexer is configured to couple the system management bus data SMBDAT line and the system management bus clock SMBCLK line to the interface connector in the absence of the first signal from the interface connector.

11. The system according to any one of claims 5 and 6, wherein the interface connector is a peripheral component interconnect high-speed PCIe connector.

12. A system for enabling a manufacturing mode, comprising: An interface connector configured to provide a first signal via one of a plurality of reserved pins to place the system in a manufacturing mode, wherein the plurality of reserved pins are configured to provide a supply voltage compatible with a communication protocol of a first type; and A memory component, which operates according to a communication protocol of the second type and is coupled to the interface connector, wherein the memory component is further configured to provide a second signal to a logic gate to place the system in the manufacturing mode; The system is placed in the manufacturing mode in response to the logic gate receiving the first signal via one of the plurality of reserved pins.

13. The system of claim 12, wherein the interface connector comprises: The first group of pins corresponding to the plurality of reserved pins; and Second set of pins; The memory component is configured to receive data corresponding to firmware via at least one of the second set of pins of the interface connector when the system is in the manufacturing mode.

14. The system according to claim 13, wherein: The memory component is configured to provide a third signal to the logic gate in response to the firmware being received and stored in the memory component; and The manufacturing mode is deactivated in response to the logic gate receiving the third signal from the memory component.

15. The system according to any one of claims 12 and 13, further comprising a multiplexer coupled to the logic gate via a shared input / output SIO line, wherein: The logic gate is configured to provide a switching signal to the multiplexer via the SIO line in response to receiving the first signal from the memory component and the second signal from the logic gate; and The multiplexer is configured to couple the memory component to the interface connector in response to receiving the switching signal from the logic gate.

16. The system of any one of claims 12 and 13, wherein the data line of the interface connector coupled to the memory component via one of the plurality of reserved pins is further coupled to an external pull-up resistor.

17. The system according to any one of claims 12 and 13, wherein the logic gate is an AND gate.

18. The system according to any one of claims 12 and 13, wherein the memory component is a controller configured to serve the system via a non-volatile memory high-speed NVMe interface.

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