Graphics detection method, device and storage medium

Abstract

A pattern detection method, device, and storage medium are disclosed. The method calculates a critical dimension offset parameter value and a SPLC parameter value of a target physical wafer pattern unit to be detected based on measurement results of the target physical wafer pattern unit, obtains an SPLC threshold corresponding to the calculated critical dimension offset parameter value, and determines whether the target physical wafer pattern unit is a defective pattern based on the relationship between the calculated SPLC parameter value and the obtained SPLC threshold. Because the relationship between the calculated SPLC parameter value and the obtained SPLC threshold when the critical dimension offset parameter value is a constant can reflect whether the model error corresponding to the target physical wafer pattern unit meets the requirements, the method can accurately identify whether the target physical wafer pattern unit is a defective pattern, thereby improving the accuracy of defective pattern detection.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a pattern detection method, device and storage medium. Background Art

[0002] Photolithography is a crucial technology in semiconductor manufacturing, enabling the transfer of patterns from a mask onto the surface of a silicon wafer, creating semiconductor products that meet design requirements. The photolithography process begins with an exposure step, where light passes through the translucent or reflective areas of the mask onto a photoresist-coated silicon wafer, reacting photochemically with the photoresist. Next, a development step utilizes the solubility of the developer in the photosensitive and unsensitive photoresists to form a photoresist pattern, enabling the transfer of the mask pattern. Finally, an etching step involves etching the silicon wafer based on the photoresist pattern, further transferring the mask pattern to the wafer.

[0003] With the rapid development of integrated circuit design and the continuous reduction in the size of semiconductor devices, distortion occurs during the process of transferring patterns onto wafers. The pattern formed on the wafer will be deformed and deviate from the pattern on the mask. This distortion is mainly caused by the optical proximity effect (OPE).

[0004] To address the above issues, the optical proximity correction (OPC) method is usually used to correct errors in the photolithography process. The OPC method pre-processes the mask before photolithography and performs pre-correction so that the amount of correction compensation is just enough to compensate for the optical proximity effect caused by the exposure system. Therefore, using the mask made from the layout data after OPC, the expected target pattern can be obtained on the wafer after photolithography.

[0005] However, the optical proximity correction model used in the optical proximity correction process does not accurately predict the size of the target pattern at the corresponding position, resulting in defects in the physical wafer pattern units formed on the wafer actually produced. Summary of the Invention

[0006] The problem solved by the present invention is to provide a pattern detection method to improve the accuracy of pattern detection.

[0007] To solve the above problems, the present invention provides a pattern detection method, which includes:

[0008] Providing a target physical wafer pattern unit to be inspected;

[0009] Measuring the target physical wafer pattern unit to obtain a corresponding measurement result;

[0010] Calculating a critical dimension offset parameter value and an SPLC parameter value of the target physical wafer graphic unit based on a measurement result of the target physical wafer graphic unit;

[0011] Obtaining the SPLC threshold corresponding to the calculated critical size offset parameter value;

[0012] Determining whether the calculated SPLC parameter value and the obtained SPLC threshold value satisfy a preset relationship;

[0013] When it is determined that the calculated SPLC parameter value and the obtained SPLC threshold value satisfy the preset relationship, determining that the target physical wafer pattern unit is a non-defective pattern;

[0014] When it is determined that the calculated SPLC parameter value and the obtained SPLC threshold value do not satisfy the preset relationship, the target physical wafer pattern unit is determined to be a defective pattern.

[0015] Optionally, the acquired SPLC thresholds include a first SPLC threshold, a second SPLC threshold, a third SPLC threshold and a fourth SPLC threshold; wherein the first SPLC threshold is smaller than the second SPLC threshold, and the third SPLC threshold is smaller than the fourth SPLC threshold.

[0016] The preset relationship includes:

[0017] The calculated SPLC parameter value is greater than the first SPLC threshold and less than the second SPLC threshold; or,

[0018] The calculated SPLC parameter value is greater than the third SPLC threshold and less than the acquired fourth SPLC threshold.

[0019] Optionally, the target physical wafer graphic unit includes a plurality of discrete metal interconnects, which extend along a first direction and are arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction.

[0020] Optionally, in the target physical wafer graphic unit, the plurality of metal interconnects include a first metal interconnect and a second metal interconnect, and the second metal interconnect is located on both sides of the first metal interconnect along the second direction.

[0021] Optionally, the step of calculating the critical dimension offset parameter value and the SPLC parameter value of the target physical wafer graphic unit includes:

[0022] Obtaining measurements of critical dimensions, lengths, and spatial spacing of the target physical wafer pattern units;

[0023] Based on the obtained measurement values of the critical dimension, length and spatial spacing of the target physical wafer graphic unit, the critical dimension offset parameter value and SPLC parameter value of the target physical wafer graphic unit are calculated.

[0024] Optionally, the critical dimension offset parameter value and the SPLC parameter value of the target physical wafer pattern unit are calculated using the following formula:

[0025] CD Bias =CD1-CD2;

[0026] ∑∈S Area ;

[0027] and:

[0028] S Area =Length*CD1;

[0029] Among them, CD Bias represents the critical dimension offset parameter value of the target physical wafer graphic unit, CD1 represents the critical dimension of the second metal interconnect line in the target physical wafer graphic unit in the second direction, CD2 represents the critical dimension of the first metal interconnect line in the target physical wafer graphic unit in the second direction, SPLC represents the SPLC parameter value of the target physical wafer graphic unit, Pitch represents the spatial spacing between the first metal interconnect line and the second metal interconnect line in the target physical wafer graphic unit in the second direction, S Area represents the area of the second metal interconnection line in the target physical wafer graphic unit, and Length represents the size of the second metal interconnection line in the target physical wafer graphic unit in the first direction.

[0030] Optionally, the calculated SPLC threshold corresponding to the critical dimension offset parameter value is related to the semiconductor process technology.

[0031] Optionally, a critical dimension scanning electron microscope is used to measure the target physical wafer graphic unit.

[0032] Optionally, the target physical wafer graphic unit is obtained by the following steps: providing an original layout including a target graphic unit; performing optical proximity correction on the original layout to form a corresponding mask layout; the mask layout includes a target mask graphic unit corresponding to the target graphic unit; using the mask layout to form a physical wafer pattern on a physical wafer; the physical wafer pattern includes the target physical wafer graphic unit corresponding to the target mask graphic unit.

[0033] Optionally, the step of performing optical proximity correction on the original layout includes: providing an optical proximity correction model; correcting the original layout according to the optical proximity correction model to obtain an intermediate correction pattern of the original layout; obtaining an edge placement error between the intermediate correction pattern of the original layout and a target mask layout; when the edge placement error is greater than a preset threshold, correcting the intermediate correction pattern of the original layout according to the optical proximity correction model until the edge placement error is less than the threshold, thereby obtaining the mask layout.

[0034] Accordingly, an embodiment of the present invention also provides a device comprising at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the graphic detection method as described in any one of the above items.

[0035] Correspondingly, an embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement any of the above-mentioned graphic detection methods.

[0036] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0037] The solution in an embodiment of the present invention calculates the critical dimension offset parameter value and SPLC parameter value of the target physical wafer pattern unit to be detected based on the measurement results of the physical wafer properties, obtains the SPLC threshold value corresponding to the calculated critical dimension offset parameter value, and determines whether the target physical wafer pattern unit is a defective pattern based on the relationship between the calculated SPLC parameter value and the obtained SPLC threshold value. Because the relationship between the calculated SPLC parameter value and the obtained SPLC threshold value when the critical dimension offset parameter value is a fixed value can reflect whether the model error corresponding to the target physical wafer pattern unit meets the requirements, it can accurately identify whether the target physical wafer pattern unit is a defective pattern, thereby improving the accuracy of defect pattern detection and improving the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of a target graphic unit is shown;

[0039] Figure 2 A schematic diagram showing a flow chart of an embodiment of a pattern detection method according to an embodiment of the present invention is shown;

[0040] Figure 3 A schematic diagram showing an original layout in an embodiment of the present invention is shown;

[0041] Figure 4 A schematic diagram of a mask layout in an embodiment of the present invention is shown;

[0042] Figure 5 A schematic diagram of a target physical wafer pattern unit in an embodiment of the present invention is shown;

[0043] Figure 6 A schematic diagram of the framework structure of a device provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0044] As can be seen from the background technology, when using photolithography technology to form the expected target pattern on the wafer, the optical proximity correction model used for optical proximity correction of the original layout inaccurately predicts the size of the target graphic unit at the corresponding position, resulting in defects in the target physical wafer graphic unit formed on the actually produced wafer.

[0045] Figure 1 A schematic diagram of a target graphics unit is shown. Figure 1 The target pattern unit 10 includes a plurality of metal interconnect patterns (not labeled). The plurality of metal interconnect patterns extend along a first direction (not labeled) and are arranged in parallel along a second direction (not labeled), wherein the first direction is perpendicular to the second direction. Specifically, the plurality of metal interconnect patterns include a first metal interconnect pattern and a plurality of second metal interconnect patterns, wherein the second metal interconnect patterns are located on both sides of the first metal interconnect pattern along the second direction.

[0046] The target graphic unit 10 is a graphic in the original layout, and the graphic formed on the physical wafer is correspondingly a target physical wafer graphic unit.

[0047] Among them, the steps of forming a target physical wafer graphic unit on a wafer include: providing an original layout including a target graphic unit; using an optical proximity correction model to perform optical proximity correction on the original layout to form a corresponding mask layout; the mask layout includes a target mask graphic unit corresponding to the target graphic unit; using the mask layout to form a physical wafer pattern on a physical wafer; the physical wafer pattern includes the target physical wafer graphic unit corresponding to the target mask graphic unit.

[0048] There is no obvious regularity between the model error corresponding to the target physical wafer graphic unit and parameters such as the spatial pitch (Pitch), critical dimension (CD), length (Length) and critical dimension deviation (CDBias) of the target physical wafer graphic unit. Technicians can only judge whether the formed target physical wafer graphic has defects based on experience, resulting in low detection accuracy.

[0049] To solve the above problems, the present invention provides a pattern detection method, comprising: providing a physical wafer pattern; the physical wafer pattern includes a target physical wafer pattern unit to be detected; measuring the target physical wafer pattern unit to obtain a corresponding measurement result; calculating a critical dimension offset parameter value and an SPLC parameter value of the target physical wafer pattern unit based on the measurement result of the target physical wafer pattern unit; obtaining an SPLC threshold value corresponding to the calculated critical dimension offset parameter value; judging whether the calculated SPLC parameter value and the obtained SPLC threshold value satisfy a preset relationship; when it is determined that the calculated SPLC parameter value and the obtained SPLC threshold value satisfy the preset relationship, determining that the target physical wafer pattern unit is a non-defective pattern; when it is determined that the calculated SPLC parameter value and the obtained SPLC threshold value do not satisfy the preset relationship, determining that the target physical wafer pattern unit is a defective pattern.

[0050] In the graphic detection method provided by an embodiment of the present invention, the relationship between the calculated SPLC parameter value and the obtained SPLC threshold value can accurately reflect whether the model error corresponding to the target physical graphic unit to be detected meets the requirements, and then accurately identify whether the target physical wafer graphic unit is a defective graphic, thereby improving the accuracy of defective graphic detection and improving the performance of the formed semiconductor structure.

[0051] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0052] Figure 2 A flow chart of a pattern detection method according to an embodiment of the present invention is shown. Figure 2 In an embodiment of the present invention, a graphics detection method includes:

[0053] Step S201: providing a target physical wafer pattern unit to be inspected;

[0054] Step S202: measuring the target physical wafer pattern unit to obtain corresponding measurement results;

[0055] Step S203: Calculating a critical dimension offset parameter value and an SPLC parameter value of the target physical wafer pattern unit based on the measurement result of the target physical wafer pattern unit;

[0056] Step S204: obtaining the SPLC threshold corresponding to the calculated critical dimension offset parameter value;

[0057] Step S205: determining whether the calculated SPLC parameter value and the obtained SPLC threshold value satisfy a preset relationship;

[0058] When the calculated SPLC parameter value and the obtained SPLC threshold value satisfy the preset relationship, step S206 may be executed: determining that the target physical wafer pattern unit is a non-defective pattern;

[0059] When the calculated SPLC parameter value and the obtained SPLC threshold value do not satisfy the preset relationship, step S207 may be executed: determining that the target physical wafer pattern unit is a defective pattern.

[0060] The correction method of the optical proximity model in the embodiment of the present invention will be described in further detail below.

[0061] Please continue to see Figure 2 , execute step S201 to provide a target physical wafer graphic unit to be detected.

[0062] The target physical wafer pattern unit is a pattern on a wafer actually being produced.

[0063] In this embodiment, the step of obtaining the target physical wafer graphic unit includes: providing an original layout including a target graphic unit; performing optical proximity correction on the original layout using an optical proximity correction model to form a corresponding mask layout; the mask layout includes a target mask graphic unit corresponding to the target graphic unit; using the mask layout to form a physical wafer pattern on a physical wafer; the physical wafer pattern includes a target physical wafer graphic unit corresponding to the target mask graphic unit.

[0064] The step of forming a physical wafer pattern on a physical wafer using the mask pattern includes: forming a patterned mask layer using the mask pattern; etching a silicon wafer using the patterned mask layer as a mask to form the target physical wafer pattern unit.

[0065] See also Figure 3 The target graphic unit 30a includes a plurality of metal interconnection line patterns (not shown), which extend along a first direction (the X direction in the figure) and are arranged in parallel along a second direction (the Y direction in the figure), and the first direction is perpendicular to the second direction.

[0066] In this embodiment, the metal interconnection pattern is in a strip shape, and the metal interconnection pattern extends along a first direction and is arranged in parallel along a second direction.

[0067] Specifically, in the target pattern unit 30a, the plurality of metal interconnect patterns include a first metal interconnect pattern 311 and a plurality of second metal interconnect patterns 312, and the second metal interconnect patterns 312 are located on both sides of the first metal interconnect pattern 311 along the second direction.

[0068] As an example, in the target pattern unit 30a, the number of the first metal interconnection pattern 311 is one, and a second metal interconnection pattern 312 is provided on each side of the first metal interconnection pattern 311 along the second direction.

[0069] The target pattern unit 30a is formed in an original layout 100. The original layout 100 is a design pattern used to form a mask layout. The original layout 100 can be set according to different semiconductor process requirements.

[0070] The original layout 100 is stored in an original layout file. The original layout file refers to a layout file containing design graphics designed using an EDA tool. Typically, the original layout file is a layout file that has passed the Design Rule Check (DRC).

[0071] In this embodiment, the file format of the original layout is GDS format. In other embodiments, the file format of the original layout can also be other formats such as OASIS.

[0072] The optical proximity correction model is used to perform optical proximity correction on the original layout 100 to pre-process the mask before photolithography and perform pre-correction of the pattern so that the correction can just compensate for the optical proximity effect caused by the exposure system.

[0073] In this embodiment, the step of performing optical proximity correction on the original layout includes: providing an optical proximity correction model; correcting the original layout according to the optical proximity correction model to obtain an intermediate correction pattern of the original layout; obtaining an edge placement error between the intermediate correction pattern of the original layout and a target mask layout; when the edge placement error is greater than a preset threshold, correcting the intermediate correction pattern of the original layout according to the optical proximity correction model until the edge placement error is less than the threshold, thereby obtaining the mask layout.

[0074] In this embodiment, the optical proximity correction model is typically constructed by optimizing fitting coefficients in the model form.

[0075] The method for obtaining the optical proximity correction model includes: providing a test mask having a plurality of test patterns therein; exposing the test patterns to obtain actual exposure patterns; measuring the size of the actual exposure patterns to obtain first test data; performing simulated exposure on the test patterns to obtain test simulated exposure patterns; measuring the size of the test simulated exposure patterns to obtain second test data; and comparing and fitting the first test data with the second test data to obtain the optical proximity correction model.

[0076] As an example, the optical proximity correction model is a model-based optical proximity correction model. Model-based optical proximity correction utilizes a photolithography simulation model to simulate the spatial intensity (aerial) distribution within the photoresist or the two-dimensional profile of the photosensitive area, and infers a mask structure that can compensate for proximity effect deviation. Model-based optical proximity correction has high accuracy.

[0077] The mask pattern is a pattern subsequently formed in the mask.

[0078] See Figure 4 In the mask layout 200, a target mask pattern unit 30b is formed. The target mask pattern unit 30b is obtained by performing optical proximity correction on the target pattern unit in the original layout.

[0079] The target graphic unit in the original layout includes a first metal interconnection line and a second metal interconnection line located on both sides of the first metal interconnection line pattern along the second direction. Figure 5 The target physical wafer pattern unit 30c includes a first metal interconnection line 311' and a second metal interconnection line 312' located on both sides of the first metal interconnection line 311' along the second direction.

[0080] In this embodiment, the shape of the graphic in the target graphic unit in the original layout is a rectangle, and the shape of the graphic in the target physical wafer graphic unit 30c in the physical wafer graphic is correspondingly an ellipse.

[0081] Please continue to see Figure 2 , execute step S202, measure the target physical wafer graphic unit, and obtain corresponding measurement results.

[0082] In this embodiment, the target physical wafer pattern unit is measured to obtain information on the critical size, length and spatial spacing of the target physical wafer pattern unit.

[0083] In this embodiment, a critical dimension scanning electron microscope (CDSEM) is used to measure the critical dimensions, length, and spatial spacing of the target physical wafer pattern unit 30c.

[0084] Please continue to see Figure 5 In the target physical wafer pattern unit 30c, the second metal interconnection line 312' is along the first direction (eg Figure 5 The dimension (shown in the X direction) is the length of the second metal interconnection line 312', and the direction perpendicular to the first direction is the second direction (shown in the X direction). Figure 5 The first metal interconnection line 311' and the second metal interconnection line 312' are spaced apart in the second direction for a space pitch Pitch, the second metal interconnection line 312' has a size CD1 along the second direction, and the first metal interconnection line 311' has a size CD2 along the second direction.

[0085] A first measurement line GL1 is set, and the first measurement line GL1 extends along the second direction. The first measurement line GL1 intersects with two opposite sides of the first metal interconnection line 311' in the target physical wafer graphic unit 30c at two points along the second direction, which are measurement points a1 and a2 respectively. The first measurement line GL1 intersects with two opposite sides of the second metal interconnection line 312' along the second direction at two points, which are measurement points a3 and a4 respectively. Then, the length of the line segment with the measurement point a1 and the measurement point a2 as endpoints is correspondingly equal to the second critical dimension CD2 of the first metal interconnect 312' in the target physical wafer graphic unit 30c; the length of the line segment with the measurement point a3 and the measurement point a4 as endpoints is correspondingly equal to the critical dimension CD1 of the second metal interconnect 312' in the target physical wafer graphic unit 30c; the length of the line segment with the measurement point a1 and the measurement point a3 as endpoints is correspondingly equal to the spatial spacing Pitch between the first metal interconnect 311' and the second metal interconnect 312' in the target physical wafer graphic unit 30c.

[0086] A second measurement line GL2 is set. The second measurement line GL2 extends along the first direction and intersects two opposite sides of the second metal interconnect line 312' in the target physical wafer pattern unit 30c at two points along the first direction, namely measurement point a5 and measurement point a6. The length of the line segment with measurement points a5 and a6 as endpoints is equal to the length Length of the second metal interconnect line 312' in the target physical wafer pattern unit 30c.

[0087] The target physical wafer pattern unit 30c is measured to prepare for the subsequent calculation of the critical dimension offset parameter value and SPLC parameter value of the target physical wafer pattern unit 30c.

[0088] Continue to see Figure 2 , execute step S203, calculate the critical dimension offset parameter value and SPLC parameter value of the target physical wafer graphic unit based on the measurement result of the target physical wafer graphic unit.

[0089] The steps of calculating the critical dimension offset parameter value and SPLC parameter value of the target physical wafer graphic unit include: obtaining the critical dimension, length and spatial spacing in the target physical wafer graphic unit; and calculating the critical dimension offset parameter value and SPLC parameter value of the target physical wafer graphic unit based on the obtained critical dimension, length and spatial spacing in the target physical wafer graphic unit.

[0090] When the critical dimension and length of the second metal interconnection line of the target physical wafer graphic unit, the critical dimension of the first metal interconnection line and the dimension of the spatial spacing between the first metal interconnection line and the second metal interconnection line are obtained, the critical dimension offset parameter value and SPLC parameter value of the target physical wafer graphic unit can be calculated.

[0091] In this embodiment, the critical dimension offset parameter value and SPLC parameter value of the target physical wafer pattern unit are calculated using the following formula:

[0092] CD Bias =CD1-CD2 (1)

[0093]

[0094] and:

[0095] S Area =Length*CD1 (3)

[0096] Among them, CD Biasrepresents the critical dimension offset parameter value of the target physical wafer graphic unit, CD1 represents the critical dimension of the second metal interconnect line in the target physical wafer graphic unit in the second direction, CD2 represents the critical dimension of the first metal interconnect line in the target physical wafer graphic unit in the second direction, SPLC represents the SPLC parameter value of the target physical wafer graphic unit, Pitch represents the spatial spacing between the first metal interconnect line and the second metal interconnect line in the target physical wafer graphic unit in the second direction, S Area represents the area of the second metal interconnection line in the target physical wafer graphic unit, and Length represents the size of the second metal interconnection line in the target physical wafer graphic unit in the first direction.

[0097] Calculating the critical dimension offset parameter value and SPLC parameter value of the target physical wafer graphic unit 30c provides a basis for subsequently obtaining the corresponding SPLC threshold and determining whether the calculated SPLC parameter value satisfies the preset relationship with the corresponding SPLC threshold.

[0098] Continue to see Figure 2 , execute step S204 to obtain the SPLC threshold corresponding to the calculated key size offset parameter value.

[0099] An SPLC threshold corresponding to the calculated critical dimension offset parameter value is obtained to prepare for subsequently determining a relationship between the calculated SPLC parameter value and the obtained SPLC threshold.

[0100] In a specific implementation, the critical dimension offset parameter value CD Bias The corresponding SPLC threshold is related to the semiconductor process. In other words, when the semiconductor device is changed, the critical dimension offset parameter value CD Bias The corresponding SPLC threshold will also change accordingly.

[0101] Continue to see Figure 2 , executing step S205, determining whether the calculated SPLC parameter value and the obtained threshold value satisfy a preset relationship.

[0102] The inventors of the present application have discovered through research that when the critical dimension offset parameter value of the target physical wafer graphic unit 30c is constant, there is a correlation between the model error corresponding to the target physical wafer graphic unit 30c and the SPLC parameter value.

[0103] Specifically, when the critical dimension offset parameter value CD of the target physical wafer pattern unit BiasWhen the critical dimension CD1 of the second metal interconnection line is constant, the model error and the SPLC parameter value of the target physical wafer pattern unit are negatively correlated, that is, when the critical dimension offset parameter value CD Bias When is a constant value, the model error of the critical dimension CD1 of the second metal interconnect line decreases as the SPLC parameter value of the target physical wafer pattern unit increases.

[0104] On the contrary, when the critical dimension of the target physical wafer pattern unit is offset by the parameter value CD Bias When the critical dimension offset parameter value CD is constant, the model error of the spacing Space between the first metal interconnection line and the second metal interconnection line in the second direction is positively correlated with the SPLC parameter value of the target physical wafer pattern unit. In other words, when the critical dimension offset parameter value CD is constant, the model error of the spacing Space between the first metal interconnection line and the second metal interconnection line in the second direction is positively correlated with the SPLC parameter value of the target physical wafer pattern unit. Bias When is a constant value, the model error of the spacing Space between the first metal interconnection line and the second metal interconnection line in the second direction increases with the increase of the SPLC parameter value of the target physical wafer pattern unit.

[0105] Therefore, it is determined whether the calculated SPLC parameter value satisfies a preset relationship with the threshold corresponding to the critical dimension offset parameter value, so as to determine whether the model error of the first critical dimension CD1 of the second metal interconnect pattern and the spacing Space between the first metal interconnect and the second metal interconnect in the second direction meet the requirements, and further determine whether the target physical wafer pattern unit is a defective pattern.

[0106] In this embodiment, the calculated critical dimension offset parameter value CD of the target physical wafer graphic unit is Bias The corresponding SPLC thresholds include a first SPLC threshold, a second SPLC threshold, a third SPLC threshold, and a fourth SPLC threshold, wherein the first SPLC threshold is smaller than the second SPLC threshold, and the third SPLC threshold is smaller than the fourth SPLC threshold.

[0107] In a specific implementation, the critical dimension offset parameter value CD Bias The corresponding first SPLC threshold and the second SPLC threshold are used to determine whether the model error of the spacing space between the first metal interconnection line and the second metal interconnection line in the second direction meets the requirements; the critical dimension offset parameter value CD Bias The corresponding third SPLC threshold and fourth SPLC threshold are used to determine whether the model error of the critical dimension CD2 in the second direction of the second metal interconnection pattern meets the requirements.

[0108] In this embodiment, it is determined whether the calculated SPLC parameter value and the threshold corresponding to the calculated key size offset parameter value satisfy a preset relationship, that is, it is determined whether the calculated SPLC parameter value is greater than or equal to the first SPLC threshold corresponding to the calculated key size offset parameter value and less than or equal to the corresponding second SPLC threshold, or it is determined whether the calculated SPLC parameter value is greater than or equal to the third SPLC threshold corresponding to the calculated key size offset parameter value and less than or equal to the corresponding fourth SPLC threshold.

[0109] Please continue to see Figure 2 When the calculated SPLC parameter value satisfies a preset relationship with the threshold corresponding to the critical dimension offset parameter value, step S206 is executed to determine that the target physical wafer pattern unit is a non-defective pattern.

[0110] In this embodiment, when the calculated SPLC parameter value is greater than or equal to the first SPLC threshold corresponding to the calculated key size offset parameter value and is less than or equal to the corresponding second SPLC threshold, or whether the calculated SPLC parameter value is greater than or equal to the third SPLC threshold corresponding to the calculated key size offset parameter value and is less than or equal to the corresponding fourth SPLC threshold, then the calculated SPLC parameter value and the threshold corresponding to the key size offset parameter value satisfy the preset relationship.

[0111] When the calculated SPLC parameter value satisfies a preset relationship with the threshold corresponding to the critical dimension offset parameter value, it indicates that, in the target physical wafer pattern unit, the model error corresponding to the spacing Space between the first metal interconnect and the second metal interconnect in the second direction meets the corresponding semiconductor process requirements, or the model error of the critical dimension CD2 of the second metal interconnect in the second direction meets the corresponding semiconductor process requirements. In this case, the target physical wafer pattern unit can be determined to be a non-defective pattern.

[0112] Please continue to see Figure 2 When the calculated SPLC parameter value and the threshold value corresponding to the critical dimension offset parameter value do not satisfy the preset relationship, step S207 is executed to determine that the target physical wafer pattern unit is a defective pattern.

[0113] In this embodiment, when the calculated SPLC parameter value is less than the first SPLC threshold corresponding to the calculated key size offset parameter value or is greater than the corresponding second SPLC threshold, or the calculated SPLC parameter value is less than the third SPLC threshold corresponding to the calculated key size offset parameter value or is greater than the corresponding fourth SPLC threshold, the calculated SPLC parameter value and the threshold corresponding to the key size offset parameter value do not satisfy the preset relationship.

[0114] If the calculated SPLC parameter value and the threshold corresponding to the critical dimension offset parameter value do not satisfy the preset relationship, it indicates that in the target physical wafer pattern unit, the model error corresponding to the spacing Space between the first metal interconnect and the second metal interconnect in the second direction does not meet the corresponding semiconductor process requirements, and the model error of the critical dimension CD2 of the second metal interconnect in the second direction does not meet the corresponding semiconductor process requirements. In this case, the target physical wafer pattern unit can be determined to be a defective pattern.

[0115] The embodiment of the present invention further provides a device that can execute the above-mentioned pattern detection method in the form of a loaded program. The pattern detection method is described in the above section and will not be described in detail.

[0116] An optional hardware structure of the terminal device provided by the embodiment of the present invention can be as follows Figure 6 As shown, it includes: at least one processor 01, at least one communication interface 02, at least one memory 03 and at least one communication bus 04.

[0117] In the embodiment of the present invention, the number of the processor 01 , the communication interface 02 , the memory 03 , and the communication bus 04 is at least one, and the processor 01 , the communication interface 02 , and the memory 03 communicate with each other via the communication bus 04 .

[0118] The communication interface 02 may be an interface of a communication module for network communication, such as an interface of a GSM module.

[0119] The processor 01 may be a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0120] The memory 03 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0121] The memory 03 stores one or more computer instructions, and the one or more computer instructions are executed by the processor 01 to implement the graphic detection method according to the embodiment of the present invention.

[0122] It should be noted that the above-mentioned terminal device may also include other devices (not shown) that may not be necessary for understanding the contents disclosed in the embodiments of the present invention; given that these other devices may not be necessary for understanding the contents disclosed in the embodiments of the present invention, the embodiments of the present invention will not introduce them one by one.

[0123] An embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the graphic detection method provided by the embodiment of the present invention.

[0124] The embodiments of the present invention described above are combinations of elements and features of the present invention. Unless otherwise mentioned, the elements or features may be considered as optional. Each element or feature may be put into practice without being combined with other elements or features. In addition, the embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some configurations of any one embodiment may be included in another embodiment and may be replaced by the corresponding configuration of another embodiment. It is obvious to those skilled in the art that claims that do not have a clear reference relationship to each other in the appended claims may be combined into embodiments of the present invention, or may be included as new claims in amendments after submitting this application.

[0125] The embodiments of the present invention may be implemented by various means such as hardware, firmware, software, or a combination thereof. In a hardware configuration, the method according to the exemplary embodiment of the present invention may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.

[0126] In a firmware or software configuration, embodiments of the present invention may be implemented in the form of modules, procedures, functions, and the like. Software code may be stored in the first metal interconnect of a memory cell to implement or utilize the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0127] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A pattern detection method, characterized in that: include: Provides a target physical wafer pattern unit for detection; Measuring the target physical wafer graphic unit to obtain measurement values of the critical size, length, and spatial spacing of the target physical wafer graphic unit; Calculating a critical dimension offset parameter value and an SPLC parameter value of the target physical wafer graphic unit based on the measured values of the critical dimension, length, and spatial spacing of the target physical wafer graphic unit; Obtaining the SPLC threshold corresponding to the calculated critical size offset parameter value; Determining whether a relationship between the calculated SPLC parameter value and the obtained SPLC threshold value satisfies a requirement that a model error corresponding to the target physical wafer pattern unit meets requirements; When it is determined that the relationship between the calculated SPLC parameter value and the obtained SPLC threshold value satisfies the requirement that the model error corresponding to the target physical wafer pattern unit meets the requirement, determining that the target physical wafer pattern unit is a non-defective pattern; When it is determined that the relationship between the calculated SPLC parameter value and the obtained SPLC threshold value does not satisfy the requirement that the model error corresponding to the target physical wafer pattern unit meets the requirement, the target physical wafer pattern unit is determined to be a defective pattern.

2. The pattern detection method according to claim 1, wherein: The obtained SPLC thresholds include a first SPLC threshold, a second SPLC threshold, a third SPLC threshold, and a fourth SPLC threshold; wherein the first SPLC threshold and the second SPLC threshold are used to determine whether the model error of the spacing of the target physical wafer graphic unit in the second direction meets the requirements, and the first SPLC threshold is less than the second SPLC threshold, and the third SPLC threshold and the fourth SPLC threshold are used to determine whether the model error of the critical dimension of the target physical wafer graphic unit in the second direction meets the requirements, and the third SPLC threshold is less than the fourth SPLC threshold; The relationship between the calculated SPLC parameter value and the obtained SPLC threshold value satisfies the requirement that the model error corresponding to the target physical wafer pattern unit meets the requirement, including: The calculated SPLC parameter value is greater than or equal to the first SPLC threshold and less than or equal to the second SPLC threshold; or, The calculated SPLC parameter value is greater than or equal to the third SPLC threshold and less than or equal to the obtained fourth SPLC threshold.

3. The pattern detection method according to claim 1, wherein: The target physical wafer graphic unit includes a plurality of discrete metal interconnection lines extending along a first direction and arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction.

4. The pattern detection method according to claim 3, wherein: In the target physical wafer pattern unit, the plurality of discrete metal interconnects include a first metal interconnect and a second metal interconnect, and the second metal interconnect is located on both sides of the first metal interconnect along the second direction.

5. The pattern detection method according to claim 4, wherein: The critical dimension offset parameter value and SPLC parameter value of the target physical wafer pattern unit are calculated using the following formula: CD Bias =CD1-CD2; and: S Area =Length*CD1; Among them, CD Bias represents the critical dimension offset parameter value of the target physical wafer graphic unit, CD1 represents the critical dimension of the second metal interconnect line in the target physical wafer graphic unit in the second direction, CD2 represents the critical dimension of the first metal interconnect line in the target physical wafer graphic unit in the second direction, SPLC represents the SPLC parameter value of the target physical wafer graphic unit, Pitch represents the spatial spacing between the first metal interconnect line and the second metal interconnect line in the target physical wafer graphic unit in the second direction, S Area represents the area of the second metal interconnection line in the target physical wafer graphic unit, and Length represents the size of the second metal interconnection line in the target physical wafer graphic unit in the first direction.

6. The pattern detection method according to claim 1, wherein: The corresponding SPLC threshold is related to the semiconductor process technology.

7. The pattern detection method according to claim 1, wherein: The target physical wafer graphic unit is measured using a critical dimension scanning electron microscope.

8. The pattern detection method according to claim 1, wherein: The target physical wafer graphic unit is obtained by the following steps: providing an original layout including a target graphic unit; performing optical proximity correction on the original layout to form a corresponding mask layout; the mask layout includes a target mask graphic unit corresponding to the target graphic unit; using the mask layout to form a physical wafer pattern on a physical wafer; the physical wafer pattern includes the target physical wafer graphic unit corresponding to the target mask graphic unit.

9. The pattern detection method according to claim 8, wherein: The step of performing optical proximity correction on the original layout includes: providing an optical proximity correction model; correcting the original layout according to the optical proximity correction model to obtain an intermediate correction pattern of the original layout; obtaining an edge placement error between the intermediate correction pattern of the original layout and a target mask layout; when the edge placement error is greater than a preset threshold, correcting the intermediate correction pattern of the original layout according to the optical proximity correction model until the edge placement error is less than the threshold, thereby obtaining the mask layout.

10. A terminal device, characterized in that: The system comprises at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the graphic detection method according to any one of claims 1 to 9.

11. A storage medium, characterized in that: The storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the graphic detection method according to any one of claims 1 to 9.

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