Apparatus, method, and related products for fast wake-up of a brain-computer interface system

Abstract

The application discloses a device, method and related product for quickly waking up a brain-computer interface system. The device comprises a frequency division circuit configured to divide an initial wake-up interrupt clock signal based on a preset frequency division coefficient to generate a high-speed wake-up interrupt clock signal in response to a wake-up interrupt signal of the processor being valid; and a wake-up clock configured to output a high-speed wake-up clock signal based on the high-speed wake-up interrupt clock signal and a switching request signal of the clock switching circuit in response to the switching request signal, so as to make the processor quickly respond to a wake-up interrupt and realize quick wake-up of the brain-computer interface system. The scheme can realize quick wake-up of the brain-computer interface system.

Description

TECHNICAL FIELD

[0001] The present application generally relates to the technical field of brain-computer interface. More particularly, the present application relates to an apparatus for fast wake-up of a brain-computer interface system and a brain-computer interface system. Further, the present application also relates to a method, a device and a computer readable storage medium for fast wake-up of a brain-computer interface system. BACKGROUND

[0002] Brain-computer interface is a direct connection path between human or animal brain (or culture of brain cells) and external devices. Since the mid-1990s, such knowledge obtained from experiments has grown significantly. On the basis of years of animal experiments, early implant devices applied to human body are designed and manufactured, such as for restoring damaged hearing, vision and limb movement ability. The main line of such research is the unusual cortical plasticity of the brain, which is adapted to brain-computer interface, and can control the implanted prosthesis like natural limbs. Under the current progress of technology and knowledge, the pioneers of brain-computer interface research can convincingly attempt to manufacture brain-computer interfaces that enhance human function, not just restore human function.

[0003] Brain-computer interface chip is a system-level chip designed to integrate most of the components required by brain-computer interface to effectively reduce the volume, power consumption and other factors of brain-computer interface system. In application scenarios, according to system application requirements, its working mode is mainly divided into full speed (working frequency above MHz), low speed (working frequency from several thousand to several hundred thousand Hz) and sleep mode, etc. Among them, due to the need for continuous monitoring of brain electrical signals, the low-speed mode occupies more than 80% of the brain-computer interface working time. During system operation, according to task load requirements, there are switching requirements between various modes, especially from low-speed or sleep mode to high-speed mode. However, due to the need for low-speed interrupt response, processor wake-up interrupt processing, low-speed mode to high-speed mode switching and other processes during the aforementioned work under low-speed clock, it takes a long time for the wake-up system. Therefore, how to quickly wake up the brain-computer interface system becomes a technical problem to be solved. SUMMARY

[0004] In order to at least partially solve the technical problems mentioned in the background, the present application provides a scheme for fast wake-up of a brain-computer interface system. By using the scheme of the present application, the time for the processor to respond to the wake-up interrupt can be reduced to achieve fast wake-up of the brain-computer interface system. To this end, the present application provides solutions in the following aspects.

[0005] In a first aspect, the present application provides an apparatus for fast wake-up of a brain-computer interface system, wherein the brain-computer interface system comprises at least a processor and a clock switching circuit, and the apparatus comprises: a frequency dividing circuit configured to divide an initial wake-up interrupt clock signal by a preset frequency dividing coefficient to generate a high-speed wake-up interrupt clock signal in response to a wake-up interrupt signal of the processor being valid; and a wake-up clock configured to output a high-speed wake-up clock signal based on the high-speed wake-up interrupt clock signal and a switching request signal of the clock switching circuit, so as to make the processor fast respond to a wake-up interrupt, and realize fast wake-up of the brain-computer interface system.

[0006] In one embodiment, the wake-up clock comprises one or more flip-flops configured to synchronize the switching request signal and the high-speed wake-up interrupt clock signal, so as to switch to the wake-up clock.

[0007] In another embodiment, the wake-up clock further comprises a latch to latch the high-speed wake-up interrupt clock signal.

[0008] In yet another embodiment, in outputting the high-speed wake-up clock signal based on the high-speed wake-up interrupt clock signal and the switching request signal, the wake-up clock is further configured to: perform an AND operation based on the high-speed wake-up interrupt clock signal and the switching request signal; and output the high-speed wake-up clock signal according to an AND operation result.

[0009] In a second aspect, the present application also provides a brain-computer interface system comprising: a processor; a clock switching circuit; and the apparatus according to the foregoing embodiments.

[0010] In one embodiment, the brain-computer interface system further comprises: a high-speed clock configured to output a high-speed clock signal based on a high-speed signal and a switching request signal of the clock switching circuit, so as to make the processor perform a high-speed task.

[0011] In another embodiment, the brain-computer interface system further comprises: a low-speed clock configured to output a low-speed clock signal based on a low-speed signal and a switching request signal of the clock switching circuit, so as to make the processor perform a low-speed task.

[0012] In yet another embodiment, the high-speed clock and the low-speed clock respectively comprise one or more flip-flops each configured to synchronize the switching request signal and the high-speed signal and synchronize the switching request signal and the low-speed signal, so as to switch to the high-speed clock or the low-speed clock.

[0013] In yet another embodiment, the high-speed clock and the low-speed clock each include a respective latch to latch the high-speed signal and the low-speed signal, respectively.

[0014] In a third aspect, the present application also provides a method for quickly waking up a brain-computer interface system, wherein the brain-computer interface system at least includes a processor and a clock switching circuit, and the method comprises: using a frequency division circuit to divide, in response to a wake-up interrupt signal of the processor being active, an initial wake-up interrupt clock signal based on a preset frequency division coefficient to generate a high-speed wake-up interrupt clock signal; and using a wake-up clock to output, in response to a switching request signal of the clock switching circuit, a high-speed wake-up clock signal based on the high-speed wake-up interrupt clock signal and the switching request signal, so as to make the processor quickly respond to a wake-up interrupt, thereby achieving quick wake-up of the brain-computer interface system.

[0015] In a fourth aspect, the present application also provides a device for quickly waking up a brain-computer interface system, comprising: a processor; and a memory storing program instructions for quickly waking up the brain-computer interface system, which, when executed by the processor, cause the device to implement the embodiments in the foregoing third aspect.

[0016] In a fifth aspect, the present application also provides a computer-readable storage medium having stored thereon computer-readable instructions for quickly waking up a brain-computer interface system, which, when executed by one or more processors, implement the embodiments in the foregoing third aspect.

[0017] Through the scheme of the present application, the high-speed wake-up interrupt clock signal is generated by dividing (or speeding up) the initial wake-up interrupt clock signal through the frequency division circuit, and the high-speed wake-up clock signal is output by the wake-up clock in response to the switching request signal of the clock switching circuit, thereby achieving quick switching to the wake-up clock. Based on this, the processor can quickly respond to the wake-up interrupt to quickly start the high-speed clock, thereby achieving quick wake-up of the brain-computer interface system. Further, the flip-flops are arranged in each clock in the embodiments of the present application, so that the signals between the clock circuits can be synchronized to ensure the stability of the system. In addition, the latches are arranged in each clock circuit in the embodiments of the present application to latch the signal information, thereby ensuring the output of high-quality signals. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and other objects, features and advantages of the exemplary embodiments of the present application will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is an exemplary schematic diagram illustrating a conventional brain-computer interface system;

[0020] Figure 2 is an exemplary schematic diagram illustrating a conventional wake-up of a brain-computer interface system;

[0021] Figure 3 is an exemplary structural block diagram of an apparatus for fast wake-up of a brain-computer interface system according to an embodiment of the present application;

[0022] Figure 4 is an exemplary schematic diagram of an apparatus for fast wake-up of a brain-computer interface system according to an embodiment of the present application;

[0023] Figure 5 is an exemplary structural block diagram of a brain-computer interface system according to an embodiment of the present application;

[0024] Figure 6 is an exemplary schematic diagram of a brain-computer interface system according to an embodiment of the present application;

[0025] Figure 7 is an exemplary flow block diagram of a method for fast wake-up of a brain-computer interface system according to an embodiment of the present application; and

[0026] Figure 8 is an exemplary structural block diagram of an apparatus for fast wake-up of a brain-computer interface system according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings. It should be understood that the embodiments described in the specification are only part of the embodiments of the present application provided for the purpose of clearly understanding the solutions and meeting the legal requirements, and not all the embodiments of the present application can be implemented. Based on the embodiments disclosed in the specification, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0028] Figure 1 is an exemplary schematic diagram illustrating a conventional brain-computer interface system 100. As shown in FIG. 1, the conventional brain-computer interface system 100 includes a brain-computer interface system 100 and a user 101. Figure 1As shown, the conventional brain-computer interface system 100 may include a processor 101, a clock switching circuit 102, a low-speed clock 103, and a high-speed clock 104. The processor 101 includes at least an interrupt response program 105 and an interrupt service routine 106. As described in the background art above, the operating modes of the brain-computer interface system 100 are mainly divided into full-speed or high-speed (operating frequency above MHz), low-speed (operating frequency between several thousand and several hundred thousand Hz), and sleep mode. The low-speed mode occupies more than 80% of the operating time of the brain-computer interface system 100, which can extend the system's operating time, reduce the power consumption of the brain-computer interface system 100, and ensure that the entire processor 101 is in a low-speed, or even sleep, state for the vast majority of its operating states.

[0029] Specifically, in application scenarios, to achieve a balance between power consumption and performance, the brain-computer interface system 100 makes sampling, stimulation, and other functions high-speed tasks. During these tasks, the system clock (or high-speed clock) operates at a high speed, with a frequency of, for example, 16MHz. During tasks such as waiting for data, the system clock operates in a sleep state, with a frequency of, for example, 32kHz. In this case, the processor 101 is inactive, and most modules of the brain-computer interface system 100 operate at a low-speed clock, or some modules are even powered off, thus causing the brain-computer interface system 100 to operate in a sleep state most of the time. When the next task requires a high-speed state, the brain-computer interface system 100 needs to switch from a low-speed state or sleep mode to a high-speed state. That is, the brain-computer interface system 100 typically has multiple mode switching requirements, such as switching from sleep mode or low-speed mode to high-speed mode, or vice versa.

[0030] Specifically, switching from sleep mode or low-speed mode to high-speed mode requires switching via the interrupt mode of the processor 101 of the brain-computer interface system 100. However, switching between low-speed and high-speed modes requires processes such as low-speed interrupt response, processor wake-up interrupt handling, and switching from low-speed mode to high-speed mode, for example... Figure 2 As shown.

[0031] Figure 2 This is an exemplary schematic diagram illustrating conventional methods of waking up a brain-computer interface system. For example... Figure 2As shown, when high-speed task 201 is completed and there is no new high-speed task to perform, the brain-computer interface system switches from high-speed task 201 to low-speed task 202. That is, the brain-computer interface system switches from high-speed mode to low-speed mode and enters, for example, sleep mode, low-speed state, standby state, or shutdown state. When high-speed task 201 needs to be executed, the brain-computer interface system switches from low-speed task 202 to high-speed task 201. That is, the brain-computer interface system switches from low-speed mode to high-speed mode. When switching to low-speed mode, a wake-up interrupt signal 203 is first generated, which is in a low-speed state. Then, it waits to see if the wake-up interrupt signal is valid. When the wake-up interrupt signal is valid, the interrupt response program in the processor responds to wake-up 204, and after responding to wake-up, the processor wakes up the interrupt service routine 205. Further, the processor controls the clock switching circuit to switch to high-speed mode, thereby running high-speed task 202.

[0032] However, because the brain-computer interface system operates at a low clock speed (e.g., 32kHz) in sleep mode, the process from generating the wake-up interrupt signal, responding to the wake-up interrupt, to processing the wake-up interrupt (e.g., the process indicated by arrow A in the diagram) requires comparing multiple cycles of the low-speed clock. This results in a significant delay when switching from sleep mode or low-speed mode to high-speed mode.

[0033] In view of this, this application provides a device for rapidly waking up a brain-computer interface system, which can reduce the time required to switch from sleep mode or low-speed mode to high-speed mode without affecting system power consumption or area. Through the embodiments of this application, the switching speed of the processor from low-power state to high-speed state can be effectively improved, reducing the latency from the millisecond level to the microsecond or nanosecond level.

[0034] Figure 3 This is an exemplary structural block diagram illustrating a device 300 for rapidly waking up a brain-computer interface system according to an embodiment of this application. Figure 3As shown, the device 300 may include a frequency divider circuit 301 and a wake-up clock 302. In one embodiment, the frequency divider circuit 301 may be configured to divide the initial wake-up interrupt clock signal based on a preset frequency division coefficient in response to a wake-up interrupt signal from the processor, thereby generating a high-speed wake-up interrupt clock signal. As described above, when the brain-computer interface system needs to switch from a low-speed mode or sleep mode to a high-speed mode, a wake-up interrupt signal is generated, and this wake-up interrupt signal operates in a low-speed state. In this embodiment, when the aforementioned wake-up interrupt signal is generated, the initial wake-up interrupt clock signal can be divided (or speeded up) by the frequency divider circuit 301 to generate a high-speed wake-up interrupt clock signal, so that the wake-up interrupt clock signal is in a high-speed state. The frequency division coefficient of the frequency divider circuit 301 may be preset, and after frequency division, it can operate at, for example, 8-16MHz.

[0035] In another embodiment, the wake-up clock 302 can be configured to respond to a switching request signal from the clock switching circuit, outputting a high-speed wake-up clock signal based on the high-speed wake-up interrupt clock signal and the switching request signal, so that the processor can quickly respond to the wake-up interrupt and achieve rapid wake-up of the brain-computer interface system. It can be understood that in the implementation scenario, when the brain-computer interface system needs to switch from a low-speed mode to a high-speed mode, the processor, in addition to handling the wake-up interrupt, can also control the clock switching circuit to achieve the switch from low-speed mode to high-speed mode. In this scenario, the clock switching circuit will send switching request signals to each clock, and then output corresponding clock signals through the switching request signals and each clock signal to achieve mode switching.

[0036] For example, regarding the wake-up clock, when the clock switching circuit issues a switching request signal, it outputs a high-speed wake-up clock signal based on the high-speed wake-up interrupt clock signal and the switching request signal. In implementation scenarios, an AND operation can be performed based on the high-speed wake-up interrupt clock signal and the switching request signal to output the high-speed wake-up clock signal based on the AND operation result. Since this high-speed wake-up clock signal is valid, the clock switching circuit can switch the brain-computer interface system from low-speed mode to wake-up mode, allowing the processor to quickly respond to the wake-up interrupt. As an example, when the AND result of the high-speed wake-up interrupt clock signal and the switching request signal is 1, it indicates that the high-speed wake-up clock signal is valid. This high-speed wake-up clock signal can serve as a start flag for the high-speed clock, thereby enabling rapid wake-up of the brain-computer interface system.

[0037] In one embodiment, the wake-up clock may include one or more triggers configured to synchronize a switching request signal and a high-speed wake-up interrupt clock signal to switch to the wake-up clock. In the implementation scenario, the switching request signal serves as the rising edge input of the trigger, and the high-speed wake-up interrupt clock signal serves as the falling edge input. Based on this, the stability of the brain-computer interface system can be guaranteed, ensuring that the system is only in one switching mode.

[0038] In one embodiment, the wake-up clock may further include a latch to latch the high-speed wake-up interrupt clock signal. For example, the high-speed wake-up interrupt clock signal entering the last trigger may be latched to prevent "glitch" in the sampled signal from affecting the signal quality.

[0039] As described above, this embodiment incorporates the wake-up interrupt signal into the signal frequency division and switching. The wake-up interrupt clock signal is frequency-divided (speeded up) by a frequency division circuit, and a high-speed wake-up clock signal is output in response to the switching request signal from the clock switching circuit. This allows the clock switching circuit to quickly switch to the wake-up clock, and subsequently to the high-speed clock (or system clock). Based on this, the processor's interrupt processing time is significantly shortened, thereby enabling rapid wake-up of the brain-computer interface system. Furthermore, this embodiment also uses triggers to synchronize the switching request signal and the high-speed wake-up interrupt clock signal to ensure system stability, and uses latches to latch the signals to ensure high-quality output signals.

[0040] Figure 4 This is an exemplary schematic diagram illustrating a device for rapidly waking up a brain-computer interface system according to an embodiment of this application. It should be understood that... Figure 4 The device in the above is Figure 3 One specific embodiment of the device 300, therefore the above regarding Figure 3 The description also applies to Figure 4 .

[0041] like Figure 4As shown, the device may include a frequency divider circuit 301 and a wake-up clock 302. The frequency divider circuit 301 can be connected to the processor and the wake-up clock 302, and the wake-up clock 302 can be connected to a clock switching circuit. Further, the aforementioned wake-up clock 302 may include one or more flip-flops 401 and latches 402; for example, three flip-flops 401 are shown in the figure. As previously mentioned, when the brain-computer interface system needs to switch from a low-speed mode or sleep mode to a high-speed mode, a wake-up interrupt signal 403 is generated. In response to this wake-up interrupt signal 403, the initial wake-up interrupt clock signal is divided by the frequency divider circuit 301 to obtain a high-speed wake-up interrupt clock signal 404, and this high-speed wake-up interrupt clock signal 404 enters the wake-up clock 302. Then, the clock switching circuit sends a switching request signal 405 to each clock.

[0042] As an example, Figure 4 Only the clock switching circuit sending a switching request signal 405 to the wake-up clock 302 is shown. Then, the aforementioned high-speed wake-up interrupt clock signal 404 and the switching request signal 405 are synchronized via flip-flop 401 to ensure system stability. Simultaneously, the aforementioned high-speed wake-up interrupt clock signal 404 is latched via latch 402 when it enters the last flip-flop 401 to ensure the quality of the output signal. Specifically, after performing a logical AND operation on the high-speed wake-up interrupt clock signal 404 and the switching request signal 405, a high-speed wake-up clock signal 406 can be output. In an exemplary scenario, assuming that the high-speed wake-up clock signal 406 is valid, the clock switching circuit can quickly switch to the wake-up clock, and then quickly switch to the high-speed clock (system clock).

[0043] In one embodiment, this application also provides a brain-computer interface system, which includes a processor, a clock switching circuit, and the apparatus described in the embodiments of this application. Further, the aforementioned brain-computer interface system may also include a high-speed clock and a low-speed clock. The following will be combined with... Figure 5 The aforementioned brain-computer interface system is described in detail.

[0044] Figure 5 This is an exemplary structural block diagram illustrating a brain-computer interface system 500 according to an embodiment of this application. Figure 5As shown, the brain-computer interface system 500 may include a processor 501, a clock switching circuit 502, a low-speed clock 503, a high-speed clock 504, and the device 300 of this embodiment. The device 300 may include a frequency divider circuit 301 and a wake-up clock 302. In one embodiment, the high-speed clock 504 may be configured to output a high-speed clock signal based on a high-speed signal and a switching request signal in response to a switching request signal from the clock switching circuit, so that the processor can perform a high-speed task. The low-speed clock 503 may be configured to output a low-speed clock signal based on a low-speed signal and a switching request signal in response to a switching request signal from the clock switching circuit, so that the processor can perform a low-speed task. As described above, the frequency divider circuit 301 may be configured to divide the initial wake-up interrupt clock signal based on a preset frequency division coefficient in response to the processor's wake-up interrupt signal being active, thereby generating a high-speed wake-up interrupt clock signal. The aforementioned wake-up clock 302 can be configured to respond to the switching request signal of the clock switching circuit, and output a high-speed wake-up clock signal based on the high-speed wake-up interrupt clock signal and the switching request signal, so that the processor can quickly respond to the wake-up interrupt and realize the rapid wake-up of the brain-computer interface system.

[0045] In the implementation scenario, when the processor 501 finishes processing a high-speed task, the brain-computer interface system will switch from high-speed mode to low-speed mode. In this scenario, the clock switching circuit 502 responds to the switching request from the processor 501 by sending switching request signals to the low-speed clock 503, the high-speed clock 504, and the wake-up clock 302, and performs an AND operation with each clock signal to obtain the output signals of each clock. For example, the switching request signal can be ANDed with the low-speed signal of the low-speed clock 503, the high-speed signal of the high-speed clock 504, or the high-speed wake-up interrupt clock signal of the wake-up clock 302, respectively, to obtain the corresponding low-speed clock signal, high-speed clock signal, and wake-up clock signal. The final output signal is the result of a logical OR operation of the aforementioned three signals, meaning that any one of the aforementioned low-speed clock signal, high-speed clock signal, or wake-up clock signal is valid. When the output low-speed clock signal is valid, the processor controls the high-speed clock 504 and the wake-up clock 302 to turn off, turns on the low-speed clock 503 and transmits the low-speed clock signal to the clock switching circuit 502, thereby controlling the brain-computer interface system to switch from high-speed mode to low-speed mode.

[0046] When the processor 501 needs to handle high-speed tasks, the brain-computer interface system will switch from low-speed mode to high-speed mode. In this scenario, the initial wake-up interrupt clock signal is divided by the frequency divider circuit 301 to obtain a high-speed wake-up interrupt clock signal, which is then fed into the wake-up clock 302. Simultaneously, the clock switching circuit 502 responds to the processor 501's switching request by sending switching request signals to the low-speed clock 503, the high-speed clock 504, and the wake-up clock 302, and ANDing these signals with the respective clock signals to obtain the output signals of each clock. When the output wake-up clock signal is valid, the processor controls the high-speed clock 504 and the low-speed clock 503 to turn off, turns on the wake-up clock 302, and transmits the wake-up clock signal to the clock switching circuit 502, thereby controlling the brain-computer interface system to quickly wake up from high-speed mode. Further, when the processor's wake-up interrupt service routine is active, the high-speed clock signal is valid, and the processor controls the wake-up clock 302 and the low-speed clock 503 to turn off, turns on the high-speed clock 504, and transmits the high-speed clock signal to the clock switching circuit 502, thereby controlling the brain-computer interface system to switch from low-speed mode to high-speed mode.

[0047] In some embodiments, the high-speed clock and the low-speed clock may each include one or more flip-flops, each flip-flop configured to synchronize the switching request signal and the high-speed signal, and the switching request signal and the low-speed signal, respectively, to switch to the high-speed clock or the low-speed clock. Similar to the wake-up clock described above, the flip-flops of the high-speed clock and the low-speed clock each use the high-speed signal and the low-speed signal as the falling edge input, and the switching request signal as the rising edge input, respectively. Furthermore, the high-speed clock and the low-speed clock may each include their own latches to latch the high-speed signal and the low-speed signal respectively, for example... Figure 6 As shown.

[0048] Figure 6 This is an exemplary schematic diagram illustrating a brain-computer interface system according to an embodiment of this application. It should be understood that... Figure 6 The device in the above is Figure 5 A specific embodiment of the brain-computer interface system 500, therefore the above regarding Figure 5 The description also applies to Figure 6 .

[0049] like Figure 6As shown, the brain-computer interface system may include a processor 501, a clock switching circuit 502, a low-speed clock 503, a high-speed clock 504, a frequency divider circuit 301, and a wake-up clock 302. The processor 501 is connected to the clock switching circuit 502 and the frequency divider circuit 301. The clock switching circuit 502 is connected to the low-speed clock 503, the high-speed clock 504, the frequency divider circuit 301, and the wake-up clock 302, respectively, and the frequency divider circuit 301 is connected to the wake-up clock 302. In one embodiment, the low-speed clock 503, the high-speed clock 504, and the wake-up clock 302 are each equipped with a corresponding trigger 601, trigger 602, and trigger 401, respectively, to synchronize the switching request signal 405 with each signal. In some embodiments, the low-speed clock 503, the high-speed clock 504, and the wake-up clock 302 are also equipped with corresponding latches 603, latch 604, and latch 402, respectively, to latch each signal.

[0050] As previously mentioned, when the processor 501 finishes processing a high-speed task, the brain-computer interface system will switch from high-speed mode to low-speed mode. In this scenario, the switching request signal 405 sent by the clock switching circuit 502 is ANDed with the low-speed signal 605 to obtain a low-speed clock signal 606, and this low-speed clock signal 606 is valid. Therefore, the processor controls the high-speed clock 504 and the wake-up clock 302 to turn off, turns on the low-speed clock 503, and transmits the low-speed clock signal 606 to the clock switching circuit 502, thereby controlling the brain-computer interface system to switch from high-speed mode to low-speed mode.

[0051] When the processor 501 needs to process high-speed tasks, the brain-computer interface system will switch from low-speed mode to high-speed mode. In this scenario, a wake-up interrupt signal 403 is generated. In response to this wake-up interrupt signal 403, the initial wake-up interrupt clock signal is divided by the frequency divider circuit 301 to obtain a high-speed wake-up interrupt clock signal 404, which is then fed into the wake-up clock 302. Simultaneously, the switching request signal 405 sent by the clock switching circuit 502 is ANDed with the high-speed wake-up interrupt clock signal 404 to obtain a high-speed wake-up clock signal 406. This high-speed wake-up clock signal 406 is valid. Therefore, the processor controls the high-speed clock 504 and the low-speed clock 503 to turn off, turns on the wake-up clock 302, and transmits the high-speed wake-up clock signal 406 to the clock switching circuit 502, thereby controlling the brain-computer interface system to quickly wake up from high-speed mode. Furthermore, the processor wakes up the interrupt service routine, and the switching request signal 405 sent by the clock switching circuit 502 is ANDed with the high-speed signal 607 to obtain the high-speed clock signal 608. The high-speed clock signal 608 is valid, and the processor controls the wake-up clock 302 and the low-speed clock 503 to turn off, turns on the high-speed clock 504, and transmits the high-speed clock signal 608 to the clock switching circuit 502, thereby controlling the brain-computer interface system to switch from low-speed mode to high-speed mode.

[0052] Figure 7 This is an exemplary flowchart illustrating a method 700 for rapidly waking up a brain-computer interface system according to an embodiment of this application. Figure 7 As shown, in step 702, a frequency divider circuit is used in response to the processor's wake-up interrupt signal being active. Based on a preset frequency division coefficient, the initial wake-up interrupt clock signal is divided to generate a high-speed wake-up interrupt clock signal. That is, the initial wake-up interrupt clock signal is accelerated through the frequency divider circuit. Next, in step 704, the wake-up clock is used in response to the clock switching circuit's switching request signal. Based on the high-speed wake-up interrupt clock signal and the switching request signal, a high-speed wake-up clock signal is output to enable the processor to quickly respond to the wake-up interrupt, thus achieving rapid wake-up of the brain-computer interface system. For more details on rapid wake-up of the brain-computer interface system, please refer to the above. Figures 3-6 The content described herein will not be repeated here.

[0053] Figure 8 This is an exemplary structural block diagram illustrating a device 800 for rapidly waking up a brain-computer interface system according to an embodiment of this application. It will be understood that the device implementing the solution of this application can be a single device (e.g., a computing device) or a multifunctional device including various peripheral devices.

[0054] like Figure 8 As shown, the device of this application may include a central processing unit (“CPU”) 811, which may be a general-purpose CPU, a special-purpose CPU, or other information processing and program execution unit. Furthermore, the device 800 may also include a mass storage device 812 and a read-only memory (“ROM”) 813, wherein the mass storage device 812 may be configured to store various types of data, including various programs required for fast wake-up, algorithm data, intermediate results, and operation of the device 800. The ROM 813 may be configured to store data and instructions required for the device 800's power-on self-test, initialization of various functional modules in the system, drivers for the system's basic input / output, and booting the operating system.

[0055] Optionally, device 800 may also include other hardware platforms or components, such as the tensor processing unit (“TPU”) 814, graphics processing unit (“GPU”) 815, field-programmable gate array (“FPGA”) 816, and machine learning unit (“MLU”) 817 shown. It is understood that although various hardware platforms or components are shown in device 800, they are merely exemplary and not limiting, and those skilled in the art can add or remove appropriate hardware as needed. For example, device 800 may include only a CPU, associated storage devices, and interface devices to implement the method for rapidly waking up a brain-computer interface system as described in this application.

[0056] In some embodiments, to facilitate data transmission and interaction with external networks, the device 800 of this application further includes a communication interface 818, through which it can connect to a local area network / wireless local area network (“LAN / WLAN”) 805, and further through the LAN / WLAN to connect to a local server 806 or to the Internet (“Internet”) 807. Alternatively or additionally, the device 800 of this application can also directly connect to the Internet or cellular network via the communication interface 818 based on wireless communication technology, such as wireless communication technology based on 3G (“3G”), 4G (“4G”), or 5G (“5G”). In some application scenarios, the device 800 of this application can also access the server 808 and database 809 of an external network as needed to obtain various known algorithms, data, and modules, and can remotely store various data or instructions.

[0057] The above combination Figure 8 This application describes a device for rapidly waking up a brain-computer interface system, which can be used to execute this application. It should be understood that the device structure or architecture described herein is merely exemplary, and the implementation methods and entities of this application are not limited thereto, but can be modified without departing from the spirit of this application.

[0058] Based on the foregoing description in conjunction with the accompanying drawings, those skilled in the art will understand that the embodiments of this application can also be implemented by a software program. Therefore, this application also provides a computer program product. This computer program product can be used to implement the embodiments of this application in conjunction with the accompanying drawings. Figure 7 The method described is for the rapid awakening of a brain-computer interface system.

[0059] It should be noted that although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. On the contrary, the steps depicted in the flowchart can be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0060] It should be understood that when the terms "first," "second," "third," and "fourth," etc., are used in the claims, specification, and drawings of this application, they are used only to distinguish different objects and not to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this application indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0061] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0062] Although the embodiments of this application are described above, the content is merely an example adopted for the purpose of facilitating understanding of this application and is not intended to limit the scope and application scenarios of this application. Any person skilled in the art described in this application may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application, but the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A device for rapidly waking up a brain-computer interface system, wherein the brain-computer interface system includes at least a processor and a clock switching circuit, the brain-computer interface system mode switching includes switching from a sleep mode or a low-speed mode to a high-speed mode, and the device comprises: The frequency divider circuit is configured to respond to the processor's wake-up interrupt signal being valid by dividing the initial wake-up interrupt clock signal based on a preset frequency division coefficient to generate a high-speed wake-up interrupt clock signal, wherein the initial wake-up interrupt signal is in a low-speed mode. as well as The wake-up clock is configured to respond to the switching request signal of the clock switching circuit, synchronize and latch the high-speed wake-up interrupt clock signal and the switching request signal, and perform an AND operation based on the processed high-speed wake-up interrupt clock signal and the switching request signal to output a high-speed wake-up clock signal, so that the processor can quickly respond to the wake-up interrupt and realize the rapid wake-up of the brain-computer interface system.

2. The apparatus of claim 1, wherein the wake-up clock comprises one or more triggers configured to synchronize the switching request signal and the high-speed wake-up interrupt clock signal in order to switch to the wake-up clock.

3. The apparatus according to claim 2, wherein the wake-up clock further includes a latch for latching the high-speed wake-up interrupt clock signal.

4. The apparatus of claim 3, wherein in outputting the high-speed wake-up clock signal based on the high-speed wake-up interrupt clock signal and the switching request signal, the wake-up clock is further configured to: Execution and operation are performed based on the high-speed wake-up interrupt clock signal and the switching request signal; and Output a high-speed wake-up clock signal based on the operation results.

5. A brain-computer interface system, comprising: processor; Clock switching circuit; as well as The apparatus according to any one of claims 1-4.

6. The brain-computer interface system according to claim 5, further comprising: A high-speed clock, configured to respond to a switching request signal from the clock switching circuit, outputs a high-speed clock signal based on the high-speed signal and the switching request signal, so that the processor can perform high-speed tasks.

7. The brain-computer interface system according to claim 6, further comprising: A low-speed clock, configured to respond to a switching request signal from the clock switching circuit, outputs a low-speed clock signal based on the low-speed signal and the switching request signal, so that the processor performs a low-speed task.

8. The brain-computer interface system according to claim 6 or 7, wherein the high-speed clock and the low-speed clock each include one or more triggers, and each trigger is configured to synchronize the switching request signal and the high-speed signal and to synchronize the switching request signal and the low-speed signal, so as to switch to the high-speed clock or the low-speed clock.

9. The brain-computer interface system according to claim 6 or 7, wherein the high-speed clock and the low-speed clock each include a respective latch to latch the high-speed signal and the low-speed signal respectively.

10. A method for rapidly waking up a brain-computer interface system, wherein the brain-computer interface system includes at least a processor and a clock switching circuit, the brain-computer interface system mode switching includes switching from a sleep mode or a low-speed mode to a high-speed mode, and the method includes: A frequency divider circuit is used to respond to the wake-up interrupt signal of the processor. The initial wake-up interrupt clock signal is divided based on a preset frequency division coefficient to generate a high-speed wake-up interrupt clock signal, wherein the initial wake-up interrupt signal is in a low-speed mode. as well as The wake-up clock is used in response to the switching request signal of the clock switching circuit. Synchronization and latching are performed based on the high-speed wake-up interrupt clock signal and the switching request signal. The high-speed wake-up clock signal is output by performing an AND operation based on the processed high-speed wake-up interrupt clock signal and the switching request signal, so that the processor can quickly respond to the wake-up interrupt and realize the rapid wake-up of the brain-computer interface system.

11. A device for rapidly waking up a brain-computer interface system, comprising: processor; as well as A memory storing program instructions for rapidly waking up a brain-computer interface system, which, when executed by the processor, cause the device to implement the method according to claim 10.

12. A computer-readable storage medium storing computer-readable instructions for rapidly waking up a brain-computer interface system, wherein the computer-readable instructions, when executed by one or more processors, implement the method of claim 10.

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