Method and apparatus for implementing integer register file in multi-instruction set processor

Abstract

This invention discloses a method and apparatus for implementing an integer register file in a multi-instruction set processor. The method includes: dividing a 64-bit wide integer register file into two 32-bit bodies; adding an extension field to the integer register renaming mapping table to indicate whether the higher 32 bits of data originate from an extension of the lower 32 bits of data and how the extension is performed; identifying the access granularity of the integer register type operands during instruction decoding; reading or updating the extension field of the register renaming mapping table during the register renaming stage based on the operand type, access granularity, and the current architecture type of the multi-instruction set processor; and controlling read and write access to the integer register file during the instruction execution stage based on the access granularity and the value of the extension field. This invention aims to avoid unnecessary read and write operations on the higher 32 bits of the integer register file when accessing integer registers with 32-bit granularity, thereby reducing the power consumption of integer register file access and simplifying hardware control.

Description

Technical Field

[0001] This invention relates to processor design technology, and more specifically to a method and apparatus for implementing integer register files in a multi-instruction set processor. Background Technology

[0002] In a 64-bit processor architecture, a 64-bit integer register can typically store both 32-bit and 64-bit integers. When storing a 32-bit integer, these 32 bits are usually stored in the lower 32 bits of the 64-bit integer register. The higher 32 bits are either zero-extended or sign-extended according to the architecture specification. For example, the Armv8 architecture specifies that when 32-bit data is stored in a 64-bit integer register, the higher 32 bits are zero-extended, meaning the higher 32 bits are all 0s. The RISC-V architecture, on the other hand, specifies that when 32-bit data is stored in a 64-bit integer register, the higher 32 bits are sign-extended, meaning the higher 32 bits are the sign bit of the 32-bit data to be stored, which may be all 0s or all 1s.

[0003] To reduce power consumption when accessing integer register files, processors typically implement 64-bit integer register files as two bodies, each 32 bits wide. When accessing integer registers at a 32-bit granularity, power consumption can be reduced by controlling the reading and writing of the higher 32 bits of the register body. For example, the patent document "A Low-Power Access Method and Apparatus for Register Files (201810715133.5)" adds a data status register with one bit to each item in the register body to indicate whether the data of that item is 0, and adds read 0 and write 0 control to the access port: when reading an integer register with 32-bit granularity, the read 0 control logic controls not to read the higher 32 bits of the register body, reducing read operations; when writing an integer register with 32-bit granularity, the write 0 control logic determines whether the data of the corresponding item in the higher 32 bits of the register body is already 0 according to the data status register. If it is, then it does not write to the higher 32 bits of the register body, reducing write operations; when reading an integer register with 64-bit granularity, if the data status register indicates that the data of the corresponding item in the higher 32 bits of the register body is 0, then it is not necessary to read the higher 32 bits of the register body, reducing read operations; when writing with 64-bit granularity, it is necessary to write to both register bodies simultaneously. This method works well in processors with zero extension of the high 32 bits. However, if the high 32 bits are sign-extended, the method needs improvement, making the design more complex. Furthermore, the sign extension can be either 0 or 1. If 0 and 1 always alternate, the high 32 bits of the register body must always be written, diminishing the power reduction effect of register access. For multi-instruction set processors, achieving low-power register file access using this method becomes even more difficult. For example, patent document "Program execution method, computer device and system supporting multi-instruction set architecture (202114156439)" proposes supporting multiple instruction set architectures, including Armv8 and RISC-V, simultaneously in user space. When accessing integer registers with 32-bit granularity, the high 32 bits sometimes need zero extension and sometimes sign extension, complicating low-power control of the register file. Summary of the Invention

[0004] Through analysis, the applicant discovered that when writing to an integer register with 32-bit granularity, subsequent reads of the same register, if also at 32-bit granularity, do not require reading the higher 32 bits. Similarly, with 64-bit granularity reads, the higher 32 bits can be obtained from the current processor execution state and the lower 32 bits of the register, also eliminating the need to read them. Therefore, writing to an integer register with 32-bit granularity completely eliminates the need to write the higher 32 bits. Based on this analysis, the technical problem this invention aims to solve is to provide a method and apparatus for implementing an integer register file in a multi-instruction set processor. This invention aims to avoid unnecessary reads and writes to the higher 32 bits of the integer register file when accessing integer registers with 32-bit granularity, thereby reducing the power consumption of integer register file access and simplifying hardware control.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] An implementation method for an integer register file in a multi-instruction set processor includes:

[0007] S1, divide the 64-bit wide integer register file into two bodies, each 32 bits wide; add an extension field to the integer register renaming mapping table to indicate whether the high 32 bits of data come from the extension of the low 32 bits of data and how to perform the extension;

[0008] S2 identifies the access granularity of integer register type operands during instruction decoding;

[0009] S3, during the register renaming phase, reads or updates the extended fields of the register renaming map table based on operand type, access granularity, and the current architecture type of the multi-instruction set processor;

[0010] S4, during the instruction execution phase, controls read and write access to the integer register file based on the access granularity and the value of the extended field.

[0011] Optionally, when dividing the 64-bit wide integer register file into two bodies in step S1, the two bodies include body bank0 and body bank1, where body bank0 is used to store the lower 32 bits of 32-bit granular data or 64-bit granular data, and body bank1 is used to store the upper 32 bits of extended data of 32-bit granular data or the upper 32 bits of 64-bit granular integers.

[0012] Optionally, the extended field in step S1 has a length of two digits, and its value definition includes:

[0013] 2'b00: The high 32 bits of data are not an extension of the low 32 bits of data;

[0014] 2'b01: The high 32 bits of data are an extension from the low 32 bits of data, and the extension is zero;

[0015] 2'b11: The high 32 bits of data are an extension of the low 32 bits of data, and are a sign bit extension.

[0016] Optionally, in step S2, when the access granularity of an integer register type operand is identified during instruction decoding, each integer register type operand is decoded to output one bit of access granularity information to indicate that the access granularity is 32-bit or 64-bit.

[0017] Optionally, the access granularity information is represented by 0 for 32-bit granularity and 1 for 64-bit granularity.

[0018] Optionally, in step S3, when reading or updating the extended field of the register renaming map table according to the operand type, access granularity, and the current architecture type of the multi-instruction set processor during the register renaming stage, if the operand being renamed is a source operand, the value of the extended field is obtained by reading the register renaming map table using the register number for use by the execution stage. At the same time, the access granularity of the source operand is also passed to the execution stage along with the value of the extended field read. The value of the extended field read by the source operand is marked as src_high32_ext[1:0]. If there are multiple source operands, the values ​​of the extended fields read by different source operands are distinguished by their numbers. If the operand being renamed is a destination operand, the value of the extended field dst_high32_ext[1:0] is generated according to the current architecture type of the multi-instruction set processor and the access granularity of the destination operand. The value dst_high32_ext[1:0] is updated to the corresponding entry in the register renaming map table and is also passed to the execution stage.

[0019] Optionally, the value of the generated extended field dst_high32_ext[1:0] includes: if the access granularity of the destination operand is 64 bits, then the value of dst_high32_ext[1:0] is 2'b00; if the access granularity of the destination operand is 32 bits, and the current architecture of multi-instruction set processors specifies zero extension of the high 32 bits, then the value of dst_high32_ext[1:0] is 2'b01; if the access granularity of the destination operand is 32 bits, and the current architecture of multi-instruction set processors specifies sign bit extension of the high 32 bits, then the value of dst_high32_ext[1:0] is 2'b11.

[0020] Optionally, in step S4, during the instruction execution phase, when controlling the read and write access of the integer register file based on the access granularity and the value of the extended field, for the source operand, if the access granularity is 32 bits, then it is not necessary to read the body bank1 of the integer register file; if the access granularity is 64 bits and the value of src_high32_ext[1:0] is 2'b01, then it is not necessary to read the body bank1 of the integer register file, and the high 32 bits of the 64-bit data to be used are assigned all 0s; if the access granularity is 64 bits and the value of src_high32_ext[1:0] is 2'b11, then it is not necessary to read the body bank1 of the integer register file, and the high 32 bits of the 64-bit data to be used are assigned the sign bit extension of the value read from the body bank0 of the integer register file, i.e., all 0s or all 1s; if the access granularity is 64 bits and the value of sr If the value of c_high32_ext[1:0] is 2'b00, then the body bank1 of the register file needs to be read; regardless of the access granularity and the value of src_high32_ext[1:0], the body bank0 of the integer register file needs to be read; for the destination operand, its access granularity is already encoded in the value dst_high32_ext[1:0]. If the value of dst_high32_ext[1:0] is 2'b01 or 2'b11, then the body bank1 of the integer register file does not need to be written; if the value of dst_high32_ext[1:0] is 2'b00, then the body bank1 of the integer register file needs to be written; regardless of the value of dst_high32_ext[1:0], the body bank0 of the integer register file needs to be written.

[0021] Furthermore, the present invention also provides an apparatus for implementing an integer register file in a multi-instruction set processor, comprising a microprocessor and a memory interconnected thereto, wherein the microprocessor is programmed or configured to execute the steps of the method for implementing the integer register file in the multi-instruction set processor.

[0022] Furthermore, the present invention also provides a computer-readable storage medium storing a computer program for being programmed or configured by a microprocessor to execute steps of an implementation method of an integer register file in the multi-instruction set processor.

[0023] Compared with the prior art, the present invention has the following main advantages:

[0024] 1. This invention reduces read and write access to integer register files, thereby reducing the power consumption of integer register file access. This invention divides the 64-bit integer register file into two bodies, each 32 bits wide. When reading or writing an integer register at a 32-bit granularity, it is not necessary to read or write the high 32 bits of the integer register file. Similarly, when reading the integer register file at a 64-bit granularity, if the most recent write to the register was at a 32-bit granularity, then it is also not necessary to read the high 32 bits of the integer register file. Therefore, this method reduces read and write access to integer register files, thereby reducing the power consumption of integer register file access.

[0025] 2. The hardware control of this invention is simple. This invention is designed for low-power register file management in multi-instruction set processors. However, the implementation complexity depends only on the type of extension method for the high 32 bits when accessing integer registers at 32-bit granularity, and is independent of the number of architecture types supported by the multi-instruction set processor. Current mainstream architectures are either zero-extension or sign-bit extension, so implementing a two-bit extension field in the integer register renaming mapping table is sufficient, simplifying hardware control. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the basic process of the method in an embodiment of the present invention. Detailed Implementation

[0027] like Figure 1 As shown, this embodiment provides a method for implementing an integer register file in a multi-instruction set processor, including:

[0028] S1, divide the 64-bit wide integer register file into two bodies, each body being 32 bits wide; add an extension field (denoted as high32_ext field in this embodiment) to the integer register renaming mapping table to indicate whether the high 32 bits of data come from the extension of the low 32 bits of data and how to perform the extension.

[0029] S2 identifies the access granularity of integer register type operands during instruction decoding;

[0030] S3, during the register renaming phase, reads or updates the high32_ext field of the register renaming map table based on operand type, access granularity, and the current architecture type of the multi-instruction set processor;

[0031] S4, during the instruction execution phase, controls the read and write access of the integer register file based on the access granularity and the value of the high32_ext field.

[0032] In this embodiment, when the 64-bit wide integer register file is divided into two bodies in step S1, the two bodies include body bank0 and body bank1. Body bank0 is used to store the lower 32 bits of 32-bit granular data or 64-bit granular data, and body bank1 is used to store the upper 32 bits of extended data of 32-bit granular data or the upper 32 bits of 64-bit granular integer.

[0033] In this embodiment, the high32_ext field in step S1 has a length of two digits, and its value definition includes:

[0034] 2'b00: The high 32 bits of data are not an extension of the low 32 bits of data;

[0035] 2'b01: The high 32 bits of data are an extension from the low 32 bits of data, and the extension is zero;

[0036] 2'b11: The high 32 bits of data are an extension of the low 32 bits of data, and are a sign bit extension.

[0037] In addition, as an optional implementation, the value definition of the high32_ext field in this embodiment also includes 2'b10, which indicates that it is reserved for future use and is not currently used.

[0038] Because instructions with mixed granularity may exist, such as the SMULL instruction in the Armv8 architecture which reads two 32-bit data points and writes them to the register integers with 64-bit granularity after calculation, each integer register type operand needs to be decoded to obtain one bit of access granularity information. In this embodiment, in step S2, when the access granularity of the integer register type operand is identified during instruction decoding, each integer register type operand is decoded to obtain one bit of access granularity information to indicate whether the access granularity is 32-bit or 64-bit. Specifically, one bit of access granularity information is represented by 0 for 32-bit granularity and 1 for 64-bit granularity.

[0039] In this embodiment, during step S3, when reading or updating the high32_ext field of the register renaming map table based on the operand type, access granularity, and the current architecture type of the multi-instruction set processor, if the operand being renamed is a source operand, the register number is used to read the register renaming map table to obtain the value of the high32_ext field for use by the execution stage. At the same time, the access granularity of the source operand is also passed to the execution stage along with the read high32_ext value, and the high32_ext field value read by the source operand is marked as src_high32_ext[1:0]. If there are multiple source operands, the values ​​of the high32_ext field read by different source operands are distinguished by their numbers. If the operand being renamed is a destination operand, the value dst_high32_ext[1:0] of the high32_ext field is generated based on the current architecture type of the multi-instruction set processor and the access granularity of the destination operand. The value dst_high32_ext[1:0] is updated to the corresponding entry in the register renaming map table and is also passed to the execution stage.

[0040] In this embodiment, generating the value dst_high32_ext[1:0] of the high32_ext field includes: if the access granularity of the destination operand is 64 bits, then the value of dst_high32_ext[1:0] is 2'b00; if the access granularity of the destination operand is 32 bits, and the current architecture of multi-instruction set processors specifies zero extension of the high 32 bits, then the value of dst_high32_ext[1:0] is 2'b01; if the access granularity of the destination operand is 32 bits, and the current architecture of multi-instruction set processors specifies sign extension of the high 32 bits, then the value of dst_high32_ext[1:0] is 2'b11. Furthermore, if there are other processing methods, they can be represented using reserved values ​​of the high32_ext field or by expanding the number of bits in the field, which will not be detailed here.

[0041] In this embodiment, during the instruction execution phase in step S4, when controlling the read and write access of the integer register file based on the access granularity and the value of the high32_ext field, for the source operand, if the access granularity is 32 bits, then it is not necessary to read the body bank1 of the integer register file; if the access granularity is 64 bits and the value of src_high32_ext[1:0] is 2'b01, then it is not necessary to read the body bank1 of the integer register file, and the high 32 bits of the 64-bit data to be used are assigned all 0s ... high 32_ext[1:0] is 2'b01, then it is not necessary to read the body bank1 of the integer register file, and the high 32 bits of the 64-bit data to be used are assigned all 0s; if the access granularity is 64 bits and the high 32_ext[1:0] is 2'b01, then If the value of xt[1:0] is 2'b11, then there is no need to read bank1 of the integer register file. The high 32 bits of the 64-bit data to be used are assigned the sign bit extension of the value read from bank0 of the integer register file, i.e., all 0s or all 1s. If the access granularity is 64 bits and the value of src_high32_ext[1:0] is 2'b00, then the bank1 of the register file needs to be read. Regardless of the access granularity and the value of src_high32_ext[1:0], the bank0 of the integer register file needs to be read. For the destination operand, its access granularity is already encoded in the value dst_high32_ext[1:0]. If the value of dst_high32_ext[1:0] is 2'b01 or 2'b11, then it is not necessary to write the body bank1 of the integer register file; if the value of dst_high32_ext[1:0] is 2'b00, then it is necessary to write the body bank1 of the integer register file; regardless of the value of dst_high32_ext[1:0], it is necessary to write the body bank0 of the integer register file.

[0042] In summary, the implementation method of the integer register file in the multi-instruction set processor of this embodiment divides the 64-bit integer register file into two bodies, each 32 bits wide. When reading or writing an integer register at a 32-bit granularity, it is not necessary to read or write the high 32 bits of the integer register file. Similarly, when reading the integer register file at a 64-bit granularity, if the most recent write to the register was at a 32-bit granularity, then it is also not necessary to read the high 32 bits of the integer register file. Therefore, this method can reduce read and write accesses to the integer register file, thereby reducing the power consumption of integer register file access. The implementation method of the integer register file in the multi-instruction set processor of this embodiment is designed for low-power register file design in multi-instruction set processors. However, the implementation complexity depends only on the type of high 32-bit extension method when accessing integer registers at a 32-bit granularity, and is independent of the number of architecture types supported by the multi-instruction set processor. The current mainstream architectures are either zero-extension or sign-bit extension, so only two bits of high32_ext need to be implemented in the integer register renaming mapping table, which is simple in hardware control.

[0043] Furthermore, this embodiment also provides an implementation apparatus for an integer register file in a multi-instruction set processor, including a microprocessor and a memory interconnected thereto, wherein the microprocessor is programmed or configured to execute the steps of the aforementioned implementation method for an integer register file in a multi-instruction set processor.

[0044] Furthermore, this embodiment also provides a computer-readable storage medium storing a computer program that is programmed or configured by a microprocessor to execute the steps of the aforementioned implementation method of the integer register file in a multi-instruction set processor.

[0045] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0046] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principle of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method of implementing an integer register file in a multiple instruction set processor, the method comprising: The method comprises the following steps: S1, dividing a 64-bit integer register file into two banks, each bank having a width of 32 bits; adding an extension field in an integer register renaming mapping table, the extension field indicating whether high 32-bit data is extended from low 32-bit data and how the extension is performed; S2, identifying access granularity of an integer register type operand during instruction decoding; S3, reading or updating the extension field of the register renaming mapping table according to the operand type, the access granularity and the current architecture type of the multi-instruction set processor during the register renaming stage; S4, controlling read and write access of the integer register file according to the access granularity and the value of the extension field during the instruction execution stage.

2. The method of claim 1, wherein the method further comprises: In step S1, when the 64-bit integer register file is divided into two banks, the two banks include bank0 and bank1, wherein bank0 is used to store 32-bit granularity data or low 32-bit of 64-bit granularity data, and bank1 is used to store high 32-bit extension data of 32-bit granularity data or high 32-bit of 64-bit granularity integer.

3. The method of claim 2, wherein the method further comprises: In step S1, the length of the extension field is two bits, and the value definition includes: 2'b00: the high 32-bit data is not extended from the low 32-bit data; 2'b01: the high 32-bit data is extended from the low 32-bit data, and is zero extension; 2'b11: the high 32-bit data is extended from the low 32-bit data, and is sign bit extension.

4. The method of claim 3, wherein the method further comprises: In step S2, when the access granularity of the integer register type operand is identified during instruction decoding, one bit of access granularity information is decoded for each integer register type operand to indicate that the access granularity is 32-bit granularity or 64-bit granularity.

5. The method of claim 4, wherein: The one bit of access granularity information indicates 32-bit granularity with 0 and 64-bit granularity with 1.

6. The method of claim 3, wherein the method further comprises: In step S3, when the extension field of the register renaming mapping table is read or updated according to the operand type, the access granularity and the current architecture type of the multi-instruction set processor during the register renaming stage, if the register renaming operand is a source operand, the register number is used to read the register renaming mapping table to obtain the value of the extension field for the execution stage, and the access granularity of the source operand is also transmitted to the execution stage together with the read value of the extension field, and the value of the extension field read by the source operand is marked as src_high32_ext[1:0], and if there are multiple source operands, the values of the extension fields read by different source operands are distinguished by numbers; if the register renaming operand is a destination operand, the value dst_high32_ext[1:0] of the extension field is generated according to the current architecture type of the multi-instruction set processor and the access granularity of the destination operand, the value dst_high32_ext[1:0] is updated to the corresponding item in the register renaming mapping table, and is also transmitted to the execution stage.

7. The method of claim 6, wherein the method further comprises: The value of the extension field, dst_high32_ext[1:0], is generated as follows: if the access granularity of the destination operand is 64 bits, then the value of dst_high32_ext[1:0] is 2'b00; if the access granularity of the destination operand is 32 bits and the current architecture of the multi-instruction set processor specifies zero extension for the high 32 bits, then the value of dst_high32_ext[1:0] is 2'b01; if the access granularity of the destination operand is 32 bits and the current architecture of the multi-instruction set processor specifies sign extension for the high 32 bits, then the value of dst_high32_ext[1:0] is 2'b11.

8. The method of claim 7, wherein: In the instruction execution stage of step S4, when controlling the read and write access to the integer register file according to the access granularity and the value of the extension field, for the source operand, if the access granularity is 32 bits, then the body bank1 of the integer register file does not need to be read; if the access granularity is 64 bits and the value of src_high32_ext[1:0] is 2'b01, then the body bank1 of the integer register file does not need to be read, and the high 32 bits of the 64-bit data to be used are assigned as all 0; if the access granularity is 64 bits and the value of src_high32_ext[1:0] is 2'b11, then the body bank1 of the integer register file does not need to be read, and the high 32 bits of the 64-bit data to be used are assigned as the sign extension of the value read from the body bank0 of the integer register file, i.e. all 0 or all 1; if the access granularity is 64 bits and the value of src_high32_ext[1:0] is 2'b00, then the body bank1 of the integer register file needs to be read; the body bank0 of the integer register file needs to be read regardless of the access granularity and the value of src_high32_ext[1:0]; for the destination operand, the access granularity is already encoded in the value of dst_high32_ext[1:0], and if the value of dst_high32_ext[1:0] is 2'b01 or 2'b11, then the body bank1 of the integer register file does not need to be written; if the value of dst_high32_ext[1:0] is 2'b00, then the body bank1 of the integer register file needs to be written; the body bank0 of the integer register file needs to be written regardless of the value of dst_high32_ext[1:0].

9. An implementation apparatus for an integer register file in a multiple instruction set processor, comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor is programmed or configured to perform the steps of the implementation method of the integer register file in the multi-instruction set processor according to any one of claims 1-8.

10. A computer-readable storage medium having stored therein a computer program, characterized in that, The computer program is used for programming or configuring the microprocessor to perform the steps of the implementation method of the integer register file in the multi-instruction set processor according to any one of claims 1-8.

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