High-speed unmanned aerial vehicle remote control framing method and device

Abstract

The application discloses a high-speed unmanned plane remote control framing method and device, which is applied to the field of unmanned plane control system in ground control station, and realizes the collection, storage and remote control frame grouping of multiple control instructions. The high-speed unmanned plane has high timeliness requirement for instructions. The method adopts an encoder board card containing a field programmable gate array (FPGA) and a digital signal processor (DSP), the DSP allocates 3 register arrays to each control data, and selectively sends the data in the array according to the storage state of each array, so as to ensure that the latest control instruction is sent to the unmanned plane. The application can send the unmanned plane control instruction in time at any time, and the time delay is not more than a remote control frame cycle. The application has simple hardware resources, high reliability and low cost.

Description

Technical Field

[0001] This invention relates to the field of UAV control systems within UAV ground control stations, enabling the reception, judgment, storage, and assembly of UAV flight, payload, and link control commands, as well as the transmission of remote control frame data to the UAV via a wireless link, thereby completing the control of the UAV. Background Technology

[0002] The drone is controlled by a ground control station, whose drone control system is the "brain" of the entire drone system. The drone operator, much like a pilot in the cockpit, performs the drone's flight and mission operations from the ground control station.

[0003] The ground control station is equipped with multiple control positions, including flight control, mission control, and link control positions. Each position generates different control commands, which are collected and stored by the encoder and assembled into remote control frames. These frames are then transmitted to the UAV via a wireless link. The control positions within the station communicate quasi-synchronously with the encoder. Because high-speed UAVs have high requirements for the timeliness of commands, if the encoder uses a traditional FIFO buffering method, the timeliness of the commands will be affected when the time difference between the two ends slips into a certain period, and the delay will exceed one remote control frame cycle. Summary of the Invention

[0004] The technical problem this invention aims to solve is that, in situations where high-speed UAV commands have high timeliness requirements, a register array is used to cache data. Based on the cache state of each array, data within the array is selectively sent to ensure that the latest control commands are delivered to the UAV. The delay does not exceed one remote control frame cycle.

[0005] The technical solution adopted in this invention is as follows:

[0006] A high-speed unmanned aerial vehicle (UAV) remote control framing method includes the following steps:

[0007] The encoder interface circuit receives data from various channels, performs level conversion, and then sends the asynchronous serial data to the FPGA chip. The FPGA chip processes multiple serial data channels in parallel and performs serial data format conversion.

[0008] The DSP reads data from the FPGA chip via the bus. Each data channel is allocated three register arrays, and each register array is set with a corresponding status word. The status word is used to identify the current status of the stored data. The status includes: sending, waiting to send, and receiving data.

[0009] After the DSP reads data through the bus, it first checks the data frame header. If the frame header is valid, it stores the data in the register array whose status is "receive data" according to the current status word of each register array. When a frame is full, the corresponding status word is changed to "waiting to send". If another register array is already in the "waiting to send" state, the status word of the other "waiting to send" register array is set to "receive data".

[0010] After the FPGA chip generates a remote control frame interrupt signal through frequency division, the DSP responds to the interrupt signal, reads the status words of each register array, points the pointer to the array waiting to be sent, changes the status of the array to "sending", and assembles a remote control frame according to the remote control frame format for transmission.

[0011] A high-speed UAV remote control framing device includes an encoder interface circuit, an FPGA chip, and a DSP. The DSP allocates three register arrays for each data channel, and each register array is set with a corresponding status word. The status word is used to identify the status of the currently stored data, including: sending, waiting to send, and receiving data.

[0012] The encoder interface circuit is used to receive data from various channels, perform level conversion, and then send the asynchronous serial data to the FPGA chip.

[0013] FPGA chips are used for parallel processing of multiple serial data streams and for serial data format conversion; they are also used for frequency division to generate remote control frame interrupt signals and send them to the DSP.

[0014] The DSP is used to read data from the FPGA chip via the bus. After reading the data, it first checks the data frame header. If the frame header is valid, it stores the data in the register array whose status is "receiving data" according to the current status word of each register array. When a frame is full, the corresponding status word changes to "waiting to send". If another register array is already in the "waiting to send" state, the status word of that other "waiting to send" register array is set to "receiving data". It is also used to respond to the interrupt signal of the FPGA chip, read the status words of each register array, point the pointer to the array waiting to send, change the status of the register array to "sending", and assemble a remote control frame according to the remote control frame format for transmission.

[0015] Compared with the prior art, the present invention has the following advantages:

[0016] This invention meets the timeliness requirements of high-speed UAVs for commands, and can send the latest UAV control commands in a timely manner at any time with a delay of no more than one remote control frame cycle.

[0017] The hardware resources of this invention are simple, highly reliable, and low in cost. Attached Figure Description

[0018] Figure 1 This is a hardware composition diagram of the present invention;

[0019] Figure 2 This is a flowchart of the signal processing of the present invention. Detailed Implementation

[0020] Below, in conjunction with Figure 1 , Figure 2 The present invention will be further described below.

[0021] The control console and encoder within the ground control station communicate in a quasi-synchronous manner. The control console sends control command frames to the encoder via an asynchronous serial method. (See reference...) Figure 1 The encoder hardware includes a power supply module, interface circuit, clock system, field programmable gate array (FPGA) and digital signal processor (DSP); the DSP allocates three register arrays for each data channel, and each register array is set with a corresponding status word. The status word is used to identify the status of the currently stored data, including: sending, waiting to send, and receiving data.

[0022] The interface circuit is used to receive data from various channels, perform level conversion, and then send the asynchronous serial data to the FPGA chip.

[0023] FPGA chips are used for parallel processing of multiple serial data streams and for serial data format conversion; they are also used for frequency division to generate remote control frame interrupt signals and send them to the DSP.

[0024] The DSP is used to read data from the FPGA chip via the bus. After reading the data, it first checks the data frame header. If the frame header is valid, it stores the data in the register array whose status is "receiving data" according to the current status word of each register array. When a frame is full, the corresponding status word changes to "waiting to send". If another register array is already in the "waiting to send" state, the status word of that other "waiting to send" register array is set to "receiving data". It is also used to respond to the interrupt signal of the FPGA chip, read the status words of each register array, point the pointer to the array waiting to send, change the status of the register array to "sending", and assemble a remote control frame according to the remote control frame format for transmission.

[0025] Reference Figure 2 A high-speed unmanned aerial vehicle (UAV) remote control framing method includes the following steps:

[0026] The interface circuit receives data from various channels, performs level conversion, and then sends the asynchronous serial data to the FPGA chip. The FPGA chip processes multiple serial data channels in parallel and performs serial data format conversion.

[0027] The DSP reads data from the FPGA chip via the bus. Each data channel is allocated three register arrays, and each register array is set with a corresponding status word. The status word is used to identify the current status of the stored data. The status includes: sending, waiting to send, and receiving data.

[0028] After the DSP reads data through the bus, it first checks the data frame header. If the frame header is valid, it stores the data in the register array whose status is "receive data" according to the current status word of each register array. When a frame is full, the corresponding status word is changed to "waiting to send". If another register array is already in the "waiting to send" state, the status word of the other "waiting to send" register array is set to "receive data".

[0029] After the FPGA chip generates a remote control frame interrupt signal through frequency division, the DSP responds to the interrupt signal, reads the status words of each register array, points the pointer to the array waiting to be sent, changes the status of the array to "sending", and assembles a remote control frame according to the remote control frame format for transmission.

[0030] The method of this invention improves the timeliness of high-speed UAV commands, ensuring that the latest control commands are sent to the UAV at any time with a delay of no more than one remote control frame cycle.

Claims

1. A method for remote-controlled framing of a high-speed unmanned aerial vehicle (UAV), characterized in that, The process includes the following: The interface circuit receives data from various channels, performs level conversion, and then sends the asynchronous serial data to the FPGA chip. The FPGA chip processes multiple serial data channels in parallel and performs serial data format conversion. The DSP reads data from the FPGA chip via the bus. Each data channel is allocated three register arrays, and each register array is set with a corresponding status word. The status word is used to identify the status of the currently stored data. The states include: sending, waiting to send, and receiving data; After the DSP reads data through the bus, it first checks the data frame header. If the frame header is valid, it stores the data in the register array whose status is "receive data" according to the current status word of each register array. When a frame is full, the corresponding status word is changed to "waiting to send". If another register array is already in the "waiting to send" state, the status word of the other "waiting to send" register array is set to "receive data". After the FPGA chip generates a remote control frame interrupt signal through frequency division, the DSP responds to the interrupt signal, reads the status words of each register array, points the pointer to the array waiting to be sent, changes the status of the array to "sending", and assembles a remote control frame according to the remote control frame format for transmission.

2. A high-speed unmanned aerial vehicle (UAV) remote control framing device, characterized in that, It includes interface circuits, FPGA chips and DSPs. The DSP allocates three register arrays for each data channel. Each register array is set with a corresponding status word. The status word is used to identify the status of the currently stored data. The status includes: sending, waiting to send, and receiving data. The interface circuit is used to receive data from various channels, perform level conversion, and then send the asynchronous serial data to the FPGA chip. FPGA chips are used for parallel processing of multiple serial data streams and for serial data format conversion; they are also used for frequency division to generate remote control frame interrupt signals and send them to the DSP. The DSP is used to read data from the FPGA chip via the bus. After reading the data, it first checks the data frame header. If the frame header is valid, it stores the data in the register array whose status is "receiving data" according to the current status word of each register array. When a frame is full, the corresponding status word changes to "waiting to send". If another register array is already in the "waiting to send" state, the status word of that other "waiting to send" register array is set to "receiving data". It is also used to respond to the interrupt signal of the FPGA chip, read the status words of each register array, point the pointer to the array waiting to send, change the status of the register array to "sending", and assemble a remote control frame according to the remote control frame format for transmission.

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