Simulation method, apparatus, device, and storage medium

Abstract

The present disclosure relates to a simulation method, device, equipment and storage medium, wherein the simulation method comprises: obtaining a local simulation model of a pre-established capacitance array region, the local simulation model being used to represent first simulation parameters of the capacitance array region; establishing a local parameter netlist of a non-capacitance array region, the local parameter netlist comprising second simulation parameters of the non-capacitance array region; based on the local simulation model and the local parameter netlist, establishing an overall parameter netlist of a peripheral region, the overall parameter netlist representing overall simulation parameters of the peripheral region, the overall simulation parameters comprising the first simulation parameters and the second simulation parameters; and based on the overall parameter netlist, simulating the peripheral region. The simulation method does not need to establish a parameter netlist of the capacitance array region, and does not need to extract parasitic parameters of the capacitance array region, which can greatly shorten the establishment time of the overall parameter netlist, and further shorten the time of the entire simulation process, thereby improving the simulation efficiency.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to, but is not limited to, the technical field of semiconductor technology, and particularly relates to a simulation method, device, equipment and storage medium. BACKGROUND

[0002] Memory structures (for example, DRAM, dynamic random access memory) are indispensable components in modern electronic systems. A plurality of cell capacitors are provided in the memory structure, cell capacitors in the same row are coupled to the same word line structure, cell capacitors in the same column are coupled to the same bit line structure, and the performance of the cell capacitors is crucial to the performance of the formed memory structure.

[0003] At present, for a designed memory structure, pre-simulation and post-simulation of the circuit are required to ensure the performance parameters of the formed memory structure. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present disclosure provides a simulation method, device, equipment and storage medium.

[0006] According to a first aspect of the embodiment of the present disclosure, a simulation method is provided, applied to a peripheral region of a memory structure, the peripheral region including a capacitor array region and a non-capacitor array region, and the simulation method includes:

[0007] obtaining a pre-established local simulation model of the capacitor array region, the local simulation model being used to represent first simulation parameters of the capacitor array region;

[0008] establishing a local parameter netlist of the non-capacitor array region, the local parameter netlist including second simulation parameters of the non-capacitor array region;

[0009] based on the local simulation model and the local parameter netlist, establishing an overall parameter netlist of the peripheral region, the overall parameter netlist representing overall simulation parameters of the peripheral region, the overall simulation parameters including the first simulation parameters and the second simulation parameters;

[0010] based on the overall parameter netlist, performing simulation and modeling of the peripheral region.

[0011] The first simulation parameters include first theoretical parameters and first parasitic parameters of the capacitor array region; or

[0012] The second simulation parameters include second theoretical parameters and second parasitic parameters of the non-capacitor array region; or

[0013] The first simulation parameter comprises a first theoretical parameter and a first parasitic parameter of the capacitor array region, and the second simulation parameter comprises a second theoretical parameter and a second parasitic parameter of the non-capacitor array region.

[0014] The local parameter netlist of the non-capacitor array region is established based on the local theoretical parameter netlist and the local parasitic parameter netlist.

[0015] The local theoretical parameter netlist is constructed and comprises the second theoretical parameter.

[0016] The second parasitic parameter of the peripheral region is extracted based on a parasitic parameter extraction program, and a local parasitic parameter netlist is established.

[0017] The local parameter netlist is established based on the local theoretical parameter netlist and the local parasitic parameter netlist.

[0018] The second parasitic parameter of the peripheral region is extracted based on a parasitic parameter extraction program, and a local parasitic parameter netlist is established.

[0019] In the process of extracting the second parasitic parameter, a preset link in the parasitic parameter extraction program is filtered, and the preset link is a verification link of the capacitor array region.

[0020] The capacitor array region comprises a plurality of preset capacitor units, the preset capacitor units comprise a plurality of unit capacitors, the first theoretical parameter comprises a first theoretical capacitance of each preset capacitor unit, and the first parasitic parameter comprises a parasitic resistance of each preset capacitor unit.

[0021] The local simulation model is established in the following manner:

[0022] A unit simulation model of the preset capacitor unit is established, and the unit simulation model is used to represent the first theoretical capacitance of the preset capacitor unit.

[0023] Based on the arrangement mode of the preset capacitor units in the capacitor array region and the unit simulation model of each preset capacitor unit, a capacitor simulation model of the capacitor array region is obtained, and the capacitor simulation model is used to represent the first theoretical capacitance of each preset capacitor unit and the arrangement mode of the preset capacitor units in the capacitor array region.

[0024] Based on the arrangement mode of the preset capacitor units, an arrangement direction of the preset capacitor units is obtained, and a parasitic resistance equivalent test structure of a group of preset capacitor units arranged in the same arrangement direction is established.

[0025] Based on the parasitic resistance equivalent test structure, the parasitic resistance of each preset capacitor unit is determined.

[0026] establish the local simulation model based on the capacitance simulation model and the parasitic resistance of each of the preset capacitor units.

[0027] The parasitic resistance equivalent test structure of the group of preset capacitor units arranged in the same arrangement direction comprises:

[0028] A wire layer is established, and the wire layer is coupled to the lower electrodes of the preset capacitor units.

[0029] A conductive layer is established, and the preset capacitor units are arranged in the conductive layer, and the conductive layer couples the upper electrodes of the group of preset capacitor units arranged in the same arrangement direction to each other in series.

[0030] The parasitic resistance equivalent test structure is established based on the wire layer and the conductive layer, and the wire layer of each of the preset capacitor units in the group of preset capacitor units is taken as an end point.

[0031] The local simulation model is established based on the capacitance simulation model and the parasitic resistance of each of the preset capacitor units, and the local simulation model comprises:

[0032] The local simulation model is established based on the equivalent capacitance of each of the preset capacitor units in the capacitance simulation model and the corresponding parasitic resistance coupled in series, and the equivalent capacitance is used to represent the first theoretical capacitance of the preset capacitor unit corresponding to the equivalent capacitance.

[0033] The local simulation model comprises a first port related to the capacitance array region and a second port related to the non-capacitance array region, and the local parameter netlist comprises a third port related to the capacitance array region and a fourth port related to the non-capacitance array region.

[0034] The overall parameter netlist of the peripheral region is established based on the local simulation model and the local parameter netlist, and the overall parameter netlist comprises:

[0035] The first port, the second port, the third port and the fourth port are invoked to establish the overall parameter netlist.

[0036] According to a second aspect of the embodiments of the present disclosure, an simulation device is provided, which is applied to a peripheral region of a storage structure, the peripheral region comprising a capacitance array region and a non-capacitance array region, and the simulation device comprises:

[0037] An acquisition module is configured to acquire a local simulation model of the capacitance array region, which is established in advance, and the local simulation model is used to represent first simulation parameters of the capacitance array region.

[0038] The establishing module is configured to establish a local parameter netlist of the non-capacitor array region, the local parameter netlist comprising a second simulation parameter of the non-capacitor array region;

[0039] The establishing module is further configured to establish, based on the simulation model and the parameter netlist, a global parameter netlist of the peripheral region, the global parameter netlist representing a global simulation parameter of the peripheral region, the global simulation parameter comprising the first simulation parameter and the second simulation parameter.

[0040] The simulation module is configured to simulate the peripheral region based on the global parameter netlist.

[0041] The first simulation parameter comprises a first theoretical parameter and a first parasitic parameter of the capacitor array region; or

[0042] The second simulation parameter comprises a second theoretical parameter and a second parasitic parameter of the non-capacitor array region; or

[0043] The first simulation parameter comprises a first theoretical parameter and a first parasitic parameter of the capacitor array region, and the second simulation parameter comprises a second theoretical parameter and a second parasitic parameter of the non-capacitor array region.

[0044] The establishing module is specifically configured to:

[0045] construct a local theoretical parameter netlist of the non-capacitor array region, the local theoretical parameter netlist comprising the second theoretical parameter;

[0046] extract a second parasitic parameter of the peripheral region based on a parasitic parameter extraction program to establish a local parasitic parameter netlist;

[0047] establish the local parameter netlist based on the local theoretical parameter netlist and the local parasitic parameter netlist.

[0048] The establishing module is further configured to:

[0049] filter a preset link in the parasitic parameter extraction program in the process of extracting the second parasitic parameter, the preset link being a verification link of the capacitor array region.

[0050] The capacitor array region comprises a plurality of preset capacitor units, the preset capacitor units comprising a plurality of unit capacitors, the first theoretical parameter comprising a first theoretical capacitance of each of the preset capacitor units, and the first parasitic parameter comprising a parasitic resistance of each of the preset capacitor units.

[0051] The local simulation model includes a first port related to the capacitor array region and a second port related to the non-capacitor array region, and the local parameter netlist includes a third port related to the capacitor array region and a fourth port related to the non-capacitor array region,

[0052] The establishing module is further configured to:

[0053] The first port, the second port, the third port and the fourth port are called to establish the overall parameter netlist.

[0054] According to a third aspect of the embodiments of the present disclosure, an emulation device applied to a peripheral region of a storage structure is provided, the peripheral region including a capacitor array region and a non-capacitor array region, and the emulation device includes:

[0055] a processor;

[0056] a memory for storing processor-executable instructions;

[0057] The processor is configured to perform the emulation method according to the first aspect.

[0058] According to a fourth aspect of the embodiments of the present disclosure, a non-transitory computer-readable storage medium is provided, when instructions in the storage medium are executed by a processor of an emulation device, the emulation device is enabled to perform the emulation method according to the first aspect.

[0059] The above technical solutions have the following advantages: the emulation method does not need to establish a parameter netlist of the capacitor array region, and does not need to extract parasitic parameters of the capacitor array region, so that the establishment time of the overall parameter netlist can be greatly shortened, and the time of the entire simulation process is also shortened, thereby improving the simulation efficiency. Moreover, since the layout of the capacitor array region is generally regular, the local simulation model can be easily established in advance, and the reliability of the local simulation model is also good. The overall parameter netlist obtained finally has high precision, and the simulation effect is good.

[0060] Other aspects can become apparent from the following detailed description when read in conjunction with the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0061] In the drawings, like reference numerals refer to same or similar functionalities throughout the several views. The drawings are not necessarily to scale. It is to be understood that the drawings only depict several embodiments of the disclosure and are not to be considered as limiting its scope.

[0062] Figure 1 is a flowchart of an emulation method according to an exemplary embodiment;

[0063] Figure 1a is a schematic diagram of a storage structure according to an example;

[0064] Figure 1b is a schematic diagram of a capacitor array region according to an example;

[0065] Figure 1c is a schematic diagram of a capacitor simulation model according to an example;

[0066] Figure 1d is a schematic diagram of a capacitor array region according to an example;

[0067] Figure 1e is a schematic diagram of a capacitor array region according to an example;

[0068] Figure 1f is a schematic diagram of an initial simulation model according to an example;

[0069] Figure 1g is a schematic diagram of a partial simulation model according to an example;

[0070] Figure 1h is a schematic diagram of a capacitor array region according to an example;

[0071] Figure 1i is a schematic diagram of a connection of a partial simulation model to a partial parameter netlist according to an example;

[0072] Figure 2 is a block diagram of a simulation apparatus according to an example embodiment.

[0073] Figure 3 is a block diagram of a simulation apparatus according to an example embodiment. DETAILED DESCRIPTION

[0074] Hereinafter, certain example embodiments are described simply. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure. Thus, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0075] REFERENCE Figure 1aAs shown, the storage structure 1 (for example, DDR (the full name of DDR is DDR SDRAM (Double Data Rate SDRAM (synchronous dynamic random-access memory)), that is, double rate synchronous dynamic random access memory) or other storage structure (DRAM), for example, synchronous dynamic random access memory (SDRAM)) generally includes a peripheral area 11 and a storage area 12. Figure 1a The area surrounded by the dashed box in the peripheral area 11 does not exist in the actual storage structure 1 Figure 1a The dashed box here is only used to distinguish the peripheral area 11 and the storage area 12.

[0076] The storage area 12 generally includes a capacitor array, and the peripheral area 11 is used for signal processing to assist the storage area 12 to realize the storage function (including reading and writing). When simulating the peripheral area 11, generally, the parameter netlist of the entire peripheral area 11 needs to be directly established. When the parameter netlist is established, the extraction of the parasitic parameters of the entire peripheral area 11 is involved.

[0077] The peripheral area 11 generally includes a capacitor array area 111 composed of capacitor units and a non-capacitor array area 112 composed of processing circuits. The capacitor array area 111 can include at least one capacitor array sub-area, for example, referring to Figure 1a As shown, the capacitor array area 111 includes four capacitor array sub-areas, namely capacitor array sub-area 111a, capacitor array sub-area 111b, capacitor array sub-area 111c and capacitor array sub-area 111d.

[0078] In the process of extracting the parasitic parameters of the capacitor array area 111 using the parasitic parameter extraction program, a large amount of time is often needed to analyze the topology of the capacitor array in the capacitor array area 111, a large amount of physical memory of the parasitic parameter extraction device is occupied, the overall operation is slow, and the subsequent simulation simulation is also affected.

[0079] However, the layout of the capacitor array area 111 is generally regular, and the layout of the capacitor array area 111 in different storage structures 1 is generally not changed or changed slightly.

[0080] In view of this, this disclosure provides a simulation method applied to the peripheral region of a memory structure, which includes a capacitor array region and a non-capacitor array region. In this simulation method, a local simulation model of the capacitor array region is pre-established, eliminating the need to create a parameter netlist for the capacitor array region. Instead, a local parameter netlist for the non-capacitor array region is directly created. Then, based on the local simulation model and the local parameter netlist, a global parameter netlist for the entire peripheral region is created to simulate the peripheral region.

[0081] This simulation method eliminates the need to build a parameter netlist for the capacitor array region and extract parasitic parameters, significantly reducing the time required to build the overall parameter netlist and thus shortening the overall simulation time, thereby improving simulation efficiency. Furthermore, since the layout of the capacitor array region is generally quite regular, it is easy to pre-build local simulation models, which also have good reliability. The final overall parameter netlist obtained also has high accuracy, resulting in good simulation performance.

[0082] refer to Figure 1 As shown, the simulation method provided in this embodiment includes:

[0083] S110, Obtain the pre-established local simulation model of the capacitor array region;

[0084] S120, Establish the local parameter netlist for the non-capacitor array region;

[0085] S130, based on the local simulation model and local parameter netlist, establish the overall parameter netlist for the peripheral region;

[0086] S140, based on the overall parameter netlist, performs simulation of the peripheral region.

[0087] In step S101, refer to Figure 1a and 1i As shown, the simulation model of the capacitor array region 111 is denoted as local simulation model 111'. The simulation parameters of the capacitor array region 111 are denoted as the first simulation parameters. The theoretical parameters (also called ideal parameters, i.e., the parameters for designing the capacitor array region) of the capacitor array region 111 are denoted as the first theoretical parameters. The parasitic parameters of the capacitor array region 111 are denoted as the first parasitic parameters.

[0088] The local simulation model 111' is used to characterize the first simulation parameters. These first simulation parameters may include first theoretical parameters and first parasitic parameters. The first theoretical parameters may include the theoretical capacitance (also called the ideal capacitance) of the capacitor array region 111. The first parasitic parameters may include the parasitic resistance, parasitic capacitance, etc., of the capacitor array region 111.

[0089] Since the layout of the capacitor array region 111 is relatively regular, a local simulation model 111' can be established according to the capacitor elements of the capacitor array region 111 and the arrangement manner of the capacitor elements.

[0090] It should be noted that the local simulation model and the local parameter netlist are a group of data, Figure 1i The schematic diagram of the local simulation model and the local parameter netlist is shown for ease of understanding.

[0091] In step S120, the reference Figure 1a and 1i It is shown that the parameter netlist of the non-capacitor array region 112 is recorded as a local parameter netlist. The simulation parameters of the non-capacitor array region 112 are recorded as second simulation parameters. The theoretical parameters of the non-capacitor array region 112 are recorded as second theoretical parameters. The parasitic parameters of the non-capacitor array region 112 are recorded as second parasitic parameters.

[0092] The local parameter netlist 112' includes the second simulation parameters. The second simulation parameters can include the second theoretical parameters and the second parasitic parameters. The second theoretical parameters can include the theoretical capacitance, the theoretical resistance (also called ideal resistance) of the non-capacitor array region 112, etc. The second theoretical parameters can be determined based on the design of the non-capacitor array region 112. The second parasitic parameters can include the parasitic capacitance, the parasitic resistance of the non-capacitor array region 112, etc. The second parasitic parameters can be extracted by a parasitic parameter extraction program.

[0093] In step S130, the reference Figure 1i It is shown that the local simulation model 111' and the local parameter netlist 112' can be connected and merged to form a parameter netlist of the peripheral region 11. The parameter netlist of the peripheral region 11 is recorded as a whole parameter netlist 11'.

[0094] The whole parameter netlist 11' represents the whole simulation parameters of the peripheral region 11, and the whole simulation parameters include the first simulation parameters and the second simulation parameters. That is, the whole parameter netlist 11' represents the simulation parameters of the capacitor array region 111 and the simulation parameters of the non-capacitor array region 112, so as to facilitate subsequent reliable simulation simulation.

[0095] In step S140, the reference Figure 1a and 1i It is shown that the whole parameter netlist 11' can be used as the parameter netlist of the peripheral region 11 to simulate and simulate the peripheral region 11, and complete the post-layout simulation of the peripheral region 11.

[0096] In the simulation method, based on the characteristics of the capacitor array region, a local simulation model for representing the first simulation parameter of the capacitor array region is established in advance. The extraction of the parasitic parameter is only performed on the non-capacitor array region, and then the local parameter netlist of the non-capacitor array region is established in combination with the second theoretical parameter of the non-capacitor array region. Finally, the local simulation model and the local parameter netlist are combined to obtain the overall parameter netlist. The simulation effect can be ensured to be good, the establishment time of the overall parameter netlist can be greatly shortened, and then the time of the entire simulation process can be shortened, and the simulation efficiency is improved.

[0097] In one example embodiment, a simulation method is provided. In the simulation method, the local parameter netlist of the non-capacitor array region is established, including:

[0098] S210, constructing a local theoretical parameter netlist;

[0099] S220, extracting the second parasitic parameter of the peripheral region based on a parasitic parameter extraction program, and establishing a local parasitic parameter netlist;

[0100] S230, establishing a local parameter netlist based on the local theoretical parameter netlist and the local parasitic parameter netlist.

[0101] In step S210, as shown in Figure 1a and 1i , the theoretical parameter of the non-capacitor array region 112 is recorded as the second theoretical parameter. The theoretical parameter netlist of the non-capacitor array region 112 is recorded as the local theoretical parameter netlist. The local theoretical parameter netlist includes the second theoretical parameter. The second theoretical parameter can be determined based on the design information of the non-capacitor array region 112.

[0102] In step S220, as shown in Figure 1a and 1i , the parasitic parameter of the non-capacitor array region 112 is recorded as the second parasitic parameter. The parasitic parameter netlist of the non-capacitor array region 112 is recorded as the local parasitic parameter netlist.

[0103] In this step, the parasitic parameter extraction program can be used for extraction. For example, the EDA (Electronics Design Automation) tool (the EDA tool is provided with the parasitic parameter extraction program) is used to extract the second parasitic parameter of the peripheral region 11. The second parasitic parameter of the peripheral region 11 is the parasitic parameter of the non-capacitor array region 111.

[0104] In this step, after the parasitic parameter extraction program obtains the parasitic parameter of the non-capacitor array region 112, the parasitic parameter netlist of the non-capacitor array region 112 can be established based on the parasitic parameter of the non-capacitor array region 112.

[0105] In step S230, referenceFigure 1a and 1i As shown, the local theoretical parameter netlist and the local parasitic parameter netlist can be connected and merged to obtain the local parameter netlist 112'. That is, the theoretical parameter netlist and the parasitic parameter netlist of the non-capacitor array region 112 are merged to obtain the parameter netlist of the non-capacitor array region 112. This parameter netlist of the non-capacitor array region 112 includes the theoretical parameters and parasitic parameters of the non-capacitor array region 112, facilitating subsequent simulation.

[0106] In this simulation method, a local theoretical parameter netlist is constructed based on the design information of the non-capacitor array region. A local parasitic parameter netlist is then established using a parasitic parameter extraction program. Finally, based on the local theoretical parameter netlist and the local parasitic parameter netlist, a local parameter netlist is constructed, resulting in a highly accurate local parameter netlist and improving the reliability of subsequent simulations.

[0107] In one exemplary embodiment, a simulation method is provided. This simulation method, based on a parasitic parameter extraction procedure, extracts second parasitic parameters from a peripheral region and establishes a local parasitic parameter netlist, including:

[0108] S310, during the extraction of the second parasitic parameter, filters the preset steps in the parasitic parameter extraction program.

[0109] The preset step is the verification step of capacitor array region 111.

[0110] That is, reference Figure 1a As shown, in this simulation method, when extracting parasitic parameters using the parasitic parameter extraction program, the verification step for the capacitor array region 111 is skipped. The capacitor array region 111 is not verified or analyzed; only the parasitic parameters (i.e., the second parasitic parameters) of the non-capacitor array region 112 are extracted. This simulation method saves the parasitic parameter extraction program from processing unnecessary regions, increases the extraction speed of parasitic parameters, and thus improves the overall simulation speed and efficiency.

[0111] It should be noted that the reference Figure 1a and 1iAs shown, when the parasitic parameters are extracted by using the parasitic parameter extraction program, the entire peripheral region 11 needs to be connected to the EDA tool. Since the simulation model (i.e., the local simulation model 111') of the capacitive array region 111 is established in advance, the parasitic parameters of the capacitive array region 111 do not need to be extracted by using the parasitic parameter extraction program, and the capacitive array region 111 does not need to be verified. Therefore, during the running of the parasitic parameter extraction program, the steps related to the capacitive array region 111 (i.e., the preset steps) can be filtered out, and the parasitic parameters of the non-capacitive array region 112 can be directly extracted. This not only does not affect the extraction accuracy of the second parasitic parameters, but also improves the extraction speed of the second parasitic parameters.

[0112] In one example embodiment, a simulation method is provided. Referring to Figure 1i As shown, in the simulation method, the local simulation model 111' includes a first port D1 related to the capacitive array region 111 and a second port D2 related to the non-capacitive array region 112. The local parameter netlist 112 includes a third port D3 related to the capacitive array region 111 and a fourth port D4 related to the non-capacitive array region 112.

[0113] It should be noted that the local simulation model and the local parameter netlist are a set of data, and the first port, the second port, the third port, and the fourth port are only virtual ports, Figure 1i The connection diagram of the local simulation model and the local parameter netlist shown is only for the convenience of understanding.

[0114] In this method, based on the local simulation model and the local parameter netlist, the overall parameter netlist of the peripheral region is established, including:

[0115] S410, calling the first port, the second port, the third port, and the fourth port to establish the overall parameter netlist.

[0116] As shown in Figure 1a and 1i As shown, the first port D1 and the third port D3 are both related to the capacitive array region 111. When the first port D1 and the third port D3 are called, the first port D1 of the local simulation model 111' is connected to the third port D3 of the local parameter netlist 112'. The second port D2 and the fourth port D4 are both related to the non-capacitive array region 112. When the second port D2 and the fourth port D4 are called, the second port D2 of the local simulation model 111' is connected to the fourth port D4 of the local parameter netlist 112'. In this way, the local simulation model 111' and the local parameter netlist 112' can be combined to establish the overall parameter netlist 111'.

[0117] In the simulation method, a first port related to the capacitor array region and a second port related to the non-capacitor array region are reserved in the local simulation model, and a third port related to the capacitor array region and a fourth port related to the non-capacitor array region are reserved in the local parameter netlist, so that the correctness of the connection relationship of the overall parameter netlist can be ensured, the connection relationship of the overall parameter netlist is the same as the connection relationship of the circuit in the peripheral region, the reliability of the overall parameter netlist is ensured, and the reliability of the subsequent simulation model is better ensured.

[0118] In one example embodiment, a simulation method is provided. In the simulation method, the capacitor array region includes a plurality of preset capacitor units. The preset capacitor unit includes a plurality of unit capacitors (e.g., capacitor elements). The first theoretical parameter includes a first theoretical capacitance of each preset capacitor unit, and the first parasitic parameter includes a parasitic resistance of each preset capacitor unit.

[0119] Example 1,

[0120] Reference Figure 1b As shown in the figure, the unit capacitors 203 can be distributed in a matrix, specifically, in a 3-column and 3-row matrix array, to form a preset capacitor unit 102. The unit capacitors 203 are coupled into a whole by the conductive layer 101.

[0121] The preset capacitor unit 102 can also be distributed in a matrix, specifically, in a 4-column and 3-row matrix array, to form a capacitor array region 100. The preset capacitor units 102 are coupled into a whole by the conductive layer 101.

[0122] The conductive wire 104 connects the lower electrodes of the preset capacitor units 102, and is used for simulating the capacitor array region 100 as a whole.

[0123] It should be noted that, in the embodiment, the unit capacitors are distributed in a matrix to form the preset capacitor unit, and the preset capacitor units are distributed in a matrix to form the capacitor array region, which is only an introduction to one implementation of the capacitor array region and the preset capacitor unit, and does not constitute a limitation on the capacitor array region and the preset capacitor unit. In specific applications, the unit capacitors and the preset capacitor units can also adopt other arrangement modes.

[0124] In the simulation method, a first port related to the capacitor array region and a second port related to the non-capacitor array region are reserved in the local simulation model, and a third port related to the capacitor array region and a fourth port related to the non-capacitor array region are reserved in the local parameter netlist, so that the correctness of the connection relationship of the overall parameter netlist can be ensured, the connection relationship of the overall parameter netlist is the same as the connection relationship of the circuit in the peripheral region, the reliability of the overall parameter netlist is ensured, and the reliability of the subsequent simulation model is better ensured.

[0125] S510, a unit simulation model of the preset capacitor unit is established;

[0126] S520, based on the arrangement mode of the preset capacitor units in the capacitor array region and the unit simulation model of each preset capacitor unit, a capacitor simulation model of the capacitor array region is obtained;

[0127] S530, based on the arrangement mode of the preset capacitive units, obtaining an arrangement direction of the preset capacitive units, and establishing a parasitic resistance equivalent test structure of a group of preset capacitive units in the same arrangement direction;

[0128] S540, based on the parasitic resistance equivalent test structure, determining the parasitic resistance of each preset capacitive unit;

[0129] S550, based on the capacitive simulation model and the parasitic resistance of each preset capacitive unit, establishing a local simulation model.

[0130] In step S510, the theoretical capacitance of the preset capacitive unit is denoted as the first theoretical capacitance, and the theoretical capacitance of the unit capacitor is denoted as the second theoretical capacitance. The unit simulation model is used to represent the first theoretical capacitance of the preset capacitive unit. Wherein, the unit simulation model can be established based on the number of unit capacitors in the preset capacitive unit and the second theoretical capacitance of the unit capacitors.

[0131] Example 2,

[0132] Reference Figure 1c As shown, the unit capacitors 203 are distributed in a matrix, specifically in a 3x3 matrix array, to form a preset capacitive unit 200. The preset capacitive unit 202 couples the unit capacitors 203 into a whole through the conductive layer 201. The capacitor array region 200 includes two preset capacitive units, denoted as the first preset capacitive unit 202a and the second preset capacitive unit 202b. The capacitor array region 200 couples the first preset capacitive unit 202a and the second preset capacitive unit 202b into a whole through the conductive layer 201. The conductive wire 204 connects the lower electrodes of the preset capacitive units, and is used to simulate the capacitor array region 200 as a whole capacitor.

[0133] In this example, a preset capacitive unit (such as the first preset capacitive unit 202a or the second preset capacitive unit 202b) includes 9 unit capacitors 203, wherein the second theoretical capacitances of the 9 unit capacitors 203 are the same, the unit simulation model is used to represent the first theoretical capacitance of a preset capacitive unit, and the first theoretical capacitance is 9 times the second theoretical capacitance of the unit capacitors 203.

[0134] It should be noted that in other examples, if the capacitance values of the 9 unit capacitors are different, the unit simulation model is used to represent the capacitance value of a preset capacitive unit as the sum of the second theoretical capacitances of the 9 unit capacitors.

[0135] In step S520, the capacitive simulation model is used to represent the first theoretical capacitance of each preset capacitive unit and the arrangement mode of the preset capacitive units in the capacitor array region.

[0136] In this step, the connection relationship of each preset capacitor unit can be obtained according to the arrangement mode of the preset capacitor units in the capacitor array region. Based on the connection relationship of each preset capacitor unit and the unit simulation model of the preset capacitor unit, the capacitor simulation model of the capacitor array region can be obtained.

[0137] Example 3,

[0138] Reference Figure 1c and 1d As shown in FIG. 3, the capacitor array region in Example 3 is the same as that in Example 2, and will not be described again.

[0139] In this example, the arrangement direction of the preset capacitor units is defined as the X direction, and the Y direction is perpendicular to the arrangement direction of the preset capacitor units. The unit simulation models of two preset capacitor units are connected in series to form the capacitor simulation model of the capacitor array region 200. The capacitor simulation model includes a first equivalent capacitor Cap1 and a second equivalent capacitor Cap2, the first equivalent capacitor Cap1 is used to represent the theoretical capacitance of the first preset capacitor unit 202a, and the second equivalent capacitor Cap2 is used to represent the theoretical capacitance of the second preset capacitor unit 202b.

[0140] It should be noted that in other embodiments, if the capacitor array region includes preset capacitor units arranged in multiple rows or multiple columns, the arrangement direction of the preset capacitor units needs to be determined according to the direction of the conductive wire connection (i.e., the X direction and the Y direction). In the X direction, the unit simulation models of the preset capacitor units are coupled in series; in the Y direction, the simulation models of the preset capacitor units are coupled in parallel.

[0141] In addition, it should be noted that the capacitor array region composed of two preset capacitor units is only an example of establishing a capacitor simulation model for this example, and does not constitute a limitation on this embodiment. In other examples, the establishment of the capacitor simulation model can be performed according to the number of preset capacitor units in the actual capacitor array region.

[0142] In step S530, after determining the arrangement mode of the preset capacitor units, the arrangement direction of the preset capacitor units can be determined based on the arrangement mode. Then, the parasitic resistance equivalent test structure of a group of preset capacitor units arranged in the same direction can be established, so as to more accurately determine the parasitic resistance of the preset capacitor units.

[0143] The parasitic resistance equivalent test structure of a group of preset capacitor units arranged in the same direction includes:

[0144] S531, establishing a wire layer, the wire layer is coupled to the lower electrode of the preset capacitor unit;

[0145] S532, establishing a conductive layer, the preset capacitor units are arranged in the conductive layer, and the conductive layer couples the upper electrodes of a group of the preset capacitor units in the same arrangement direction to each other in series;

[0146] S533, based on the wire layer and the conductive layer, establishing the parasitic resistance equivalent test structure with the wire layer of each of the preset capacitor units in the group of the preset capacitor units as an end point.

[0147] Example 4,

[0148] Reference Figure 1c and 1e As shown in FIG. 4, the capacitor array region in Example 4 is the same as that in Example 2, and thus is not described again.

[0149] In this example, the wire layer 204 can be coupled to the lower electrode 206 of the preset capacitor unit 202 through the bottom conductive layer 207, which is a capacitor landing pad structure used to change the arrangement mode of the unit capacitor 203 in the storage structure.

[0150] The preset capacitor unit 202 is arranged in the conductive layer 201, and the conductive layer 201 couples the upper electrodes 205 of a group of the preset capacitor units 202 in the same arrangement direction to each other in series.

[0151] It should be noted that there can be a capacitor dielectric layer between the upper electrode 205 and the lower electrode 206, but the capacitor dielectric layer is not related to the content of the application in this example, and thus is not shown in the drawing.

[0152] Based on the conductive layer 201 and the wire layer 204, the parasitic resistance equivalent test structure is determined with the wire layer 204 of each of the preset capacitor units 202 in the group of the preset capacitor units as an end point.

[0153] In step S540, one of the preset capacitor units in the capacitor array region is selected as a target preset capacitor unit, and the preset interface of the conductive layer where the adjacent preset capacitor unit is located is taken as a separation interface (for example, as shown by the dashed line in FIG. 4), to define the equivalent conductive layer of the preset capacitor unit. Figure 1b

[0154] It should be noted that if the number of the group of the preset capacitor units in the arrangement direction is greater than or equal to 3, then, except for the two preset capacitor units at the edges, the equivalent conductive layers of the remaining preset capacitor units are defined by the separation interfaces located on both sides, and for the equivalent conductive layers located at the edges, the equivalent conductive layer is defined by the separation interface located on one side and the edge of the conductive layer.

[0155] ​In this step, the preset interface is the middle line interface of the conductive layer where the adjacent preset capacitor unit is located. Taking the middle line interface of the conductive layer as the preset interface makes the parasitic resistance of the obtained preset capacitor unit more accurate.

[0156] Example 5,

[0157] Referring to Figure 1c and 1f As shown in FIG. 5, the capacitor array region in Example 5 is the same as that in Example 2, and thus will not be described again.

[0158] In this example, the left first preset capacitor unit 202a is taken as an example to be described in detail.

[0159] Based on the arrangement direction of the first preset capacitor unit 202a and the second preset capacitor unit 202b, that is, based on the X direction, the minimum distance between the boundary of the target preset capacitor unit and the boundary of the equivalent conductive layer where the target preset capacitor unit is located is obtained.

[0160] In the arrangement direction of the preset capacitor unit (that is, the X direction), the first side minimum distance b and the second side minimum distance f of the boundary of the target preset capacitor unit from the separation boundary are obtained, the first side minimum distance b is close to the left end point A, and the second side minimum distance is away from the left end point A. In this example, since the capacitor array region 200 composed of two preset capacitor units is taken as an example to be described in detail, there is no separation boundary on the side close to the end point A of the target preset capacitor unit, but the boundary of the equivalent conductive layer, and thus the first minimum distance b is obtained based on the boundary of the equivalent conductive layer as the separation boundary.

[0161] Based on the arrangement direction perpendicular to the arrangement direction of the preset capacitor unit, that is, based on the Y direction, the minimum distance between the boundary of the target preset capacitor unit and the boundary of the equivalent conductive layer is obtained.

[0162] In the arrangement direction perpendicular to the arrangement direction of the preset capacitor unit, the first minimum distance a of the upper boundary of the target preset capacitor unit from the upper boundary of the equivalent conductive layer is obtained, and the second minimum distance c of the lower boundary of the target preset capacitor unit from the lower boundary of the equivalent conductive layer is obtained.

[0163] In the arrangement direction of the preset capacitor unit and the arrangement direction perpendicular to the arrangement direction of the preset capacitor unit, the characteristic quantity of the capacitor unit in the target preset capacitor unit is obtained. The characteristic quantity includes the number of capacitor units, the distance between the capacitor units, and the line width of the capacitor units.

[0164] Referring to Figure 1fAs shown, the characteristic quantities include nc, L-nc, nr, L-nr, d, and e. Among them, nc is the number of unit capacitors 203 in the X direction, L-nc is the line width of the unit capacitors 203 in the X direction, and d is the spacing of the unit capacitors 203 in the X direction; nr is the number of unit capacitors 203 in the Y direction, L-nr is the line width of the unit capacitors 203 in the Y direction, and e is the spacing of the unit capacitors 203 in the Y direction.

[0165] Based on the minimum distance and the characteristic quantities, obtaining the parasitic resistance of the target preset capacitor unit can include:

[0166] The parasitic resistance of the target preset capacitor unit is determined based on the following formula:

[0167] R = Rtcp * (L-nc*nc / 2+b / 2+f-d) / (L-nr*nr+a+c-e);

[0168] Among them, R is the parasitic resistance, Rtcp is the resistivity of the equivalent conductive layer, that is, the circuit resistivity of the conductive layer 201; b is the minimum distance of the first side, f is the minimum distance of the second side; nc is the number of unit capacitors in the X direction, L-nc is the line width of the unit capacitors 203 in the X direction, and d is the spacing of the unit capacitors 203 in the X direction; nr is the number of unit capacitors 203 in the Y direction, L-nr is the line width of the unit capacitors 203 in the Y direction, and e is the spacing of the unit capacitors 203 in the Y direction; a and c are the minimum distances of the boundary of the target preset capacitor unit to the boundary of the capacitor array region 111 in the Y direction, respectively.

[0169] Based on the minimum distance and the characteristic quantities defined in the X direction and the Y direction, the formula for obtaining the parasitic capacitance R is applicable to the capacitor array region 111 in any arrangement. In the capacitor array region 111 in any arrangement, since there are at least two conductive layers, the parasitic resistance equivalent test structure is determined by the conductive layer, thereby determining the X direction (which can be referred to as Figure 1b 、 1c 、1f) and the Y direction (which can be referred to as Figure 1b 、 1c 、1f), ensuring that there is only one X direction and Y direction in the capacitor array region, thereby ensuring the applicability of the formula for determining the parasitic capacitance R.

[0170] The above steps are repeated to obtain the parasitic resistance of each preset capacitor unit in the capacitor array region.

[0171] In step S550, a local simulation model can be established based on the equivalent capacitance of each preset capacitor unit in the capacitance simulation model coupled with the corresponding parasitic resistance.

[0172] The equivalent capacitance is used to represent a first theoretical capacitance of a preset capacitance unit corresponding to the equivalent capacitance.

[0173] Example 6,

[0174] Referring to Figure 1c , 1g and 1h, the capacitance array region in Example 6 is the same as that in Example 2, and will not be repeated here.

[0175] In this example, the capacitance simulation model includes a first equivalent capacitance Cap1 and a second equivalent capacitance Cap2. The first parasitic resistance R1 is the parasitic resistance determined by the first preset capacitance unit 202a according to step S540, and the second parasitic resistance R2 is the parasitic resistance determined by the second preset capacitance unit 202b according to step S540.

[0176] The first equivalent capacitance Cap1 is coupled in series with the first parasitic resistance R1, and the second equivalent capacitance Cap2 is coupled in series with the second parasitic resistance R2, to form an initial simulation model. Referring to Figure 1g , the initial simulation model includes the first equivalent capacitance Cap1, the first parasitic resistance R1, the second equivalent capacitance Cap2, and the second parasitic resistance R2.

[0177] Then, the first equivalent capacitance Cap1, the first parasitic resistance R1, the second equivalent capacitance Cap2, and the second parasitic resistance R2 in the initial simulation model are equivalent to an equivalent capacitance, denoted as a third equivalent capacitance Cap3, to form a final local simulation model. That is, referring to Figure 1h , the local simulation model includes the third equivalent capacitance Cap3. The local simulation model is established based on the equivalent capacitances of the preset capacitance units in the capacitance simulation model being coupled in series with the corresponding parasitic resistances. The local simulation model takes into account the performance impact of the parasitic resistances of the preset capacitance units on the formed storage structure, improving the accuracy and reliability of the simulation results of the storage structure.

[0178] In this simulation method, an accurate local simulation model and a local parameter netlist can be obtained, and then based on the above accurate local simulation model and the local parameter netlist, a whole parameter netlist of the peripheral region is established to improve the accuracy and reliability of the simulation results. In addition, when establishing the local parameter netlist, the parasitic parameter extraction program does not need to perform a verification link on the capacitance array region, which can improve the speed of parasitic parameter extraction, and further improve the speed of establishing the local parameter netlist and the speed of the entire simulation simulation. That is, the simulation method can realize efficient and reliable simulation.

[0179] The simulation device is applied to a peripheral region of a storage structure, and the peripheral region includes a capacitor array region and a non-capacitor array region. The simulation device is used to implement the simulation method described above, so as to improve the efficiency and reliability of simulation of the storage structure.

[0180] In one example embodiment, a simulation device is provided. Referring to Figure 2 the simulation device can include an acquisition module 10, a building module 20 and a simulation module 30, and the simulation device is used to implement the simulation method described above,

[0181] The acquisition module 10 is configured to acquire a pre-established local simulation model of the capacitor array region, and the local simulation model is used to represent first simulation parameters of the capacitor array region.

[0182] The building module 20 is configured to build a local parameter netlist of the non-capacitor array region, and the local parameter netlist includes second simulation parameters of the non-capacitor array region.

[0183] The building module 20 is further configured to build an overall parameter netlist of the peripheral region based on the simulation model and the parameter netlist, and the overall parameter netlist represents overall simulation parameters of the peripheral region, and the overall simulation parameters include the first simulation parameters and the second simulation parameters.

[0184] The simulation module 30 is configured to simulate the peripheral region based on the overall parameter netlist.

[0185] The first simulation parameters can include first theoretical parameters and first parasitic parameters of the capacitor array region. The second simulation parameters can include second theoretical parameters and second parasitic parameters of the non-capacitor array region.

[0186] In one example embodiment, a simulation device is provided. Referring to Figure 2 the simulation device, the building module 20 is specifically configured to:

[0187] build a local theoretical parameter netlist of the non-capacitor array region, and the local theoretical parameter netlist includes the second theoretical parameters.

[0188] extract the second parasitic parameters of the peripheral region based on a parasitic parameter extraction program, and build a local parasitic parameter netlist;

[0189] build the local parameter netlist based on the local theoretical parameter netlist and the local parasitic parameter netlist.

[0190] In one example embodiment, a simulation device is provided. Referring to Figure 2 the simulation device, the building module 20 is further configured to:

[0191] In the process of extracting the second parasitic parameter, a preset link in the parasitic parameter extraction procedure is filtered, and the preset link is a verification link for the capacitor array region.

[0192] In one example embodiment, a simulation device is provided. In the simulation device, the capacitor array region includes a plurality of preset capacitor units, each of the preset capacitor units includes a plurality of unit capacitors, the first theoretical parameter includes a first theoretical capacitance of each of the preset capacitor units, and the first parasitic parameter includes a parasitic resistance of each of the preset capacitor units.

[0193] In one example embodiment, a simulation device is provided. In the simulation device, the local simulation model includes a first port related to the capacitor array region and a second port related to the non-capacitor array region, and the local parameter netlist includes a third port related to the capacitor array region and a fourth port related to the non-capacitor array region,

[0194] Reference is made to Figure 2 As shown in the figure, the establishing module 20 is further configured to:

[0195] The first port, the second port, the third port and the fourth port are invoked to establish the overall parameter netlist.

[0196] In one example embodiment, a simulation device is also provided, which is applied to a peripheral region of a storage structure, and the peripheral region includes a capacitor array region and a non-capacitor array region. Reference is made to Figure 3 As shown in the figure, the simulation device 300 can be provided as a server. The simulation device 300 can include a processor 301, and the number of the processor can be set to one or more as needed. The simulation device 300 can also include a memory 302 for storing executable instructions of the processor 301, such as an application program. The number of the memory can be set to one or more as needed. The application program stored therein can be one or more. The processor 301 is configured to execute the instructions to perform the memory test method described above.

[0197] For example, the processor 301 is configured to execute:

[0198] Obtain a local simulation model of the capacitor array region, which is used to represent first simulation parameters of the capacitor array region;

[0199] Establish a local parameter netlist of the non-capacitor array region, which includes second simulation parameters of the non-capacitor array region;

[0200] Based on the local simulation model and the local parameter netlist, establish an overall parameter netlist of the peripheral region, which represents overall simulation parameters of the peripheral region, and the overall simulation parameters include the first simulation parameters and the second simulation parameters;

[0201] Based on the overall parameter netlist, the peripheral region is simulated.

[0202] In one example embodiment, a non-transitory computer readable storage medium (not shown in the figure) is also provided, which, when the instructions in the storage medium are executed by the processor of the simulation device described above, enables the simulation device to perform the simulation method described above.

[0203] For example, when the instructions in the storage medium are executed by the processor of the simulation device described above, the simulation device is enabled to perform:

[0204] Obtaining a local simulation model of the pre-established capacitor array region, the local simulation model being used to represent first simulation parameters of the capacitor array region;

[0205] Establishing a local parameter netlist of the non-capacitor array region, the local parameter netlist including second simulation parameters of the non-capacitor array region;

[0206] Based on the local simulation model and the local parameter netlist, an overall parameter netlist of the peripheral region is established, the overall parameter netlist representing overall simulation parameters of the peripheral region, the overall simulation parameters including the first simulation parameters and the second simulation parameters;

[0207] Based on the overall parameter netlist, the peripheral region is simulated.

[0208] Those skilled in the art will appreciate that embodiments herein can be provided as a method, apparatus, or computer program product. Accordingly, embodiments herein can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments herein can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, it should be appreciated by those skilled in the art that a computer program product can be tangibly embodied as a signal carrier, such as a server, cloud, or other device, carrying computer readable instructions for use by or in connection with a computer. Computer program code embodied on a computer readable medium can be downloaded over a network from a remote computer (e.g., a server) or can be uploaded from a local computer or other device.

[0209] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure One one or more flowcharts and / or blocks Figure One means for functionally implementing the steps listed in one or more flowcharts and / or blocks

[0210] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. Figure One one or more flowcharts and / or blocks Figure One means for functionally implementing the steps listed in one or more flowcharts and / or blocks

[0211] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure One one or more flowcharts and / or blocks Figure One Figure One means for functionally implementing the steps listed in one or more flowcharts and / or blocks

[0212] In this document, the terms "comprise", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0213] While preferred embodiments have been described herein, changes and modifications can be suggested to one skilled in the art, and it is intended that the scope of the claims be governed only by the broadest interpretation of the language used in the claims.

[0214] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A simulation method applied to a peripheral region of a memory structure, the peripheral region including a capacitive array region and a non-capacitive array region, characterized in that, The simulation method comprises: obtaining a pre-established local simulation model of the capacitor array region, the local simulation model being used to represent first simulation parameters of the capacitor array region; the first simulation parameters comprising first theoretical parameters and first parasitic parameters of the capacitor array region; and the first parasitic parameters of the capacitor array region not being extracted; establishing a local parameter netlist of the non-capacitor array region, the local parameter netlist comprising second simulation parameters of the non-capacitor array region; the second simulation parameters comprising second theoretical parameters and second parasitic parameters of the non-capacitor array region; and the second parasitic parameters of the non-capacitor array region being extracted only, and the second theoretical parameters of the non-capacitor array region being combined to establish the local parameter netlist of the non-capacitor array region; based on the local simulation model and the local parameter netlist, establishing an overall parameter netlist of the peripheral region, the overall parameter netlist representing overall simulation parameters of the peripheral region, the overall simulation parameters comprising the first simulation parameters and the second simulation parameters; based on the overall parameter netlist, simulating the peripheral region.

2. The simulation method of claim 1, wherein, The establishment of the local parameter netlist of the non-capacitor array region comprises: constructing a local theoretical parameter netlist, the local theoretical parameter netlist comprising the second theoretical parameters; extracting the second parasitic parameters of the peripheral region based on a parasitic parameter extraction program to establish a local parasitic parameter netlist; based on the local theoretical parameter netlist and the local parasitic parameter netlist, establishing the local parameter netlist.

3. The simulation method of claim 2, wherein, The extraction of the second parasitic parameters of the peripheral region based on the parasitic parameter extraction program to establish the local parasitic parameter netlist comprises: in the process of extracting the second parasitic parameters, filtering a preset link in the parasitic parameter extraction program, the preset link being a verification link of the capacitor array region.

4. The simulation method of claim 1, wherein, The capacitor array region comprises a plurality of preset capacitor units, the preset capacitor units comprising a plurality of unit capacitors, the first theoretical parameters comprising first theoretical capacitors of the preset capacitor units, and the first parasitic parameters comprising parasitic resistances of the preset capacitor units.

5. The simulation method of claim 4, wherein, The local simulation model is established by: establishing a unit simulation model of the preset capacitor unit, the unit simulation model being used to represent the first theoretical capacitors of the preset capacitor unit; based on an arrangement mode of the preset capacitor units in the capacitor array region and the unit simulation model of each preset capacitor unit, obtaining a capacitor simulation model of the capacitor array region, the capacitor simulation model being used to represent the first theoretical capacitors of each preset capacitor unit and the arrangement mode of the preset capacitor units in the capacitor array region; based on the arrangement mode of the preset capacitor units, obtaining an arrangement direction of the preset capacitor units, and establishing a parasitic resistance equivalent test structure of a group of preset capacitor units arranged in the same arrangement direction; based on the parasitic resistance equivalent test structure, determining the parasitic resistances of each preset capacitor unit; The local simulation model is established based on the capacitance simulation model and the parasitic resistance of each of the preset capacitance units.

6. The simulation method of claim 5, wherein, The parasitic resistance equivalent test structure of the group of preset capacitance units arranged in the same direction comprises: A wire layer is established, and the wire layer is coupled to the lower electrodes of the preset capacitance units; A conductive layer is established, and the preset capacitance units are arranged in the conductive layer, and the conductive layer is coupled to the upper electrodes of the group of preset capacitance units arranged in the same direction in series with each other; The parasitic resistance equivalent test structure is established based on the wire layer and the conductive layer, and the wire layer of each of the preset capacitance units in the group of preset capacitance units is taken as an end point.

7. The simulation method of claim 5, wherein, The local simulation model is established based on the capacitance simulation model and the parasitic resistance of each of the preset capacitance units. The local simulation model is established based on the capacitance simulation model and the parasitic resistance of each of the preset capacitance units.

8. The emulation method of claim 1, wherein, The local simulation model comprises a first port related to the capacitance array region and a second port related to the non-capacitance array region, and the local parameter netlist comprises a third port related to the capacitance array region and a fourth port related to the non-capacitance array region, The overall parameter netlist of the peripheral region is established based on the local simulation model and the local parameter netlist, comprising: The overall parameter netlist is established by calling the first port, the second port, the third port and the fourth port.

9. An emulation device applied to a peripheral area of a memory structure, the peripheral area including a capacitor array area and a non-capacitor array area, characterized in that, The simulation device comprises: The acquisition module is configured to acquire a local simulation model of the capacitance array region, the local simulation model being used to represent first simulation parameters of the capacitance array region; the first simulation parameters comprise first theoretical parameters and first parasitic parameters of the capacitance array region; and the acquisition module does not extract the first parasitic parameters of the capacitance array region. The establishment module is configured to establish a local parameter netlist of the non-capacitance array region, the local parameter netlist comprising second simulation parameters of the non-capacitance array region; the second simulation parameters comprise second theoretical parameters and second parasitic parameters of the non-capacitance array region; and the establishment module is configured to only extract the second parasitic parameters of the non-capacitance array region and establish the local parameter netlist of the non-capacitance array region in combination with the second theoretical parameters of the non-capacitance array region. The simulation module is configured to simulate the peripheral region based on the overall parameter netlist. The establishment module is specifically configured to:

10. The emulation apparatus of claim 9 wherein, construct a local theoretical parameter netlist of the non-capacitance array region, the local theoretical parameter netlist comprising the second theoretical parameters; ​ extracting a second parasitic parameter of the peripheral region based on the parasitic parameter extraction procedure, and establishing a local parasitic parameter netlist; establishing the local parameter netlist based on the local theoretical parameter netlist and the local parasitic parameter netlist.

11. The emulation apparatus of claim 10, wherein, The establishing module is further configured to: filter a preset link in the parasitic parameter extraction procedure in the process of extracting the second parasitic parameter, the preset link being a verification link for the capacitor array region.

12. The emulation apparatus of claim 9 wherein, The capacitor array region includes a plurality of preset capacitor units, each of the preset capacitor units including a plurality of unit capacitors, the first theoretical parameter including a first theoretical capacitance of each of the preset capacitor units, and the first parasitic parameter including a parasitic resistance of each of the preset capacitor units.

13. The emulation apparatus of claim 9 wherein, The local simulation model includes a first port related to the capacitor array region and a second port related to the non-capacitor array region, and the local parameter netlist includes a third port related to the capacitor array region and a fourth port related to the non-capacitor array region. The establishing module is further configured to: invoke the first port, the second port, the third port, and the fourth port to establish the overall parameter netlist.

14. An emulation device applied to a peripheral area of a storage structure, the peripheral area including a capacitor array area and a non-capacitor array area, characterized by, The simulation device includes: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to perform the simulation method according to any one of claims 1 to 8.

15. A non-transitory computer-readable storage medium, comprising: When the instructions in the storage medium are executed by the processor of the simulation device, the simulation device is enabled to perform the simulation method according to any one of claims 1 to 8.

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