Signal generation circuit, method and semiconductor memory

Abstract

Embodiments of the present application disclose a signal generation circuit, method, and semiconductor memory, wherein the signal generation circuit includes: a clock module for receiving a flag signal and generating a clock signal; a control module for generating a control signal; the period of the clock signal and the target value represented by the control signal have opposite trends with process changes; a generation module connected to the clock module and the control module, respectively, for receiving the clock signal, the control signal, and the flag signal, and generating a target signal; when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level, and after the target signal maintains the fourth level for a target duration, it changes from the fourth level to the third level; the generation module is further used to determine the target duration based on the clock signal and the control signal.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a signal generation circuit, method and semiconductor memory. Background Art

[0002] Semiconductor memories may include volatile memories (such as dynamic random access memory or static random access memory) and non-volatile memories (such as flash memory, phase change memory, ferroelectric memory, magnetic memory, or resistive memory). Generally, volatile memories support high-speed random access and are often used as main memory in computing systems (such as personal computers, servers, or workstations).

[0003] During the semiconductor memory manufacturing process, differences in the position of the field-effect transistors (FETs) on the same wafer, or in the parameters of different wafer batches, result in different process corners for each manufactured semiconductor memory device. Consequently, the clock signal generated by the ring oscillator within the semiconductor memory device can vary with process variations, and the signal controlled by this clock signal can also vary with the process. Consequently, at different process corners, the signal controlled by this clock signal within different semiconductor memories can deviate from the expected value, even exceeding standard requirements. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a signal generation circuit, method, and semiconductor memory to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of the embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a signal generating circuit, the circuit comprising:

[0007] A clock module, configured to receive a flag signal and generate a clock signal;

[0008] A control module, configured to generate a control signal;

[0009] The period of the clock signal and the target value represented by the control signal have opposite trends in terms of process changes;

[0010] A generation module is connected to the clock module and the control module respectively, and is used to receive the clock signal, the control signal and the flag signal, and generate a target signal; when the flag signal changes from the first level to the second level, the target signal changes from the third level to the fourth level, and after the target signal maintains the fourth level for a target time, it changes from the fourth level to the third level; the generation module is also used to determine the target time according to the clock signal and the control signal.

[0011] In an optional embodiment, the generation module includes a counter; when the flag signal changes from the first level to the second level, the counter starts counting the clock signal, and when the count value reaches the target value represented by the control signal, controls the target signal to change from the fourth level to the third level.

[0012] In an optional implementation, the clock module includes a ring oscillator; when the flag signal changes from the first level to the second level, the ring oscillator generates the clock signal.

[0013] In an optional implementation, the first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level.

[0014] In an optional implementation, the flag signal is a check flag signal, and the check flag signal is used to indicate a parity check error or a redundancy check error.

[0015] In an optional embodiment, the period of the clock signal increases as the process changes; the target value represented by the control signal decreases as the process changes;

[0016] The process change is a change from the FF process corner to the SS process corner.

[0017] In an optional embodiment, the control module includes a ZQ calibrator and an operator; wherein,

[0018] The ZQ calibrator is used to perform a ZQ calibration operation and output a ZQ calibration code for calibrating the output impedance;

[0019] The operator is configured to receive the ZQ calibration code, divide the coefficient by the ZQ calibration code, and output the result as the control signal.

[0020] In an optional embodiment, the ZQ calibration code increases with process changes;

[0021] The process change is a change from an FF process angle to an SS process angle.

[0022] In a second aspect, an embodiment of the present application provides a signal generation method, the method comprising:

[0023] Receiving a flag signal through a clock module, generating a clock signal, and outputting the clock signal to a generating module;

[0024] Generate a control signal through the control module, and output the control signal to the generation module;

[0025] The period of the clock signal and the target value represented by the control signal have opposite trends in terms of process changes;

[0026] The generation module receives the clock signal, the control signal, and the flag signal, and generates a target signal; when the flag signal changes from the first level to the second level, the target signal changes from the third level to the fourth level, and after the target signal maintains the fourth level for a target duration, it changes from the fourth level to the third level; the target duration is determined by the generation module based on the clock signal and the control signal.

[0027] In an optional implementation, the receiving a flag signal through a clock module to generate a clock signal includes:

[0028] The ring oscillator receives the flag signal, and when the flag signal changes from the first level to the second level, the ring oscillator generates the clock signal.

[0029] In an optional embodiment, when the flag signal changes from the first level to the second level, the target signal changes from the third level to the fourth level, and after the target signal maintains the fourth level for a target time period, changes from the fourth level to the third level, includes:

[0030] When the flag signal changes from the first level to the second level, the clock signal is counted by a counter. When the count value reaches the target value represented by the control signal, the counter controls the target signal to change from the fourth level to the third level.

[0031] In an optional implementation, the first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level.

[0032] In an optional implementation, the flag signal is a check flag signal, and the check flag signal is used to indicate a parity check error or a redundancy check error.

[0033] In an optional embodiment, the period of the clock signal increases as the process changes; the target value represented by the control signal decreases as the process changes;

[0034] The process change is a change from the FF process corner to the SS process corner.

[0035] In an optional implementation, the generating, by the control module, a control signal for compensating for process variations of the clock signal includes:

[0036] Performing a ZQ calibration operation through a ZQ calibrator and outputting a ZQ calibration code for calibrating output impedance;

[0037] The operator receives the ZQ calibration code, divides the coefficient by the ZQ calibration code, and outputs the result as the control signal.

[0038] In an optional embodiment, the ZQ calibration code increases with process changes;

[0039] The process change is a change from an FF process angle to an SS process angle.

[0040] In a third aspect, an embodiment of the present application provides a semiconductor memory comprising a signal generating circuit as described in any one of the first aspects.

[0041] In an optional embodiment, the semiconductor memory is a dynamic random access memory DRAM chip.

[0042] In an optional embodiment, the dynamic random access memory DRAM chip complies with DDR4 memory specifications.

[0043] In the technical solution provided in this application, a clock module and a control module are configured in the signal generation circuit to generate a clock signal and a control signal. The period of the clock signal and the target value represented by the control signal have opposite trends over process variations. In this way, the target duration determined by the clock signal and the control signal is not affected by the process, thereby ensuring a stable pulse width of the target signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0045] Figure 1 Parity check alarm circuit for common DDR4 chips;

[0046] Figure 2 Schematic diagram of pulse width deviation of ALERT signal under different processes;

[0047] Figure 3 A schematic structural diagram of a signal generating circuit provided in an embodiment of the present application;

[0048] Figure 4 A graph showing the ZQ calibration code variation over the process provided in the embodiment of the present application;

[0049] Figure 5 A graph showing the trend of the clock signal period changing with the process according to an embodiment of the present application;

[0050] Figure 6 A graph showing the target duration versus process change trends provided in the embodiments of this application;

[0051] Figure 7 Schematic diagram of the pulse width of the ALERT signal under different processes;

[0052] Figure 8 A schematic diagram of the implementation flow of a signal generation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0054] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0055] In addition, the accompanying drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0056] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to actual circumstances.

[0057] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0058] In the SPEC (Specification) of the DDR4 chip, the pulse width (pulse width) tPAR_ALERT_PW of the ALERT signal output by the command / address bus parity alert system (C / A Parity Alert) is specified to be between 60ns and 120ns. Figure 1 This is a common parity alarm circuit for DDR4 chips. In this circuit design, after a parity error occurs, a PAR_Error_Flag signal is output to enable the ring oscillator, causing it to generate a clock signal CLK with a fixed period of T'. The number of counter stages, N', is then determined based on the SPEC requirement of tPAR_ALERT_PW. With this circuit design, the parity alarm circuit outputs a logic 1 when it receives the PAR_Error_Flag signal, and then outputs a logic 0 after the counter completes counting. The final result is that the pulse width of the output ALERT signal is tPAR_ALERT_PW = T'×N', where T' is the period of the clock signal generated by the ring oscillator and N' is the number of counter stages.

[0059] However, while the pulse width of the ALERT signal output by this circuit design does not change with the chip's operating frequency, it does vary with the process. During semiconductor device manufacturing, variations in field-effect transistor (FET) parameters can occur due to differences in position on the same wafer or between wafer batches. This variation is called process corner, which is generally categorized as slow-slow (SS), typical-typical (TT), and fast-fast (FF). Figure 2 is the pulse width deviation of the ALERT signal under different process angles, such as Figure 2As shown, when the process variation is particularly large, the period T' of the clock signal CLK generated by the ring oscillator will vary greatly. For example, at the FF process angle, the period T' of the clock signal CLK generated by the ring oscillator is smaller, while at the SS process angle, the period T' of the clock signal CLK generated by the ring oscillator is larger. With the amplification of the counter stage N', the pulse width tPAR_ALERT_PW of the ALERT signal at the SS process angle can easily exceed the range of 60ns-120ns specified by SPEC, and the pulse width tPAR_ALERT_PW of the ALERT signal at the FF process can also easily be smaller than the range of 60ns-120ns specified by SPEC.

[0060] To this end, the following technical solutions of the embodiments of the present application are proposed.

[0061] The embodiment of the present application provides a signal generating circuit, Figure 3 A schematic diagram of a signal generating circuit according to an embodiment of the present invention is shown in FIG. Figure 3 As shown, the circuit includes:

[0062] The clock module 310 is configured to receive a flag signal and generate a clock signal;

[0063] A control module 320, configured to generate a control signal;

[0064] The period of the clock signal and the target value represented by the control signal have opposite trends in terms of process changes;

[0065] The generation module 330 is connected to the clock module 310 and the control module 320 respectively, and is used to receive the clock signal, the control signal and the flag signal, and generate a target signal; when the flag signal changes from the first level to the second level, the target signal changes from the third level to the fourth level, and after the target signal maintains the fourth level for a target period of time, it changes from the fourth level to the third level; the generation module 330 is also used to determine the target duration based on the clock signal and the control signal.

[0066] Here, the target duration for which the target signal output by the generating module 330 is maintained at the fourth level is the pulse width of the target signal output by the generating module 330 .

[0067] The target value represented by the control signal in the embodiment of the present application and the period of the clock signal have opposite trends in change with the process, so that the target duration determined by the clock signal and the control signal will not be affected by the process, thereby making the pulse width of the target signal stable.

[0068] Furthermore, in the embodiment of the present application, the pulse width of the target signal is adjusted by the clock signal and the control signal to control the pulse width of the target signal within a certain range, weaken or eliminate the change of the pulse width of the target signal with the process, and stabilize the pulse width of the target signal.

[0069] In one embodiment of the present application, a signal generation circuit is provided for generating a target signal and adjusting the pulse width of the target signal to stabilize it within a certain range. The signal generation circuit can be widely used in semiconductor memory devices such as DDR2, DDR3, DDR4, LPDDR2, and LPDDR3, which are not listed here.

[0070] The clock module 310 provided in this embodiment of the application includes a ring oscillator; when the flag signal changes from the first level to the second level, the ring oscillator generates the clock signal. In this embodiment of the application, the ring oscillator is used to generate the clock signal as the internal clock signal.

[0071] In this embodiment of the present application, the control module 320 includes a ZQ calibrator 321 and an operator 322. The ZQ calibrator 321 is configured to perform a ZQ calibration operation and output a ZQ calibration code for calibrating the output impedance. The operator 322 is configured to receive the ZQ calibration code and divide a coefficient by the ZQ calibration code to output the result as the control signal. In this embodiment of the present application, the control signal is obtained by dividing the coefficient by the ZQ calibration code.

[0072] DRAM memory chips are equipped with output driver circuits for outputting data signals when the DRAM memory performs a read operation. The output impedance of the output driver circuit affects the quality of the output data signal. Furthermore, on-die termination (ODT) resistors are typically also provided within the DRAM memory chip to reduce signal reflections at the terminals, thereby achieving a higher memory clock speed. Because the output impedance and ODT resistor values vary with factors such as the manufacturing process and the application environment, such as voltage and temperature, ZQ calibration is required to calibrate the output impedance and ODT resistors. Specifically, a port, namely a ZQ port, is provided on the DRAM memory. One end of the ZQ port is connected to the memory chip, and the other end is connected to an external resistor, namely a 240 ohm low-tolerance reference resistor. The output impedance and ODT resistor are verified using an on-chip ZQ calibrator. When the system issues a ZQ calibration command, the on-chip ZQ calibrator calibrates the output impedance and ODT resistor according to the specified ZQ calibration cycle.

[0073] The ZQ calibrator can perform a ZQ calibration operation in response to a ZQ calibration enable signal to generate a ZQ calibration code. For example, if the ZQ calibration enable signal is enabled, the ZQ calibrator can perform a ZQ calibration operation to generate a ZQ calibration code. The ZQ calibration code is used to calibrate the output impedance and ODT resistance, thereby matching the impedance between the memory and the external device and improving the signal quality when reading and writing data. Since the ZQ calibration is performed on the output impedance and ODT resistance under the current chip process, the ZQ calibration code can reflect information about the current process.

[0074] Since the ZQ calibration code increases with the change of process, and the control signal is obtained by dividing the ZQ calibration code by a coefficient, the target value represented by the control signal decreases with the change of process. And the period of the clock signal increases with the change of process. Specifically, different chips on the same wafer or the same batch of wafers may have different process angles, so that the frequency / period of the clock signals of these chips with different process angles will be different, and the ZQ calibration code used to calibrate the output impedance and ODT resistance will also be different. In the embodiment of the present application, this difference caused by different process angles is referred to as variation with process. In this way, the target duration determined based on the target value represented by the control signal and the period of the clock signal will not change significantly with the change of process. Among them, the change in the process is the change from the FF process angle to the SS process angle.

[0075] In an embodiment of the present application, the pulse width of the target signal is adjusted by utilizing the variation of the ZQ calibration code with the process and the variation of the clock signal with the process, so as to control the pulse width of the target signal within a certain range, thereby weakening or eliminating the variation of the pulse width of the target signal with the process and stabilizing the pulse width of the target signal.

[0076] In a specific embodiment, when the signal generating circuit is applied to a DDR4 chip, the ZQ calibrator 321 is used to output a ZQ calibration code M; the operator 322 is used to receive the ZQ calibration code M and divide the coefficient N by the ZQ calibration code M to output as the control signal. Figure 4 A trend diagram of the ZQ calibration code changing with the process is provided in an embodiment of the present application. Since the ZQ calibration code M is used to calibrate the output impedance and ODT resistance, the ZQ calibration code M increases with the change of the process, so that the trend of the target value represented by the control signal changing with the process is opposite to the trend of the period of the clock signal changing with the process. Therefore, the control signal generated based on the ZQ calibration code M can effectively compensate for the change of the pulse width of the target signal with the process.

[0077] Here, the coefficient N is divided by the ZQ calibration code M to convert the ZQ calibration code M into a signal that decreases with process variations, thereby making the target value represented by the control signal vary with the process trend opposite to the process variation trend of the clock signal period. In practical applications, the corresponding coefficient N can be selected based on the actual pulse width of the target signal. Here, the number of counter stages is the target value N / M represented by the control signal. In the embodiment of the present application, the ZQ calibration code M increases with process variations, thereby decreasing the target value N / M represented by the control signal with process variations; the process variation is the change from the FF process angle to the SS process angle.

[0078] Here, the control signal is a counter stage selection signal of the counter. The counter can determine its stage number according to the control signal, and thus perform counting based on the stage number.

[0079] In the embodiment of the present application, the flag signal is a check flag signal, and the check flag signal is used to represent a parity check error or a redundancy check error.

[0080] In an embodiment of the present application, the generation module 330 includes a counter; when the flag signal changes from the first level to the second level, the counter begins counting the clock signal, and when the count value reaches the target value represented by the control signal, the target signal is controlled to change from the fourth level to the third level. When the flag signal is used to represent a parity check error, after a parity check error occurs, a flag signal PAR_Error_Flag is output, and the flag signal PAR_Error_Flag is active high. Therefore, when the flag signal PAR_Error_Flag changes from a low level to a high level, the generation module controls the target signal to change from a low level to a high level. Simultaneously, the counter begins counting the clock signal, and when the count value reaches the target value represented by the control signal, the target signal is controlled to change from a high level to a low level.

[0081] In some embodiments, the flag signal is used to characterize a parity error. After a parity error occurs, a parity flag signal PAR_Error_Flag is output. The target signal generated by the generation module is a parity alarm signal ALERT. Thus, the signal generation circuit provided in the embodiments of the present application can adjust the pulse width tPAR_ALERT_PW of the parity alarm signal to control the pulse width tPAR_ALERT_PW of the parity alarm signal within a certain range, reducing or eliminating process variations in the pulse width tPAR_ALERT_PW of the parity alarm signal, and stabilizing the pulse width tPAR_ALERT_PW of the parity alarm signal within the range specified by the SPEC.

[0082] It should be noted that the ALERT signal here is not the signal that is ultimately output through the alert_n pin. The ALERT signal needs to pass through several inverters or output buffer circuits before being output to the chip's alert_n pin. In a specific example, the ALERT signal can be output to the chip's alert_n pin after passing through an odd number of inverters, thereby ensuring that the alert_n signal output by the alert_n pin is active low.

[0083] Here, the number of stages of the counter is the target value N / M represented by the control signal. If the period of the clock signal is T, then the target duration (pulse width of the target signal) is T×N / M. N / M and T have opposite trends with process changes. Therefore, the target duration (pulse width of the target signal) hardly changes with process changes. In other words, the target duration (pulse width of the target signal) is stable within the range specified by SPEC under different processes. The process change is the change from the FF process corner to the SS process corner.

[0084] Figure 5 The following is a graph showing the trend of the clock signal period changing with the process according to the embodiment of the present application: Figure 6 This is a graph showing the target length changing with the process provided in the embodiments of the present application. Figure 5 The vertical axis is the period of the clock signal, and the horizontal axis is the process; Figure 6 The vertical axis is the target duration, and the horizontal axis is the process. Figure 4 、 Figure 5 and Figure 6 As shown, the period T of the clock signal increases with the change of the process, and the ZQ calibration code M increases with the change of the process, so that the target value N / M represented by the control signal decreases with the change of the process. Then, the target duration T×N / M obtained based on the period T of the clock signal and the target value N / M represented by the control signal can also be stable within the range specified by SPEC in the case of process changes.

[0085] Figure 7 Schematic diagram of the pulse width of the ALERT signal under different processes. Figure 7 The ALERT signal in is generated by the signal generating circuit provided in the embodiment of the present application, such as Figure 7 As shown, at the FF process angle, the period T of the clock signal CLK generated by the ring oscillator is small, but the target value N / M (number of counter stages) represented by the control signal is large. At the SS process angle, the period T of the clock signal CLK generated by the ring oscillator is large, but the target value N / M (number of counter stages) represented by the control signal is small. Therefore, the pulse width of the final output ALERT signal does not vary much at both the FF and SS process angles. In other words, through the combined control of the clock signal and the control signal, the pulse width of the target signal can be controlled within a certain range, reducing or eliminating the pulse width variation of the target signal with the process, and stabilizing the pulse width of the target signal within the range specified by the SPEC.

[0086] In an embodiment of the present application, the first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level. Then when the flag signal changes from a low level to a high level, the target signal changes from a low level to a high level, and after the target signal maintains the high level for the target duration, it changes from a high level to a low level. Here, the flag signal is a check flag signal, and the check flag signal is valid when it is at a high level. When the check flag signal is at a high level, it indicates that a check error has occurred; when the check flag signal is at a low level, it indicates that no check error has occurred. In an embodiment of the present application, the target duration is determined based on the period of the clock signal and the target value represented by the control signal, and the period of the clock signal and the target value represented by the control signal have opposite trends with the process, so that the target duration (pulse width of the target signal) hardly changes with the process. In other words, the target duration (pulse width of the target signal) remains stable under different processes.

[0087] Based on the same technical concept as the aforementioned signal generating circuit, the embodiment of the present application provides a signal generating method. Figure 8 A schematic diagram of the implementation flow of a signal generation method provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the method mainly includes the following steps:

[0088] Step 810: Receive a flag signal through a clock module, generate a clock signal, and output the clock signal to a generation module.

[0089] Step 820: Generate a control signal through the control module and output the control signal to the generation module; the period of the clock signal and the target value represented by the control signal have opposite trends in process changes.

[0090] Step 830: The generation module receives the clock signal, the control signal, and the flag signal, and generates a target signal; when the flag signal changes from the first level to the second level, the target signal changes from the third level to the fourth level, and after the target signal maintains the fourth level for a target duration, it changes from the fourth level to the third level; the target duration is determined by the generation module based on the clock signal and the control signal.

[0091] Here, the target duration for which the target signal output by the generating module is maintained at the fourth level is the pulse width of the target signal output by the generating module.

[0092] In the embodiment of the present application, step 810 includes: when the flag signal changes from the first level to the second level, the ring oscillator generates the clock signal. In the embodiment of the present application, the ring oscillator is used to generate the clock signal as the internal clock signal.

[0093] The target value represented by the control signal in the embodiment of the present application and the period of the clock signal have opposite trends in change with the process, so that the target duration determined by the clock signal and the control signal will not be affected by the process, thereby making the pulse width of the target signal stable.

[0094] Furthermore, in the embodiment of the present application, the pulse width of the target signal is adjusted by the clock signal and the control signal to control the pulse width of the target signal within a certain range, weaken or eliminate the change of the pulse width of the target signal with the process, and stabilize the pulse width of the target signal.

[0095] In the embodiment of the present application, the flag signal is a check flag signal, and the check flag signal is used to represent a parity check error or a redundancy check error.

[0096] In the embodiment of the present application, step 820 includes: performing a ZQ calibration operation through a ZQ calibrator and outputting a ZQ calibration code for calibrating the output impedance; an operator receiving the ZQ calibration code and dividing a coefficient by the ZQ calibration code to output as the control signal.

[0097] Because the ZQ calibration code increases with process variations, and the control signal is obtained by dividing the ZQ calibration code by a coefficient, the target value represented by the control signal decreases with process variations. Furthermore, the period of the clock signal increases with process variations. Thus, the target duration determined based on the target value represented by the control signal and the period of the clock signal does not change significantly with process variations. The process variation is the change from the FF process corner to the SS process corner.

[0098] Here, the coefficient N is divided by the ZQ calibration code M to convert the ZQ calibration code M into a signal that decreases with process variations, thereby making the target value represented by the control signal vary with the process trend opposite to the process variation trend of the clock signal period. In practical applications, the corresponding coefficient N can be selected based on the actual pulse width of the target signal. Here, the number of counter stages is the target value N / M represented by the control signal. In the embodiment of the present application, the ZQ calibration code M increases with process variations, thereby decreasing the target value N / M represented by the control signal with process variations; the process variation is the change from the FF process angle to the SS process angle.

[0099] In an embodiment of the present application, when the flag signal changes from the first level to the second level, the target signal changes from the third level to the fourth level, and after the target signal maintains the fourth level for a target period of time, it changes from the fourth level to the third level, including: when the flag signal changes from the first level to the second level, the clock signal is counted by a counter, and when the count value reaches the target value represented by the control signal, the counter controls the target signal to change from the fourth level to the third level.

[0100] Here, the number of counter stages is the target value N / M represented by the control signal. If the period of the clock signal is T, then the target duration (the pulse width of the target signal) is T×N / M. N / M and T have opposite trends with process variations. Therefore, the target duration (the pulse width of the target signal) hardly changes with process variations. In other words, the target duration (the pulse width of the target signal) remains stable under different process conditions.

[0101] In the embodiment of the present application, the first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level.

[0102] The embodiment of the present application also provides a semiconductor memory, including the aforementioned signal generation circuit. The semiconductor memory referred to in the present application includes but is not limited to dynamic random access memory, etc. The semiconductor memory can adopt the signal generation circuit of the present application to adjust the pulse width of the target signal generated by it, so that the pulse width of the target signal is not affected by the process and is stable within a certain range. In other words, the semiconductor memory can adopt the signal generation circuit of the present application to adjust the pulse width of the target signal generated by it, so that the pulse width of the target signal is not affected by the process angle and is stable within a certain range.

[0103] In the embodiment of the present application, the dynamic random access memory DRAM chip complies with the DDR4 memory specification.

[0104] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0105] The features disclosed in the several device embodiments provided in this application can be arbitrarily combined without conflict to obtain new device embodiments.

[0106] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A signal generating circuit, characterized in that: The circuit comprises: A clock module, configured to receive a flag signal and generate a clock signal; A control module, configured to generate a control signal; The period of the clock signal and the target value represented by the control signal have opposite trends in terms of process changes; A generation module is connected to the clock module and the control module respectively, and is used to receive the clock signal, the control signal and the flag signal, and generate a target signal; when the flag signal changes from the first level to the second level, the target signal changes from the third level to the fourth level, and after the target signal maintains the fourth level for a target time, it changes from the fourth level to the third level; the generation module is also used to determine the target time according to the clock signal and the control signal.

2. The signal generating circuit according to claim 1, wherein: The generation module includes a counter; when the flag signal changes from the first level to the second level, the counter starts counting the clock signal, and when the count value reaches the target value represented by the control signal, controls the target signal to change from the fourth level to the third level.

3. The signal generating circuit according to claim 1, wherein: The clock module includes a ring oscillator; when the flag signal changes from the first level to the second level, the ring oscillator generates the clock signal.

4. The signal generating circuit according to any one of claims 1 to 3, characterized in that: The first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level.

5. The signal generating circuit according to claim 1, wherein: The flag signal is a check flag signal, and the check flag signal is used to indicate a parity check error or a redundancy check error.

6. The signal generating circuit according to claim 1, wherein: The period of the clock signal increases as the process changes; the target value represented by the control signal decreases as the process changes; The process change is a change from the FF process corner to the SS process corner.

7. The signal generating circuit according to claim 1, wherein: The control module includes a ZQ calibrator and an operator; wherein, The ZQ calibrator is used to perform a ZQ calibration operation and output a ZQ calibration code for calibrating the output impedance; The operator is configured to receive the ZQ calibration code, divide the coefficient by the ZQ calibration code, and output the result as the control signal.

8. The signal generating circuit according to claim 7, wherein: The ZQ calibration code increases with the change of the process; The process change is a change from an FF process angle to an SS process angle.

9. A signal generation method, characterized in that: The method comprises: Receiving a flag signal through a clock module, generating a clock signal, and outputting the clock signal to a generating module; Generate a control signal through the control module, and output the control signal to the generation module; The period of the clock signal and the target value represented by the control signal have opposite trends in terms of process changes; The generation module receives the clock signal, the control signal, and the flag signal, and generates a target signal; when the flag signal changes from the first level to the second level, the target signal changes from the third level to the fourth level, and after the target signal maintains the fourth level for a target duration, it changes from the fourth level to the third level; the target duration is determined by the generation module based on the clock signal and the control signal.

10. The signal generating method according to claim 9, characterized in that: The step of receiving a flag signal through a clock module and generating a clock signal includes: The ring oscillator receives the flag signal, and when the flag signal changes from the first level to the second level, the ring oscillator generates the clock signal.

11. The signal generating method according to claim 9, wherein: When the flag signal changes from the first level to the second level, the target signal changes from the third level to the fourth level, and after the target signal maintains the fourth level for a target time period, the target signal changes from the fourth level to the third level, including: When the flag signal changes from the first level to the second level, the clock signal is counted by a counter. When the count value reaches the target value represented by the control signal, the counter controls the target signal to change from the fourth level to the third level.

12. The signal generating method according to any one of claims 9 to 11, characterized in that: The first level is a low level, the second level is a high level, the third level is a low level, and the fourth level is a high level.

13. The signal generating method according to claim 9, wherein: The flag signal is a check flag signal, and the check flag signal is used to indicate a parity check error or a redundancy check error.

14. The signal generating method according to claim 9, characterized in that: The period of the clock signal increases as the process changes; the target value represented by the control signal decreases as the process changes; The process change is a change from the FF process corner to the SS process corner.

15. The signal generating method according to claim 9, characterized in that: Generating, by a control module, a control signal for compensating for process variations of the clock signal includes: Performing a ZQ calibration operation through a ZQ calibrator and outputting a ZQ calibration code for calibrating output impedance; The operator receives the ZQ calibration code, divides the coefficient by the ZQ calibration code, and outputs the result as the control signal.

16. The signal generating method according to claim 15, characterized in that: The ZQ calibration code increases with the change of the process; The process change is a change from an FF process angle to an SS process angle.

17. A semiconductor memory, characterized in that: The method comprises the signal generating circuit according to any one of claims 1 to 8.

18. The semiconductor memory according to claim 17, wherein: The semiconductor memory is a dynamic random access memory DRAM chip.

19. The semiconductor memory according to claim 18, wherein The dynamic random access memory DRAM chip complies with the DDR4 memory specification.

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