A method for electrical detection during packaging

Abstract

The application discloses a kind of electrical detection methods in packaging process, comprising: forming circuit on the active surface of semiconductor wafer, there are multiple semiconductor chips on semiconductor wafer;Forming re-formation passivation layer one on effective chip, forming re-formation passivation layer two on ineffective chip;Re-formation passivation layer one forms opening one at the electrode of effective chip, and re-formation passivation layer two forms opening two at the electrode of ineffective chip;Forming rewiring metal layer one on re-formation passivation layer one, forming metal rewiring one and metal rewiring two on re-formation passivation layer two, and forming metal rewiring electrode one and metal rewiring electrode two;Implementing leakage current detection and contact resistance detection;Forming re-formation passivation layer three on rewiring metal layer one;Forming rewiring metal layer two on re-formation passivation layer three, forming metal wiring on ineffective chip;Delivery.The application can make up the deficiency of optical detection in wafer level packaging process.

Description

Technical Field

[0001] This invention relates to the field of electrical testing methods, and more specifically to an electrical testing method during the packaging process. Background Technology

[0002] In recent years, driven by the combined demands for thinner and smaller consumer electronics and advancements in front-end wafer manufacturing processes, there is a growing need for semiconductor devices to have smaller individual chip package sizes. Wafer-level packaging technology effectively meets this requirement. However, during the wafer-level packaging process, only optical visual inspections are typically performed on the chip surface quality. Electrical testing directly related to the wafer-level packaging process is not conducted. If anomalies are found that are not detected by existing optical inspection methods, they can only be discovered during wafer-level electrical testing after packaging is complete. This leads to a significant impact on the affected batch during product anomaly investigations.

[0003] In its existing wafer-level packaging and testing process, the re-passivation layer forms an opening near the effective chip electrode. In this process, if a process anomaly occurs, such as developer bubbles, causing impurities within the opening... Figure 1 The organic film shown is relatively easy to detect with existing optical detection technology when it is thin and non-uniform and has colored diffraction fringes. However, when the organic film is thick or relatively uniform, existing optical detection technology has difficulty detecting this anomaly. It is only discovered when the effective chip test after wafer-level packaging finds high impedance or open circuit. Furthermore, existing technology has optical inspection to check whether there is metal residue between multiple redistribution metal layers. However, metal residue is at the atomic level and cannot be detected by existing optical technology when it is hidden in the reconstructed passivation layer. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide an electrical detection method in the packaging process, which can make up for the shortcomings of optical detection in wafer-level packaging process.

[0005] The technical solution provided by this invention to solve the above problems is: an electrical detection method during the packaging process, the method comprising the following steps,

[0006] After the circuit is formed on the active side of the semiconductor wafer, there are electrodes and a passivation layer on the surface. There are multiple semiconductor wafers on the semiconductor wafer, including active chips and inactive chips.

[0007] On the effective chip, a reconstructed passivation layer one is formed, and on the ineffective chip, a reconstructed passivation layer two is formed.

[0008] Reconstructed passivation layer one forms opening one at the electrode of the effective chip, and reconstructed passivation layer two forms opening two at the electrode of the ineffective chip.

[0009] A redistribution metal layer 1 is formed on the reconstructed passivation layer 1, and metal redistribution layer 1 and metal redistribution layer 2 are formed on the reconstructed passivation layer 2, and corresponding metal redistribution electrode 1 and metal redistribution electrode 2 are formed.

[0010] Leakage current detection is performed on a pair of electrodes of the first metal rewiring electrode, and contact resistance detection is performed on a pair of electrodes of the second metal rewiring electrode.

[0011] After passing the inspection, a reconstructed passivation layer three is formed on the rewiring metal layer one.

[0012] A second redistribution metal layer is formed on the third reconstructed passivation layer, and metal wiring is formed on the invalid chip.

[0013] Effective chips undergo wafer-level electrical performance testing;

[0014] Through thinning, back-side protection treatment, and cutting, qualified electrical chips are packaged and shipped.

[0015] Preferably, the regenerated passivation layer three has corresponding openings on the metal redistribution electrode one and the metal redistribution electrode two.

[0016] Preferably, the regenerated passivation layer is formed on a semiconductor wafer by a process of coating, exposure, development, post-development inspection, and curing.

[0017] Preferably, the reconstructed passivation layer II is formed on a semiconductor wafer by a process of coating, exposure, development, post-development inspection, and curing.

[0018] Preferably, the reconstituted passivation layer is formed by a method of coating, exposure, development and curing.

[0019] Preferably, a pair of metal rewiring electrodes can be used to test whether there is leakage current or short circuit between multiple metal rewirings.

[0020] Preferably, the presence of organic film residue in the opening can be detected between the other pair of metal redistribution electrodes, which may cause abnormalities such as high contact resistance or even open circuit.

[0021] Preferably, after forming metal wiring on the invalid chip, wafer-level electrical performance testing is required on the valid chip.

[0022] Compared with the prior art, the advantages of the present invention are: the present invention can make up for the lack of optical detection in the wafer-level packaging process. By forming a redistribution metal layer one on the reconstructed passivation layer one, forming metal redistribution one and metal redistribution two on the reconstructed passivation layer two, and forming corresponding metal redistribution electrode one and metal redistribution electrode two, the inter-line leakage current and contact resistance and other electrical properties of the redistribution in the wafer-level packaging process can be monitored and fed back in a timely manner. Attached Figure Description

[0023] The accompanying drawings, which are provided to further illustrate the invention and constitute a part of this invention, are illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention.

[0024] Figure 1 This is a flowchart of the present invention.

[0025] Figure 2 This is a side view of the packaging structure of the present invention;

[0026] Figure 3 This is a top view of the packaging structure of the present invention.

[0027] Figure labels: 101, semiconductor wafer; 102, electrode; 102a, invalid chip electrode; 103, passivation layer; 201, reconstructed passivation layer one; 201a, reconstructed passivation layer two; 202, opening one; 202a, opening two; 203X, organic film; 301a, metal redistribution one; 302a, metal redistribution electrode one; 303a, metal redistribution two; 304a, metal redistribution electrode two; 305, redistribution metal layer one; 401, reconstructed passivation layer three; 501, redistribution metal layer two; 502, metal wiring. Detailed Implementation

[0028] The following will describe in detail the implementation of the present invention with reference to the accompanying drawings and embodiments, so that the process of how the present invention uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0029] In the description of this invention, it should be noted that the directional terms such as "center", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", and "counterclockwise" indicate the orientation and positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. They should not be construed as limiting the specific protection scope of this invention.

[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features. Thus, the use of "first" and "second" to define a feature may explicitly or implicitly include one or more of that feature, and in the description of this invention, "a number" means two or more, unless otherwise explicitly specified.

[0031] In this invention, unless otherwise explicitly specified and limited, the terms "assembly," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can also refer to a mechanical connection; they can refer to a direct connection or a connection through an intermediate medium; or they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0032] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0033] It should also be understood that the terminology used in this specification of embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of the invention. As used in this specification of embodiments of the invention and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0034] An electrical detection method during the packaging process, the method comprising the following steps:

[0035] After the circuit is formed on the active side of the semiconductor wafer 101, there are electrodes and a passivation layer 103 on the surface. There are multiple semiconductor wafers on the semiconductor wafer, including active chips and inactive chips.

[0036] It should be noted that a semiconductor wafer contains multiple semiconductor chips. The chips within 3mm of the edge are invalid, while the chips outside 3mm are mostly valid. Some wafers are also used to manufacture identification chips.

[0037] On the valid chip, a reconstructed passivation layer is formed by coating, exposure, development, post-development inspection and curing methods to form reconstructed passivation layer 201. On the invalid chip, a reconstructed passivation layer 201a is formed.

[0038] Reconstructed passivation layer 1 201 forms an opening 202 at the electrode of the effective chip, and reconstructed passivation layer 201a forms an opening 202a at the electrode of the ineffective chip (i.e., ineffective chip electrode 102a).

[0039] A redistribution metal layer 305 is formed on the effective chip through sputtering, photolithography and electroplating processes on the reconstructed passivation layer 1. Metal redistribution layer 301a and metal redistribution layer 303a are formed on the reconstructed passivation layer 201a, and corresponding metal redistribution electrode 302a and metal redistribution electrode 304a are formed.

[0040] Leakage current detection is performed on a pair of electrodes of metal redistribution electrode 1 302a, and contact resistance detection is performed on a pair of electrodes of metal redistribution electrode 2 304a.

[0041] Among them, the pair of metal redistribution electrodes (302a) can test whether there is leakage current or short circuit between multiple metal redistribution electrodes (301a); the pair of metal redistribution electrodes (304a) can test whether there is organic film residue in the opening (202a) causing abnormalities such as high contact resistance or even open circuit.

[0042] After passing the inspection, a reconstructed passivation layer 401 is formed on the rewiring metal layer 305.

[0043] A redistribution metal layer 501 is formed on the reconstructed passivation layer 3 401, and a metal wiring 502 is formed on the invalid chip;

[0044] Effective chips undergo wafer-level electrical performance testing;

[0045] Through thinning, back-side protection treatment, and cutting, qualified electrical chips are packaged and shipped.

[0046] Typical electrical performance defects related to the wafer-level packaging process include open / short circuit defects, high contact resistance defects, and excessive leakage current defects. Open circuits and high contact resistance can be addressed through… Figure 2 Impedance monitoring between a pair of metal redistribution electrodes revealed that electroplating short circuits and leakage currents could be detected through... Figure 2 The circuit between the other pair of metal redistribution electrodes was monitored.

[0047] This invention integrates a set of rewiring devices on the chip that can test leakage current and impedance, thereby achieving the purpose of monitoring electrical performance in wafer-level packaging processes.

[0048] The above description only illustrates the preferred embodiments of the present invention and should not be construed as limiting the scope of the claims. The present invention is not limited to the above embodiments, and variations in its specific structure are permitted. All modifications made within the scope of the independent claims of this invention are also within the scope of protection of this invention.

Claims

1. A method for electrical testing during packaging, characterized by: The method comprises the following steps, An electrode and a passivation layer (103) are formed on the active surface of a semiconductor wafer (101), and the semiconductor wafer comprises a plurality of semiconductor chips, including effective chips outside 3mm from the edge and ineffective chips inside 3mm from the edge; A first reformed passivation layer (201) is formed on the effective chips, and a second reformed passivation layer (201a) is formed on the ineffective chips; The first reformed passivation layer (201) forms an opening one (202) at the electrode of the effective chip, and the second reformed passivation layer (201a) forms an opening two (202a) at the electrode of the ineffective chip; A first rewire metal layer (305) is formed on the first reformed passivation layer, a metal rewire one (301a) and a metal rewire two (303a) are formed on the second reformed passivation layer (201a), and a corresponding metal rewire electrode one (302a) and a metal rewire electrode two (304a) are formed; A pair of electrodes of the metal rewire electrode one (302a) is subjected to leakage current detection, and a pair of electrodes of the metal rewire electrode two (304a) is subjected to contact resistance detection; After the detection is qualified, a third reformed passivation layer (401) is formed on the first rewire metal layer (305); A second rewire metal layer (501) is formed on the third reformed passivation layer (401), and a metal wire (502) is formed on the ineffective chip; The effective chips with qualified electrical properties are packaged and sold through thinning, back protection treatment, cutting and packaging; The third reformed passivation layer (401) has corresponding openings on the metal rewire electrode one (302a) and the metal rewire electrode two (304a); The first reformed passivation layer (201) is formed on the semiconductor wafer (101) by the method of coating, exposing, developing, developing inspection and curing; The second reformed passivation layer (201a) is formed on the semiconductor wafer (101) by the method of coating, exposing, developing, developing inspection and curing; The third reformed passivation layer (401) is formed by the method of coating, exposing, developing and curing; Whether there is leakage current or circuit short circuit between a plurality of metal rewire ones (301a) can be tested between a pair of metal rewire electrode ones (302a); In addition, whether there is excessive contact resistance or circuit open caused by residual organic film in the opening two (202a) can be tested between another pair of metal rewire electrode twos (304a); After the metal wire (502) is formed on the ineffective chip, wafer-level electrical performance test needs to be performed on the effective chip; The first rewire metal layer (305) is formed on the effective chip by sputtering, photolithography and electroplating process steps on the first reformed passivation layer (201).

Images