Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure, including: forming a plurality of capacitor holes on a substrate, with the bottom end of the capacitor holes exposing a part of the substrate; forming a lower electrode layer on the surface of the capacitor holes; forming a dielectric layer continuously covering the surface of the lower electrode layer on the surface of the lower electrode layer; continuously covering a first upper electrode layer on the surface of the dielectric layer through a first film forming process; forming a second upper electrode layer continuously covering the surface of the first upper electrode layer in the circumferential direction of the capacitor holes through a second film forming process, and simultaneously forming a second upper electrode layer discontinuously covering the surface of the first upper electrode layer in the axial direction of the capacitor holes. In the present disclosure, the cross-section and longitudinal section of the second upper electrode layer formed in the capacitor holes are both discontinuous sections, reducing capacitor leakage and improving the reliability of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] DRAM (Dynamic Random Access Memory) has small volume, high integration, and low power consumption. At the same time, it is faster than all ROMs (Read-Only Memories). As the integration increases, the characteristic size and plate area of the capacitor continuously decrease. Therefore, it is necessary to use thinner and / or higher dielectric constant dielectric materials to increase the capacitance density. As the size of DRAM gradually decreases, it is necessary to further ensure that the capacitor has sufficiently low leakage current while ensuring a sufficiently large capacitance value. Summary of the Invention

[0003] Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure. The following is an overview of the subject matter described in detail in the present disclosure. This overview is not intended to limit the scope of protection of the claims.

[0004] According to a first aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a semiconductor structure, including:

[0005] Forming a plurality of capacitor holes on a substrate, with the bottom end of the capacitor holes exposing a part of the substrate;

[0006] Forming a lower electrode layer on the surface of the capacitor holes;

[0007] Forming a dielectric layer on the surface of the lower electrode layer, continuously covering the surface of the lower electrode layer;

[0008] Continuously covering a first upper electrode layer on the surface of the dielectric layer through a first film-forming process;

[0009] Forming a second upper electrode layer on the surface of the first upper electrode layer by a second film-forming process, continuously covering the surface of the first upper electrode layer in the circumferential direction of the capacitor holes, and discontinuously covering the surface of the first upper electrode layer in the axial direction of the capacitor holes.

[0010] In some embodiments, a stacked structure is provided on the substrate, the stacked structure includes a sacrificial layer, and the capacitor holes are formed in the stacked structure.

[0011] In some embodiments, after forming the lower electrode layer on the surface of the capacitor holes and before forming the dielectric layer, it further includes:

[0012] Selectively etching the stacked structure to form a plurality of openings exposing the sacrificial layer;

[0013] Remove the sacrificial layer in the stacked structure along the opening, forming a first void between the capacitor holes, and the first void exposes another surface of the lower electrode layer.

[0014] In some embodiments, the second upper electrode layer that continuously covers the surface of the first upper electrode layer is formed in the circumferential direction of the first void through the second film-forming process, and at the same time, the second upper electrode layer that discontinuously covers the surface of the first upper electrode layer is formed in the axial direction of the first void.

[0015] In some embodiments, the stacked structure further includes a support layer, and the support layer and the sacrificial layer are alternately stacked.

[0016] In some embodiments, the first film-forming process includes a first deposition rate, the second film-forming process includes a second deposition rate, and the first deposition rate is less than the second deposition rate.

[0017] In some embodiments, after forming the second upper electrode layer, forming a third upper electrode layer on the surface of the second upper electrode layer is further included, and the third upper electrode layer has the same or different material as the second upper electrode layer.

[0018] In some embodiments, after forming the second upper electrode layer, performing an annealing treatment is further included.

[0019] According to a second aspect of the embodiments of the present disclosure, a semiconductor structure is provided, and the semiconductor structure includes:

[0020] A substrate;

[0021] Multiple capacitor holes, located on the substrate;

[0022] A lower electrode layer, covering the surface of the capacitor holes;

[0023] A dielectric layer, continuously covering the surface of the lower electrode layer;

[0024] A first upper electrode layer, continuously covering the surface of the dielectric layer;

[0025] A second upper electrode layer, continuously covering the surface of the first upper electrode layer in the circumferential direction of the capacitor holes, and discontinuously covering the surface of the first upper electrode layer in the axial direction of the capacitor holes.

[0026] In some embodiments, the semiconductor structure further includes a first void, and the first void is located between the capacitor holes.

[0027] In some embodiments, the second upper electrode layer continuously covers the surface of the first upper electrode layer in the circumferential direction of the first void and discontinuously covers the surface of the first upper electrode layer in the axial direction of the first void.

[0028] In some embodiments, the semiconductor structure further includes a stacked structure located on a substrate, and the stacked structure includes a support layer that is in contact connection with the capacitor via hole.

[0029] In some embodiments, the semiconductor structure further includes: a third upper electrode layer that covers the surface of the second upper electrode layer, and the third upper electrode layer has the same or different material from that of the second upper electrode layer.

[0030] The technical solution provided by the embodiments of the present disclosure may include the following beneficial effects: by dividing the cross-section and longitudinal section of the second upper electrode layer formed in the capacitor via hole into discontinuous sections, the continuity of the second upper electrode layer is reduced, and the capacitance leakage of the semiconductor structure is reduced.

[0031] The above summary is only for the purpose of illustration and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be readily apparent by referring to the drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0033] Figure 1 is a flowchart of a method for manufacturing a semiconductor structure shown according to an exemplary embodiment;

[0034] Figure 2 is a schematic structural diagram of a semiconductor structure after forming a stacked structure on a substrate shown according to an exemplary embodiment;

[0035] Figure 3 is a schematic structural diagram of a semiconductor structure after completing step S100 in a method for manufacturing a semiconductor structure shown according to an exemplary embodiment;

[0036] Figure 4 is a schematic structural diagram of a semiconductor structure after completing step S102 in a method for manufacturing a semiconductor structure shown according to an exemplary embodiment;

[0037] Figure 5 is a schematic structural diagram of forming a barrier layer after completing step S102 in a method for manufacturing a semiconductor structure shown according to an exemplary embodiment;

[0038] Figure 6 is a schematic structural diagram of a semiconductor structure after selectively etching a stacked structure after completing step S102 in a method for manufacturing a semiconductor structure shown according to an exemplary embodiment;

[0039] Figure 7 FIG. Figure 7 is a schematic structural diagram of a semiconductor structure after removing a sacrificial layer in a stacked structure after completing step S102 in a manufacturing method of a semiconductor structure according to an exemplary embodiment;

[0040] Figure 8 FIG. Figure 8 is a schematic structural diagram of a semiconductor structure after completing step S104 in a manufacturing method of a semiconductor structure according to an exemplary embodiment;

[0041] Figure 9 FIG. Figure 9 is a schematic structural diagram of a semiconductor structure after completing step S106 in a manufacturing method of a semiconductor structure according to an exemplary embodiment;

[0042] Figure 10 FIG. Figure 10 is a schematic structural diagram of a semiconductor structure after completing step S108 in a manufacturing method of a semiconductor structure according to an exemplary embodiment;

[0043] Figure 11 FIG. Figure 11 is a schematic structural diagram of a semiconductor structure after forming a third upper electrode layer after completing step S108 in a manufacturing method of a semiconductor structure according to an exemplary embodiment;

[0044] Figure 12 FIG. Figure 12 is a schematic structural diagram of a stacked structure formed on a substrate according to an exemplary embodiment;

[0045] Figure 13 FIG. Figure 13 is a schematic structural diagram of a semiconductor after completing step S100 in a manufacturing method of a semiconductor according to an exemplary embodiment;

[0046] Figure 14 FIG. Figure 14 is a schematic structural diagram of a semiconductor structure after selectively etching a stacked structure after completing step S102 in a manufacturing method of a semiconductor structure according to an exemplary embodiment;

[0047] Figure 15 FIG. Figure 15 is a schematic structural diagram of a semiconductor structure after removing a sacrificial layer in a stacked structure after completing step S102 in a manufacturing method of a semiconductor structure according to an exemplary embodiment;

[0048] Figure 16 FIG. Figure 16 is a schematic structural diagram of a semiconductor structure after forming a third upper electrode layer after completing step S108 in a manufacturing method of a semiconductor structure according to an exemplary embodiment. DETAILED DESCRIPTION

[0049] In the following, only some exemplary embodiments are briefly described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and the description are considered to be exemplary in nature and not restrictive.

[0050] In the description of the present disclosure, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present disclosure.

[0051] It can be understood that the terms "first", "second", etc. used in the present disclosure can be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish the first structure from another structure.

[0052] In one or more of the drawings, the same elements are denoted by like reference numerals. For the sake of clarity, the multiple parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, the structure obtained after several steps may be described in one drawing. Many specific details of the present disclosure are described hereinafter, such as the structure, material, size, processing technology and technique of the device, in order to understand the present disclosure more clearly. However, as those skilled in the art can understand, the present disclosure can be implemented without these specific details.

[0053] The following is combined with Figures 1 to 16 to describe in detail the manufacturing method of the semiconductor structure and the semiconductor structure provided by the present disclosure.

[0054] The manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure, as Figure 1 shown, includes the following steps.

[0055] Step S100, forming a plurality of capacitor holes on the substrate, and the bottom end of the capacitor holes exposes a part of the substrate.

[0056] In this embodiment, as Figure 2 shown, a substrate 1 is provided. The material of the substrate 1 can be single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon-on-insulator, etc. In this embodiment, the material of the substrate 1 is silicon nitride. In addition, the substrate 1 may further include a transistor word line (Wordline), a bit line (Bitline), etc. Semiconductor structures such as shallow trench isolation structures and doping regions (not shown) may also be formed in the substrate 1, and the present disclosure does not limit this.

[0057] In this embodiment, a plurality of metal structures 3 are embedded in the substrate 1. The plurality of metal structures 3 are arranged at intervals in the substrate 1, and the metal structures 3 are correspondingly arranged with the capacitor holes 4, that is, the number of the metal structures 3 is the same as that of the capacitor holes 4, as Figure 3As shown, the capacitor holes 4 are arranged opposite to the positions of the metal structures 3, and the longitudinal cross-sectional width of the capacitor holes 4 is the same as that of the metal structures 3. For example, a patterned first mask layer (not shown) may be formed on the substrate 1. The patterned first mask layer has a plurality of first opening patterns. Each first opening is opposite to a metal structure 3, and the longitudinal cross-sectional width of each first opening is the same as that of the metal structure 3. The top surface of the metal structure 3 is exposed by etching the substrate 1 using the patterned first mask layer as a mask. Each capacitor hole 4 extends through the stacked structure 2 into the substrate 1, exposing the entire top surface of the metal structure 3 and a part of the surface of the substrate 1 around the metal structure 3.

[0058] The first mask layer may be a polysilicon mask layer, and the patterned first mask layer is formed by a photolithography and etching process.

[0059] In this embodiment, as Figure 2 shown, the top surface of the metal structure 3 and the top surface of the substrate 1 are not in the same plane. For example, the top surface of the metal structure 3 is lower than a part of the top surface of the main body of the substrate 1, or the top surface of the metal structure 3 is lower than a part of the top surface of the substrate 1 near the outer periphery of the metal structure 3. The longitudinal cross-sectional shape of the metal structure 3 includes, but is not limited to, a rectangular structure.

[0060] In this embodiment, as Figure 3 shown, the substrate 1 has a stacked structure 2. Processes such as chemical vapor deposition (CVD, Chemical Vapor Deposition) or atomic layer deposition (ALD, Atomic layer deposition) can be used to sequentially form the stacked structure 2 on the substrate 1 and the top surface of the metal structure 3. The stacked structure 2 may only include a functional layer for realizing an auxiliary function, that is, a sacrificial layer; or a structure in which a sacrificial layer for realizing an auxiliary function and a support layer for realizing support are sequentially stacked, that is, the support layer and the sacrificial layer are alternately stacked. The sacrificial layer can be made of materials such as silicon oxide. A photoresist is coated on the upper surface of the sacrificial layer and a photoresist pattern (not shown in the figure) is formed. The photoresist pattern is used to etch the stacked structure 2 to form a plurality of capacitor holes 4.

[0061] Step S102, forming a lower electrode layer on the surface of the capacitor hole.

[0062] In this embodiment, as Figure 4As shown, processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition can be used to form the lower electrode layer 5 on the surface of the capacitor via hole 4. The lower electrode layer 5 covers the upper surface of the stacked structure 2, and at the same time covers the inner wall surface of the capacitor via hole and the top surface of the metal structure 3. The bottom surface of the lower electrode layer 5 is in contact with the top surface of the metal structure 3, forming an electrical connection between the lower electrode layer 5 and the metal structure 3. At the same time, the outer wall surface at the bottom of the lower electrode layer 5 is connected and in contact with a part of the surface of the substrate 1, and the substrate 1 plays a role in supporting the lower electrode layer 5, improving the stability of the lower electrode layer 5.

[0063] In this embodiment, after forming the lower electrode layer on the surface of the capacitor via hole in step S102 and before forming the dielectric layer, it further includes:

[0064] Selectively etching the stacked structure to form a plurality of openings exposing the sacrificial layer;

[0065] Removing the sacrificial layer in the stacked structure along the openings to form a first void between the capacitor via holes, and the first void exposes another surface of the lower electrode layer.

[0066] As Figures 5 - 6 shown, a barrier layer 6 is formed above the stacked structure 2. The barrier layer 6 can include a multi-layer dielectric material. Exemplarily, the barrier layer 6 includes a silicon nitride layer 61, a silicon oxide layer 62, a carbon layer 63, and a silicon oxynitride layer 64. An imageable second mask layer 7 can be formed on the barrier layer 6 using a photolithography and etching process. The patterned second mask layer 7 has an opening pattern, and based on the opening pattern, the barrier layer 6 is etched to form a plurality of openings 8. Each opening 8 exposes the surface of a part of the lower electrode layer 5 on the upper surface of the sacrificial layer. The exposed part of the lower electrode layer 5 is removed to expose a part of the surface of the sacrificial layer, and the sacrificial layer is removed. As Figure 7 shown, the lower electrode layer 5 is located on the surface of the capacitor via hole 4. After removing the sacrificial layer, a part of the upper surface of the substrate 1 is exposed. At the same time, a cup-shaped lower electrode layer 5 is formed on the substrate 1, and another surface of the lower electrode layer 5 is exposed, that is, the outer wall surface of the lower electrode layer 5. A first void 10 is formed between two adjacent capacitor via holes 4, that is, a first void 10 is formed between the outer wall surfaces of the lower electrode layers 5 in two adjacent capacitor via holes.

[0067] In this embodiment, the sacrificial layer can be removed using a wet etching process, and the lower electrode layer 5 can be etched using a dry etching process.

[0068] Step S104, forming a dielectric layer continuously covering the surface of the lower electrode layer on the surface of the lower electrode layer.

[0069] In this embodiment, as Figure 8As shown, the dielectric layer 9 continuously covers all the exposed surfaces of the lower electrode layer 5, that is, the dielectric layer 9 is formed on the inner and outer surfaces of the lower electrode layer 5 in the capacitor via hole 4, and at the same time, the dielectric layer 9 also covers a part of the upper surface on the substrate 1. The continuous coverage can be understood as that the dielectric layer 9 covering the lower electrode layer 5 has continuity. For example, the dielectrics in the capacitor via hole 4 are connected together, or the dielectric layer 9 in multiple capacitor via holes 4 and the dielectric layer 9 between the capacitor via holes 4 are connected to each other.

[0070] Among them, the material of the dielectric layer 9 can be a high-K dielectric material to increase the capacitance value of the semiconductor structure, such as one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx or a stack formed by two or more of the above materials in a group.

[0071] Step S106, continuously cover the surface of the dielectric layer with a first upper electrode layer through a first film-forming process.

[0072] In this embodiment, as Figure 9 shown, a first upper electrode layer 11 covering the outer surface of the dielectric layer 9 is formed by using a first film-forming process.

[0073] As Figure 9 shown, the atomic layer chemical vapor deposition method (Atomic layer CVD, ALCVD) can be used to deposit the first upper electrode layer 11 on the surface of the dielectric layer 9, and a conductive material such as TiN (titanium nitride) can also be added to the first upper electrode layer 11. Specifically, the boron-doped SiGe (germanium silicon) in the first upper electrode layer 11 can be replaced with TiN, so as to reduce the penetration of boron into the high-dielectric material (dielectric layer 9) and prevent the generation of leakage current. The precursors used for the growth of the TiN layer are generally metal compounds such as TiCl4 reacting with ammonia gas, and the growth temperature needs to be controlled within 500 degrees Celsius.

[0074] In this embodiment, the first film-forming process can include a first deposition rate. Exemplarily, the first deposition rate can be controlled within 1 nm / min, so as to form the first upper electrode layer 11 on the dielectric layer 9 through a slow growth process, effectively reducing the defect states between the dielectric layer 9 and the first upper electrode layer 11, reducing leakage current, and improving the reliability of the semiconductor structure. The first film-forming process is also used to control the thickness of the first upper electrode layer 11 within a certain range, for example, controlling the thickness of the first upper electrode layer 11 to be about 5 nm.

[0075] Step S108, form a second upper electrode layer that continuously covers the surface of the first upper electrode layer in the circumferential direction of the capacitor via hole, and at the same time form a second upper electrode layer that discontinuously covers the surface of the first upper electrode layer in the axial direction of the capacitor via hole.

[0076] In this embodiment, as Figures 9 - 10As shown, the surface of the first upper electrode layer 11 is continuously covered by a second film-forming process to form a second upper electrode layer 12, that is, the second upper electrode layer 12 is located on the surface of the first upper electrode layer 11 on the inner wall surface of the capacitor hole 4, and also on the surface of the first upper electrode layer 11 on the outer wall surface opposite to the inner wall surface of the capacitor hole 4. At the same time, the cross-section (cross-sectional view) of a part of the second upper electrode layer 12 in the capacitor hole 4 in the first direction and the cross-section (longitudinal section) in the second direction are both discontinuous, that is, the second upper electrode layer 12 forms a first air gap 20 in the capacitor hole 4, and the first air gap 20 disconnects a part of the second upper electrode layer 12 to reduce the possibility of capacitor leakage in the semiconductor structure. As Figure 9 shown. Among them, the direction indicated by the arrow X is the first direction of the cross-section of the second upper electrode layer 12 in the capacitor hole (that is, the direction perpendicular to the longitudinal central axis of the capacitor hole), and the direction indicated by the arrow Y is the second direction of the cross-section of the second upper electrode layer 12 in the capacitor hole 4 (that is, the direction parallel to the longitudinal central axis of the capacitor hole).

[0077] In this embodiment, a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) can be used to deposit the second upper electrode layer 12. When PVD growth is used, a TiN target is used and Ar bombardment deposition is carried out. When CVD is used, metal organic compounds such as TiCl4 are used as precursors to react with NH3.

[0078] In this embodiment, the second film-forming process may include a second deposition rate. When depositing the second upper electrode layer 12 by PVD or CVD, the second deposition rate needs to be greater than the first deposition rate. Exemplarily, the second deposition rate can be controlled to be about 5 - 10 nm / min. Among them, the first air gap 20 is defined by the second upper electrode layer 12, and the size and shape of the first air gap 20 formed in the capacitor hole 4 can be adjusted by adjusting the second deposition rate.

[0079] In this embodiment, the manufacturing method of the semiconductor structure includes forming a second upper electrode layer that continuously covers the surface of the first upper electrode layer in the circumferential direction of the first void by a second film-forming process, and at the same time forming a second upper electrode layer that discontinuously covers the surface of the first upper electrode layer in the axial direction of the first void.

[0080] As Figures 9 - 10As shown, the second upper electrode layer 12 can be continuously covered on the surface of the first upper electrode layer 11 on the inner wall surface of the first gap 10 located between the capacitor holes 4 by using the second film-forming process. Among them, the second upper electrode layers 12 on the inner wall surface of the first gap 10 are connected together, and at the same time, the second upper electrode layer 12 on the inner wall surface of the first gap 10 is connected to the second upper electrode layer 12 on the inner wall surface of the capacitor hole 4, that is, the second upper electrode layer 12 on the inner wall surface of the first gap 10 is connected to the outer wall surface of the second upper electrode layer 12. The second upper electrode layer 12 formed in the first gap 10 is discontinuous in both the cross-section in the first direction and the longitudinal section in the second direction, that is, the second upper electrode layer 12 forms a second air gap 30 in the first gap 10, and the second air gap 30 disconnects part of the second upper electrode layer 12, thereby improving the leakage current situation of the semiconductor structure.

[0081] In this embodiment, after forming the second upper electrode layer in step S108, an annealing treatment is further included.

[0082] The residual impurities in the first upper electrode layer 11 and the second upper electrode layer 12 are removed by a rapid annealing process, and the adhesion between the capacitor dielectric layer 8 and the first upper electrode layer 11 is improved by the rapid annealing process.

[0083] In this embodiment, after forming the second upper electrode layer, a third upper electrode layer is further included on the surface of the second upper electrode layer, and the third upper electrode layer has the same or different material from the second upper electrode layer.

[0084] As Figure 11 shown, after performing a rapid annealing process on the semiconductor structure, in order to increase the conductivity of the capacitor in the semiconductor structure, a third upper electrode layer 13 covering the outer surface of the second upper electrode layer 12 can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition process. Among them, the materials used to prepare the third upper electrode layer 13 include conductive materials such as polysilicon or metal, such as tungsten metal.

[0085] In this embodiment, the stacked structure further includes a support layer, that is, the stacked structure is a laminated structure in which the support layer and the sacrificial layer are alternately stacked. The number of layers M of the support layer in the laminated structure is greater than or equal to the number of layers N of the sacrificial layer that needs to be removed later, that is, M is greater than N. And, above or below the sacrificial layer in the laminated structure is the support layer. The number of the support layer and the sacrificial layer can be set according to needs, and is not limited to this specific embodiment.

[0086] As Figure 12As shown, the stacked structure 2 is composed of a first sacrificial layer 21, a first support layer 22, a second sacrificial layer 23, and a second support layer 24 stacked in sequence from bottom to top. Among them, the materials of the first sacrificial layer 21 and the second sacrificial layer 23 can be selected as materials such as silicon oxide, and the materials of the first support layer 22 and the second support layer 24 can be selected as materials such as silicon nitride or silicon carbonitride. Under the same etching conditions, the removal rates of the first sacrificial layer 21, the second sacrificial layer 23, the first support layer 22, and the second support layer 24 can be different.

[0087] In this embodiment, as Figure 12 shown, the capacitor holes 4 formed in the stacked structure sequentially pass through the second support layer 24, the second sacrificial layer 23, the first support layer 22, and the first sacrificial layer 21 and extend to the top surface of the metal structure 3 in the substrate 1.

[0088] As Figures 13 - 14 shown, during the process of forming the lower electrode layer 5 on the surface of the capacitor holes 4 in step S102, a part of the lower electrode layer 5 also covers the upper surface of the second support layer 24. In order to remove all the sacrificial layers (i.e., the first sacrificial layer 21 and the second sacrificial layer 23) in the stacked structure 2, it is necessary to first selectively etch a part of the lower electrode layer 5 located on the second support layer 24 and a part of the second support layer 24 to expose the sacrificial layer (i.e., the second sacrificial layer 23) in the stacked structure 2. For example, a barrier layer 6 can be formed above the lower electrode layer 5, and by using a third mask layer (not shown in the figure) with an opening pattern, the barrier layer 6 is etched based on the opening pattern to form an opening 8. The opening 8 exposes a part of the upper surface of the lower electrode layer 5 located on the second support layer 24. Based on the opening 8, the lower electrode layer 5 located on the second support layer 24 and a part of the second support layer 24 in the stacked structure 2 are etched to expose a part of the surface of the second sacrificial layer 23. All the second sacrificial layer 23 is removed to expose a part of the surface of the first support layer 22. A part of the first support layer 22 is etched to expose a part of the surface of the first sacrificial layer 21. All the first sacrificial layer 21 is removed. As Figure 14 shown, the lower electrode layer 5 is formed on the surface of the capacitor holes. The structure of the lower electrode layer 5 includes but is not limited to a cup-shaped structure. Among them, the remaining part of the second support layer 24 is in contact and connected with the upper part of the outer wall surface of the lower electrode layer 5, and the remaining part of the first support layer 22 is in contact and connected with the middle part of the outer wall surface of the lower electrode layer 5. The second support layer 24 and the first support layer 22 respectively play a supporting role in the upper part and the middle part of the lower electrode layer 5, further improving the stability of the lower electrode layer 5.

[0089] In this embodiment, the first sacrificial layer 21 and the second sacrificial layer 23 can be removed by a wet etching process, and the first support layer 22 and the second support layer 24 can be etched by a dry etching process.

[0090] In this embodiment, as Figure 15As shown, after removing all the sacrificial layers (i.e., the first sacrificial layer and the second sacrificial layer) in the stacked structure 2, a part of the upper surface of the substrate 1 and the other surface of the lower electrode layer 5, i.e., the outer wall surface of the lower electrode layer 5, are exposed. At the same time, a first gap 10 is formed between two adjacent capacitor holes 4, and a part of the first gap 10 is divided into an upper gap 101 and a lower gap 102 by the first support layer 22.

[0091] In this embodiment, as Figures 15 - 16 shown, when forming the dielectric layer 9 that continuously covers the surface of the lower electrode layer 5 on the surface of the upper electrode layer 5 in step S104, the dielectric layer 9 also covers the surfaces of the second support layer 24 and the first support layer 22 and a part of the surface of the substrate 1 at the same time.

[0092] As Figure 16 shown, when forming the second upper electrode layer 12 that continuously covers the surface of the first upper electrode layer 11 on the surface of the first upper electrode layer 11 in step 108 by the second film-forming process, since a part of the first gap 10 is divided into an upper gap 101 and a lower gap 102 by the first support layer 22, therefore, the second air gap 30 formed by the second upper electrode layer 12 located in the first gap 10 is also divided into an upper air gap 301 and a lower air gap 302. Among them, the upper air gap 301 is formed in the second upper electrode layer 12 located in the upper gap 101, and the lower air gap 302 is formed in the second upper electrode layer 12 located in the lower gap 102.

[0093] A semiconductor structure provided by the present disclosure includes: a substrate, a plurality of capacitor holes, a lower electrode layer, a dielectric layer, a first upper electrode layer, and a second upper electrode layer.

[0094] As Figure 3 and 11 shown, for the substrate 1, a plurality of metal structures 3 are embedded in the substrate 1, and a plurality of capacitor holes 4 are located on the substrate 1. The capacitor holes 4 and the metal structures 3 are arranged in one-to-one correspondence; the lower electrode layer 5 covers the surface of the capacitor holes 4 and the top surface of the metal structures 3 and forms an electrical connection with the capacitor metal structure 3. The dielectric layer 9 continuously covers the surface of the lower electrode layer 5; the first upper electrode layer 11 continuously covers the surface of the dielectric layer 9; the second upper electrode layer 12 continuously covers the surface of the first upper electrode layer 11 in the circumferential direction of the capacitor hole, and at the same time does not continuously cover the surface of the first upper electrode layer 11 in the axial direction of the capacitor hole, that is, the second upper electrode layer 12 located in the capacitor hole 4 forms a first air gap 20 in the capacitor hole 4. For example, the second upper electrode layer 12 forms a first air gap 20 in the middle of the capacitor hole 4.

[0095] In this embodiment, a first air gap 20 is formed in the capacitor hole 4 in the second upper electrode layer 12. The first air gap 20 divides the cross-section and longitudinal section of the second upper electrode layer 12 formed in the capacitor hole 4 into discontinuous sections, reducing the continuity of the second upper electrode layer 12, reducing leakage current, and improving the reliability of the semiconductor structure.

[0096] In this embodiment, the semiconductor structure further includes a first void located between the capacitor holes. As Figure 7 and Figure 11 shown, the first void 10 is located between two adjacent capacitor holes. The second upper electrode layer 12 continuously covers the surface of the first upper electrode layer 11 in the circumferential direction of the first void 10. At the same time, the second upper electrode layer 12 located in the first void 10 forms a second air gap 30 in the first void 10. For example, the second upper electrode layer 12 forms the second air gap 30 in the middle of the first void 10, that is, the second upper electrode layer 12 does not continuously cover the surface of the first upper electrode layer 11 in the axial direction of the first void 10.

[0097] In this embodiment, the second upper electrode layer 12 forms a second air gap 30 in the first void 10 between the capacitor holes 4. The second air gap 30 divides the cross-section and longitudinal section of the second upper electrode layer 12 formed in the first void 10 into discontinuous sections, further reducing the continuity of the second upper electrode layer 12, thereby achieving the effect of reducing leakage current and improving the stability of the semiconductor structure.

[0098] In this embodiment, the semiconductor structure further includes a stacked structure located on the substrate. As Figure 16 shown, the stacked structure 2 includes a first support layer 22 and a second support layer 24. Both the first support layer 22 and the second support layer 24 are in contact connection with the capacitor hole 4. Among them, the first support layer 22 is connected and contacted with the middle part of the outer wall surface of the lower electrode layer 5 in the capacitor hole 4, and the second support layer 24 is connected and contacted with the upper part of the outer wall surface of the lower electrode layer 5 in the capacitor hole 4. The first support layer 22 is located in the middle of the capacitor hole 4, dividing part of the first void 10 into an upper void 101 and a lower void 102, that is, the upper void 101 is located between the second support layer 24 and the first support layer 22, and the lower void 102 is located between the first support layer 22 and the substrate 1. As Figure 15 shown, the second air gap 30 formed by the second upper electrode layer 12 in part of the first void 10 is divided into an upper air gap 301 and a lower air gap 302 by the first support layer 22, that is, the upper air gap 301 is located between the second support layer 24 and the first support layer 22, and the lower air gap 302 is located between the first support layer 22 and the substrate 1.

[0099] In this embodiment, in order to increase the conductivity of the upper electrode layer. As Figure 16As shown, the semiconductor structure further includes a third upper electrode layer 13, which covers the surface of the second upper electrode layer 12. The material of the third upper electrode layer 13 is the same as or different from that of the second upper electrode layer 12. For example, the material of the third upper electrode layer 13 is tungsten, and the material of the second upper electrode layer is titanium nitride, or the materials of both the second upper electrode layer 12 and the third upper electrode layer are titanium nitride.

[0100] In this document, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such article or device. Without further limitation, the elements defined by the statement "comprising..." do not preclude the presence of additional identical elements in the article or device comprising said elements.

[0101] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure.

[0102] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the intention of the present disclosure also includes these modifications and variations.

Claims

1. A method for fabricating a semiconductor structure, characterized in that Comprising: Forming a plurality of capacitor holes in a substrate, with the bottom end of the capacitor holes exposing a part of the substrate; Forming a lower electrode layer on the surface of the capacitor holes; Forming a dielectric layer continuously covering the surface of the lower electrode layer; Continuously covering the surface of the dielectric layer with a first upper electrode layer through a first film formation process, the material of the first upper electrode layer including TiN; Forming a second upper electrode layer continuously covering the surface of the first upper electrode layer in the circumferential direction of the capacitor holes through a second film formation process, and simultaneously forming the second upper electrode layer discontinuously covering the surface of the first upper electrode layer in the axial direction of the capacitor holes, the material of the second upper electrode layer including TiN, the first film formation process including a first deposition rate, the second film formation process including a second deposition rate, and the first deposition rate being less than the second deposition rate.

2. The manufacturing method of the semiconductor structure according to claim 1, wherein A stacked structure is provided on the substrate, the stacked structure including a sacrificial layer, and the capacitor holes are formed in the stacked structure.

3. The manufacturing method of the semiconductor structure according to claim 2, wherein After forming the lower electrode layer on the surface of the capacitor holes and before forming the dielectric layer, further comprising: Selectively etching the stacked structure to form a plurality of openings exposing the sacrificial layer; Removing the sacrificial layer in the stacked structure along the openings to form a first gap between the capacitor holes, the first gap exposing another surface of the lower electrode layer.

4. The manufacturing method of the semiconductor structure according to claim 3, wherein, Forming the second upper electrode layer continuously covering the surface of the first upper electrode layer in the circumferential direction of the first gap through the second film formation process, and simultaneously forming the second upper electrode layer discontinuously covering the surface of the first upper electrode layer in the axial direction of the first gap.

5. The method for manufacturing a semiconductor structure according to claim 3, wherein, The stacked structure further includes a support layer, and the support layer and the sacrificial layer are alternately stacked.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein, After forming the second upper electrode layer, further comprising forming a third upper electrode layer on the surface of the second upper electrode layer, the third upper electrode layer being the same as or different from the second upper electrode layer in material.

7. The method for fabricating a semiconductor structure according to claim 1, wherein After forming the second upper electrode layer, further comprising performing an annealing treatment.

8. A semiconductor structure, characterized in that, The semiconductor structure includes: A substrate; A plurality of capacitor holes located on the substrate; A lower electrode layer covering the surface of the capacitor holes; A dielectric layer continuously covering the surface of the lower electrode layer; A first upper electrode layer continuously covering the surface of the dielectric layer; A second upper electrode layer continuously covering the surface of the first upper electrode layer in the circumferential direction of the capacitor holes, and simultaneously discontinuously covering the surface of the first upper electrode layer in the axial direction of the capacitor holes, the material of the first upper electrode layer including TiN, the material of the second upper electrode layer including TiN, and the deposition rate of the first upper electrode layer being less than the deposition rate of the second upper electrode layer.

9. The semiconductor structure according to claim 8, wherein The semiconductor structure further includes a first gap located between the capacitor holes.

10. The semiconductor structure according to claim 9, characterized in that, The second upper electrode layer continuously covers the surface of the first upper electrode layer in the circumferential direction of the first gap, and simultaneously discontinuously covers the surface of the first upper electrode layer in the axial direction of the first gap.

11. The semiconductor structure according to claim 8, wherein The semiconductor structure further includes a stacked structure located on the substrate, the stacked structure including a support layer, and the support layer is in contact connection with the capacitor holes.

12. The semiconductor structure according to claim 8, wherein, The semiconductor structure further includes: a third upper electrode layer, which covers the surface of the second upper electrode layer, and the third upper electrode layer has the same or different material from that of the second upper electrode layer.

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