A SPAD quenching circuit based on current comparison

Abstract

The application belongs to the technical field of analog integrated circuits, and particularly relates to a SPAD quenching circuit based on current comparison. Avalanche current is inducted by a current mirror, and then the avalanche current signal is detected by current comparison, and a pulse signal is output after being processed by an inverter; this structure effectively accelerates the response speed of single photon detection, shortens the quenching time, thereby reducing the charge quantity of a single photon avalanche photodiode (SPAD); a delay holding circuit with adjustable time is also adopted, which reduces the probability of non-ideal factors such as a post-pulse generated according to the characteristics of different single photon avalanche photodiodes (SPADs), increases the flexibility of the circuit, and makes the circuit more reliable. The quenching and resetting speed of the application is fast, and the quenching and resetting of the single photon avalanche photodiode can be realized within several nanoseconds. The application effectively solves the problem of low single photon detection efficiency caused by the long quenching and resetting time of the traditional single photon detector quenching circuit due to the slow response speed of the avalanche current.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, and specifically relates to a SPAD quenching circuit based on current comparison. Background Technology

[0002] Single-photon avalanche photodiodes (SPADs) are widely used in single-photon laser ranging, homeland security and surveillance, quantum encryption systems, and fluorescence lifetime detection due to their advantages of long detection range and high sensitivity. SPADs utilize the avalanche multiplication effect of charge carriers to detect single photons. Operating in Geiger mode, they function within a very small voltage range exceeding the breakdown voltage but not yet breaking down. In this mode, the high voltage in the SPAD creates a high electric field, placing it within a highly sensitive operating range. Even a weak light signal can trigger a milliampere-level avalanche current within picoseconds, resulting in extremely fast response. Due to the high electric field, the carrier triggering from a single photon is a self-sustaining process with infinite multiplication gain. The avalanche process continues indefinitely; otherwise, the continuous avalanche current would generate excessive power consumption, causing the detector to overheat and potentially damaging the device, preventing subsequent detections.

[0003] In addition to the above, single-photon avalanche photodiodes (SPADs) also suffer from non-ideal factors in single-photon detection, such as dark counting, after-pulse effect, dead time, and noise. These factors limit the detection efficiency that single-photon detection can ultimately achieve. To reduce the impact of these non-ideal factors, a quenching circuit is typically needed to control the operating voltage of the SPAD: the reverse bias voltage of the SPAD is rapidly reduced below the avalanche breakdown voltage to quench the avalanche current. After quenching, the reverse bias voltage of the SPAD is reset to above the avalanche breakdown voltage, restoring it to a standby state, ready for the next avalanche signal detection. This reduces the self-sustaining effect of the avalanche current.

[0004] Quenching circuits have a significant impact on single-photon detection, and there are three main types: passive quenching circuits, active quenching circuits, and gated quenching circuits. Passive quenching circuits have a simple structure, but they have long reset times, long overall dead times, and significant after-pulse effects, which greatly affect the detector's efficiency. Therefore, passive quenching is rarely used in practical circuit designs. Active quenching circuits effectively overcome the shortcomings of passive quenching circuits, requiring shorter quenching and reset times, and shorter dead times, thus effectively improving single-photon detection efficiency. However, in active quenching circuits, the quenching time is mainly determined by the comparator's sensitivity and the detection delay time; a long comparator delay time will lead to an excessively long quenching time. Gated quenching circuits can reduce the bias voltage across the single-photon avalanche photodiode (SPAD) immediately after an avalanche occurs, outputting an avalanche pulse immediately, and quickly reset to the operating voltage after the pulse duration. However, gated quenching circuits can only quench discontinuous photon signals with known arrival times.

[0005] Existing quenching circuits generally employ voltage-sensing or current-sensing avalanche current and use voltage detection to achieve the bias state of the operating voltage across the single-photon avalanche photodiode (SPAD). As a result, the response speed is slow, which affects the quenching reset time, increases the dead time, and reduces the detection efficiency of single photons. Summary of the Invention

[0006] To address the aforementioned problems and shortcomings, and to solve the problem of low single-photon detection efficiency caused by the long quenching reset time due to the slow response speed of avalanche current in traditional single-photon detector quenching circuits, this invention proposes a SPAD quenching circuit based on current comparison. This circuit senses the avalanche current through a current sensing mode and then detects the avalanche current signal through current comparison, effectively improving the response speed of single-photon detection, reducing the dead time, and thus improving the detection efficiency of single photons.

[0007] A SPAD quenching circuit based on current comparison includes a single-photon avalanche photodiode (SPAD), a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a first inverter INV1, a delay-hold circuit, and a current comparator. The first MOSFET M1, second MOSFET, third MOSFET, and fourth MOSFET are all N-type MOSFETs; the fifth MOSFET is a P-type MOSFET.

[0008] The first MOS transistor M1 serves as a reset transistor, with its gate connected to the output of the delay hold circuit, and its drain connected to the anode of the single-photon avalanche photodiode SPAD, the drain of the second MOS transistor M2 and the fifth MOS transistor M5, and the gate of the third MOS transistor M3 and the fourth MOS transistor M4; the source of the first MOS transistor M1 is grounded.

[0009] When the first MOSFET M1 receives the reset signal REC from the delay hold circuit, it turns on, pulling the potential at the anode point of the single-photon avalanche photodiode SPAD down to ground. As a result, the reverse bias voltage across the SPAD is greater than the avalanche breakdown voltage, restoring it to the working state and waiting for the next single-photon trigger.

[0010] The gate of the second MOSFET M2 is interconnected with the gate of the fifth MOSFET M5 and connected to the output of the current comparator. Its source is connected to the drain of the third MOSFET M3. The source of the fifth MOSFET M5 is connected to the power supply voltage VDD.

[0011] The sources of the third MOSFET M3 and the fourth MOSFET M4 are both grounded; the third MOSFET M3 and the fourth MOSFET M4 form a current mirror structure to replicate the current Ispad generated by the avalanche branch of the single-photon avalanche photodiode SPAD; the drain of the fourth MOSFET M4 connects the current Ispad with the external avalanche threshold current Iref, calculates the difference, and outputs the current signal Iin to the input of the current comparator for current comparison.

[0012] The input terminal of the first inverter INV1 is connected to the output terminal of the current comparator, and the output terminal is connected to the input terminal of the delay hold circuit; the first inverter INV1 flips the avalanche current pulse signal OUTb and uses it as the input signal of the delay hold circuit.

[0013] The cathode voltage of the single-photon avalanche photodiode (SPAD) is the sum of its avalanche breakdown voltage Vbreak and the power supply voltage VDD, ensuring that the reverse bias voltage of the SPAD is greater than its avalanche breakdown voltage during operation. The avalanche branch current Ispad of the SPAD is mirrored by a current mirror structure composed of the third MOSFET M3 and the fourth MOSFET M4, compared with the avalanche threshold current Iref, and then outputs a logic level of 0 after a current comparator.

[0014] The input of the current comparator is connected to the drain of the fourth MOS transistor M4 and the externally input avalanche threshold current Iref; it is used to detect avalanche signals. When the avalanche branch current Ispad of the single-photon avalanche photodiode SPAD is generated, it is compared with the avalanche threshold current Iref, and the avalanche current pulse signal OUTb is output to the gate of the first inverter INV1 and the fifth MOS transistor M5.

[0015] The delay hold circuit is used to generate a reset signal REC for the SPAD quenching circuit, which resets the reverse bias voltage of the SPAD to above the avalanche breakdown voltage, restores it to the standby state, and waits for the detection of the next avalanche signal.

[0016] Before a photon arrives, the single-photon avalanche photodiode SPAD is not triggered by a photon, and the current in the avalanche branch is extremely small. At this time, the avalanche current Ispad is copied by the current mirror structure and compared with the avalanche threshold current Iref. Ispad≤Iref, Iin≥0, ​​the output signal OUTb of the current comparator is high, the first MOSFET M1 and the fifth MOSFET M5 are cut off, and the second MOSFET M2 is turned on to form a low-impedance path, so that the anode potential of the single-photon avalanche photodiode SPAD is at a low level. As a result, the reverse bias voltage across the single-photon avalanche photodiode SPAD is greater than the avalanche breakdown voltage Vbreak, and the circuit is in a stable state waiting for photon detection.

[0017] When a photon arrives, the single-photon avalanche photodiode (SPAD) generates an avalanche current Ispad. This avalanche current Ispad is replicated using a current mirror structure and compared with the avalanche threshold current Iref. Ispad > Iref, Iin < 0, the comparator's output signal OUTb is low, the fifth MOSFET M5 is turned on, and the second MOSFET M2 is turned off. This pulls the anode potential of the SPAD high, reducing the reverse bias voltage across the SPAD to below the avalanche breakdown voltage. The avalanche self-sustaining effect of the SPAD stops, achieving the quenching effect.

[0018] Meanwhile, the avalanche current pulse signal OUTb output by the current comparator is inverted by the first inverter INV1, and then delayed by the delay and hold circuit to output the reset signal REC, which turns on the first MOS transistor M1, which acts as the reset transistor, and pulls the potential at the anode point of the single-photon avalanche photodiode SPAD to ground. As a result, the reverse bias voltage across the single-photon avalanche photodiode SPAD is greater than the avalanche breakdown voltage, and it returns to the working state, waiting for the next single-photon trigger.

[0019] Furthermore, the delay hold circuit includes a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, and a second inverter INV2; wherein the sixth MOSFET M6, the seventh MOSFET M7, and the ninth MOSFET M9 are all N-type MOSFETs, and the eighth MOSFET M8 is a P-type MOSFET.

[0020] The source of the sixth MOSFET M6 and the drain and source of the ninth MOSFET M9 are all grounded. The ninth MOSFET M9 is used as a MOSFET capacitor C1.

[0021] The drain of the eighth MOSFET M8 is connected to the source of the seventh MOSFET M7. The source of the eighth MOSFET M8 is connected to the power supply voltage, and the gate of the eighth MOSFET M8 is connected to the external control voltage. The control voltage is used to adjust the delay time of the delay and hold circuit.

[0022] The drain of the seventh MOSFET M7, the drain of the sixth MOSFET M6, and the gate of the ninth MOSFET M9 are connected to the input of the second inverter INV2. The second inverter INV2 flips the gate voltage of the ninth MOSFET M9 after charging or discharging to generate a reset signal REC. Its output is used as the output of the delay and hold circuit, and outputs the reset signal REC to the gate of the first MOSFET M1.

[0023] Furthermore, the avalanche threshold current Iref = 200uA. In Geiger mode, the critical value of the avalanche current for a single-photon avalanche photodiode (SPAD) is 100uA. When an avalanche occurs, a large current in the mA range is generated, far exceeding the avalanche threshold current of 100uA. After quenching is complete, the current in the SPAD avalanche branch is less than 100uA, indicating that quenching is complete. To ensure that the SPAD can detect and quench avalanche after fully entering Geiger mode, the avalanche threshold current Iref is set to be greater than 100uA. However, to improve the detection rate, the avalanche threshold current Iref is set to be much smaller than the peak current. Considering both factors, a current of 200uA is chosen as the avalanche threshold current Iref.

[0024] Furthermore, the current comparator includes a tenth MOSFET M10, an eleventh MOSFET M11, a twelfth MOSFET M12, a thirteenth MOSFET M13, and a third inverter INV3; wherein, the eleventh MOSFET M11 and the twelfth MOSFET M12 are both N-type MOSFETs, and the tenth MOSFET M10 and the thirteenth MOSFET M13 are both P-type MOSFETs.

[0025] The drain of the eleventh MOSFET M11 and the source of the thirteenth MOSFET M13 are connected to the power supply voltage; the drain of the tenth MOSFET M10 and the source of the twelfth MOSFET M12 are grounded.

[0026] The source of the eleventh MOSFET M11 is connected to the source of the tenth MOSFET M10, serving as the input terminal of the current comparator. The input current signal Iin is the difference between the avalanche branch current Ispad (replicated by the current mirror structure) and the avalanche threshold current Iref. The gate of the eleventh MOSFET M11 is also connected to the input terminal of the third inverter INV3.

[0027] The gate of the thirteenth MOSFET M13 is connected to the gate of the twelfth MOSFET M12 and is connected to the input of the current comparator; the drain of the thirteenth MOSFET M13 is connected to the drain of the twelfth MOSFET M12 and is connected to the input of the third inverter INV3, and the signal Vout of the current comparison result is output to the third inverter INV3.

[0028] The third inverter INV3, as the output of the current comparator, flips the received signal Vout and generates an avalanche current pulse signal OUTb, which is then output to the first inverter INV1.

[0029] The SPAD quenching circuit based on current comparison described above operates as follows:

[0030] Testing stage ( Figure 4 (Before time t1): In the initial state, the first MOSFET M1 is off, and the single-photon avalanche photodiode SPAD is connected to the branches of the second MOSFET M2 and the third MOSFET M3, forming an avalanche branch. The single-photon avalanche photodiode SPAD is in reverse bias and there is no photon trigger. The current in the avalanche branch is extremely small, so the voltage drop of the second MOSFET M2 and the third MOSFET M3 is almost zero. The anode potential of the single-photon avalanche photodiode SPAD is at a low level, and the reverse bias voltage of SPAD is higher than the avalanche breakdown voltage. At this time, the avalanche branch current Ispad and the avalanche threshold current Iref are compared by a current comparator, and the output logic level is 1. OUTb is at a high level, the first MOSFET M1 and the fifth MOSFET M5 are off, and the second MOSFET M2 is on, forming a low-impedance path. The circuit is in a stable state awaiting photon detection.

[0031] Avalanche stage ( Figure 4(During the time interval t1-t2): When a photon enters the single-photon avalanche photodiode (SPAD), it instantly triggers an avalanche. The current in the branch of the SPAD and the second MOSFET M2 and the third MOSFET M3 increases rapidly. The anode potential of the SPAD rises. The current in the avalanche branch is mirrored by the current mirror structure composed of the third MOSFET M3 and the fourth MOSFET M4, and compared with the avalanche threshold current by a current comparator, resulting in a logic level of 0. OUTb is at a low level, the second MOSFET M2 is cut off, forming a high-impedance path, cutting off the current mirror of the avalanche branch, causing the anode potential of the SPAD to rise. At the same time, the fifth MOSFET M5 is turned on, pulling the anode potential of the SPAD to a high level VDD, further accelerating the rise of the anode voltage of the SPAD. At this point, the reverse bias voltage across the single-photon avalanche photodiode (SPAD) drops more quickly to below the avalanche breakdown voltage, the avalanche self-sustaining effect stops, and the current in the circuit decreases rapidly, thereby achieving the purpose of rapid quenching.

[0032] Reset phase ( Figure 4 In the middle (the part between time t2-t4): After quenching is completed, the avalanche current pulse signal OUTb outputs a reset signal REC through the first inverter INV1 and a delay hold circuit. Figure 4 At time t3, the first MOS transistor M1 is turned on, rapidly pulling the potential at the anode of the single-photon avalanche photodiode (SPAD) down to a low level. Figure 4 At time t4, the fourth MOSFET M4 is turned off, the current comparator outputs logic level 1, thus turning on the second MOSFET M2, and the avalanche branch of the single-photon avalanche photodiode SPAD is turned on. The reverse bias voltage of the single-photon avalanche photodiode SPAD is greater than the breakdown voltage, so it is reset to the standby state and waits for the next photon trigger.

[0033] Furthermore, the delay-holding circuit delays the reset signal REC beyond the quenching time, waiting for complete quenching before resetting. This delay-holding circuit ensures complete quenching, thereby overcoming the afterpulse phenomenon that affects the imaging accuracy of the single-photon avalanche photodiode (SPAD) detector.

[0034] In summary, compared to ordinary resistive induction quenching circuits, this invention uses a current mirror to sense avalanche current, then detects the avalanche current signal through current comparison, and outputs a pulse signal after processing by an inverter. This structure effectively accelerates the response speed of single-photon detection, shortens the quenching time, and thus reduces the charge quantity of the single-photon avalanche photodiode (SPAD). This invention employs an adjustable-time delay-hold circuit, which, considering the characteristics of different single-photon avalanche photodiodes (SPADs), reduces the probability of non-ideal factors such as afterpulses, increases circuit flexibility, and makes the circuit more reliable. The quenching and reset speeds of this invention are fast, achieving quenching and reset of the single-photon avalanche photodiode within nanoseconds. This effectively solves the problem of low single-photon detection efficiency caused by long quenching and reset times due to the slow response speed of avalanche current in traditional single-photon detector quenching circuits. Attached Figure Description

[0035] Figure 1 This is a circuit diagram of the present invention;

[0036] Figure 2 A circuit diagram of the delay-holding circuit used in this embodiment;

[0037] Figure 3 The circuit diagram of the current comparator in the embodiment;

[0038] Figure 4 This is a waveform diagram of the working state of the present invention;

[0039] Figure 5 The simulation results are shown in the example diagram. Detailed Implementation

[0040] The technical solution of the present invention will now be described in detail with reference to the embodiments and accompanying drawings.

[0041] This invention provides a SPAD quenching circuit based on current comparison, such as... Figure 1As shown, the circuit includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a delay-hold circuit, and a current comparator. The first MOSFET M1, the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 are N-type MOSFETs, and the fifth MOSFET M5 is a P-type MOSFET. The drains of the first MOSFET M1, the second MOSFET M2, and the fifth MOSFET M5, and the gates of the third MOSFET M3 and the fourth MOSFET M4 are all connected to the anode of a single-photon avalanche photodiode (SPAD). The sources of the first MOSFET M1, the third MOSFET M3, and the fourth MOSFET M4 are all grounded to GND. The source of the fifth MOSFET M5 is connected to the external voltage VDD. The source of the second MOSFET M2 is connected to the drain of the third MOSFET. The gate of the second MOSFET M2 is connected to the output of the current comparator. The input of the current comparator is connected to the drain of the fourth MOSFET M4. The gate of the first MOSFET M1 is connected to the output of the delay and hold circuit. The signal input of the delay and hold circuit is connected to the output of the first inverter. The input of the first inverter is connected to the output of the current comparator.

[0042] The current of the single-photon avalanche photodiode (SPAD) is mirrored by a current mirror composed of the third MOSFET M3 and the fourth MOSFET M4, compared with the avalanche threshold current Iref by a current comparator, and then outputs a logic level of "0".

[0043] When OUTb is at a low level, the second MOSFET M2 is cut off and the fifth MOSFET M5 is turned on, which pulls the potential at the anode point of the single-photon avalanche photodiode SPAD to a high level. As a result, the reverse bias voltage across the single-photon avalanche photodiode SPAD can be reduced to below the avalanche breakdown voltage more quickly, and the avalanche self-sustaining effect of the single-photon avalanche photodiode SPAD stops, thus achieving the purpose of quenching the avalanche current.

[0044] Meanwhile, the avalanche current pulse signal OUTb output by the current comparator is inverted by the first inverter INV1 and delayed by the delay and hold circuit to output the reset signal REC, which turns on the first MOS transistor M1, which acts as the reset transistor. This quickly pulls the potential at the anode point of the single-photon avalanche photodiode SPAD to ground, so that the reverse bias voltage across the single-photon avalanche photodiode SPAD is greater than the avalanche breakdown voltage, and it returns to the working state, waiting for the next single-photon trigger.

[0045] The delay and hold circuit for the reset signal REC in this embodiment is as follows: Figure 2As shown, the circuit includes a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, and a second inverter INV2. The sixth MOSFET M6, seventh MOSFET M7, and ninth MOSFET M9 are N-type MOSFETs, while the eighth MOSFET M8 is a P-type MOSFET. The drain of the eighth MOSFET M8 is connected to the source of the seventh MOSFET. The drain of the seventh MOSFET M7 and the drain of the sixth MOSFET M6 are connected to the gate of the ninth MOSFET M9. The gate of the ninth MOSFET M9 is connected to the input of the second inverter INV2, and the output of the second inverter INV2 serves as the output of the delay-hold unit. The source of the eighth MOSFET M8 is connected to the power supply voltage VDD. The source of the sixth MOSFET M6 and the drain and source of the ninth MOSFET M9 are all grounded. The gate of the eighth MOSFET M8 is connected to the external control voltage Vctrl. The ninth MOSFET M9 is used as a MOSFET capacitor C1.

[0046] By adjusting the control voltage Vctrl, the delay can be adjusted to suit the characteristics of different SPADs. The control voltage Vctrl ranges from (0, VDD). The higher the voltage, the smaller the drain current of the eighth MOSFET M8, resulting in a slower charging speed of capacitor C1 and a longer delay time. In the delay-hold circuit, the MOS capacitor C1 formed by the ninth MOSFET M9 is charged through the drain currents of the seventh MOSFET M7 and the eighth MOSFET M8. Since the gate voltage Vctrl of the eighth MOSFET M8 is adjustable, the charging time of the MOS capacitor C1 is also adjustable.

[0047] Upon detecting an avalanche signal, the gate voltage Vcap of MOS capacitor C1 begins to charge slowly until it exceeds the threshold voltage of the second inverter INV2. Then, the output of INV2 flips, outputting a reset signal REC, which turns on the first MOS transistor M1. This pulls the anode potential of the single-photon avalanche photodiode SPAD to ground through the first MOS transistor M1, while the fourth MOS transistor M4 is turned off. The current comparator outputs a logic level "1", turning on the second MOS transistor M2. This activates the avalanche branch of the single-photon avalanche photodiode SPAD, making the reverse bias voltage across SPAD greater than the avalanche breakdown voltage. At this point, the reset of the single-photon avalanche photodiode SPAD is complete, and it returns to its operating state, awaiting the next single-photon trigger.

[0048] The current comparator in this embodiment compares the branch current with the avalanche threshold current, such as... Figure 3As shown: This includes the tenth MOSFET M10, the eleventh MOSFET M11, the twelfth MOSFET M12, the thirteenth MOSFET M13, and the third inverter INV3 and the fourth inverter INV4; the eleventh MOSFET M11 and the twelfth MOSFET M12 are N-type MOSFETs. The tenth MOSFET M10 and the thirteenth MOSFET M13 are P-type MOSFETs. The source of the eleventh MOSFET M11 is connected to the source of the tenth MOSFET M10, serving as the input terminal of the current comparator. The gate of the thirteenth MOSFET M13 is connected to the gate of the twelfth MOSFET M12, serving as the input terminal of the current comparator. The drain of the thirteenth MOSFET M13 is connected to the drain of the twelfth MOSFET M12, serving as the input terminal of the third inverter INV3. The drain of the eleventh MOSFET M11 and the source of the thirteenth MOSFET M13 are connected to the power supply voltage VDD, while the drain of the tenth MOSFET M10 and the source of the twelfth MOSFET M12 are grounded.

[0049] Figure 3 In this context, Iin represents the difference between the avalanche branch current Ispad and the avalanche threshold current Iref of the single-photon avalanche photodiode SPAD. As the input of the current comparator, Iin is a current value that is >0 or <0. The current comparator processes Iin and outputs a binary signal representing the current comparison result Vout. To increase the amplitude of the output voltage, the input of the third inverter INV3 is connected to the Vout signal, and the output of the third inverter INV3 is the avalanche current pulse signal OUTb.

[0050] The 10th MOSFET M10 and the 11th MOSFET M11 serve as the input terminals of the current comparator, acting as source followers that convert current to voltage. The 12th MOSFET M12 and the 13th MOSFET M13 serve as the output terminals, acting as CMOS complementary amplifiers that provide negative feedback. When the input current signal Iin changes, this negative feedback can suppress the change in the input voltage. Therefore, this current comparator has smaller input and output impedances and a shorter response time compared to traditional current comparators based on a common-source cascode current mirror structure.

[0051] When a photon arrives, the single-photon avalanche photodiode (SPAD) generates an avalanche current Ispad. This current is replicated by a current mirror and compared with the avalanche threshold current Iref. When Ispad > Iref, Iin < 0, the output signal OUTb of the current comparator is low, the fifth MOSFET M5 is turned on, and the second MOSFET M2 is turned off. This pulls the anode potential of the SPAD high, achieving the purpose of quenching.

[0052] The following is combined with Figure 1 and Figure 4 The working principle of this invention will be explained.

[0053] 1. The stage to be tested ( Figure 4 (Before time t1): In the initial state, the first MOSFET M1 is off, and the single-photon avalanche photodiode SPAD is connected to the branches of the second MOSFET M2 and the third MOSFET M3, forming an avalanche branch. The single-photon avalanche photodiode SPAD is in a reverse bias state and there is no photon trigger. The current in the avalanche branch is extremely small, so the voltage drop of the second MOSFET M2 and the third MOSFET M3 is almost zero. The anode potential of the single-photon avalanche photodiode SPAD is at a low level, and the reverse bias voltage of SPAD is higher than the avalanche breakdown voltage. At this time, the avalanche branch current Ispad and the avalanche threshold current Iref are compared by a current comparator, and the output logic level is "1". OUTb is at a high level, the first MOSFET M1 and the fifth MOSFET M5 are off, and the second MOSFET M2 is on, forming a low-impedance path. The circuit is in a stable state awaiting photon detection.

[0054] 2. Avalanche stage ( Figure 4 (During the time interval t1-t2): When a photon enters the single-photon avalanche photodiode (SPAD), it instantly triggers an avalanche. The current in the branch of the SPAD and the second MOSFET M2 and the third MOSFET M3 increases rapidly, causing the anode potential of the SPAD to rise. The current in the avalanche branch is mirrored by the current mirror formed by the third MOSFET M3 and the fourth MOSFET M4, and compared with the avalanche threshold current by a current comparator, resulting in a logic level "0". OUTb is at a low level, the second MOSFET M2 is cut off, forming a high-impedance path, which cuts off the current mirror of the avalanche branch, causing the anode potential of the SPAD to rise. At the same time, the fifth MOSFET M5 is turned on, pulling the anode potential of the SPAD to a high level VDD, further accelerating the rise of the anode voltage of the SPAD.

[0055] At this point, the reverse bias voltage across the single-photon avalanche photodiode (SPAD) drops more quickly to below the avalanche breakdown voltage, the avalanche self-sustaining effect stops, and the current in the circuit decreases rapidly, thereby achieving the purpose of rapid quenching.

[0056] 3. Reset Phase ( Figure 4 In the middle (the part between time t2-t4): After quenching is completed, the avalanche current pulse signal OUTb outputs a reset signal REC through the first inverter INV1 and a delay hold circuit. Figure 4 At time t3, the first MOS transistor M1 is turned on, rapidly pulling the potential at the anode of the single-photon avalanche photodiode (SPAD) down to a low level. Figure 4At time t4, the fourth MOSFET M4 is turned off, the current comparator outputs logic level "1", thus turning on the second MOSFET M2, and the avalanche branch of the single-photon avalanche photodiode SPAD is turned on. The reverse bias voltage of the single-photon avalanche photodiode SPAD is greater than the breakdown voltage, so it is reset to the standby state and waits for the next photon trigger.

[0057] Because the afterpulse phenomenon affects the imaging accuracy of the single-photon avalanche photodiode (SPAD) detector, in order to prevent incomplete quenching, the reset signal REC is delayed by the quenching time through a delay hold circuit, and the reset is performed after complete quenching.

[0058] This embodiment uses a current comparison-based SPAD quenching circuit as the dynamic bias circuit for the SPAD. It offers fast quenching and reset speeds, achieving quenching and reset of a single-photon avalanche photodiode (SPAD) within nanoseconds. Simulation of the quenching effect is shown below. Figure 5 As shown, Figure 5 From top to bottom, the graph shows the changes in the anode voltage, avalanche current pulse signal OUTb, and reset signal REC of the single-photon avalanche photodiode, representing the analog single-photon signal. As can be seen from the graph, it takes about 1.4 ns for the reverse bias voltage to reach a value less than the breakdown voltage, and 623 ps for it to recover to the test state where the voltage is greater than the breakdown voltage.

[0059] As can be seen from the above embodiments, compared with ordinary resistive induction quenching circuits, this invention uses a current mirror to sense avalanche current, then detects the avalanche current signal through current comparison, and outputs a pulse signal after processing by an inverter. This effectively accelerates the response speed of single-photon detection, shortens the quenching time, and thus reduces the charge quantity of the single-photon avalanche photodiode (SPAD). An adjustable-time delay-hold circuit is also employed to reduce the probability of non-ideal factors such as afterpulses, increasing circuit flexibility and reliability, taking into account the characteristics of different single-photon avalanche photodiodes (SPADs). The quenching and reset speeds of this invention are fast, achieving quenching and reset of the single-photon avalanche photodiode within nanoseconds. This effectively solves the problem of long quenching and reset times caused by the slow response speed of avalanche current in traditional single-photon detector quenching circuits, resulting in low single-photon detection efficiency. This invention senses the avalanche current through a current-sensing mode during the quenching process and then detects the avalanche current signal through current comparison, effectively improving the response speed of single-photon detection, reducing dead time, and thus improving single-photon detection efficiency.

Claims

1. A SPAD quenching circuit based on current comparison, characterized in that: It includes a single-photon avalanche photodiode (SPAD), a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a first inverter INV1, a delay-hold circuit, and a current comparator; wherein the first MOSFET M1, the second MOSFET, the third MOSFET, and the fourth MOSFET are all N-type MOSFETs; and the fifth MOSFET is a P-type MOSFET. The first MOS transistor M1 serves as a reset transistor, with its gate connected to the output terminal of the delay hold circuit, its drain connected to the anode of the single-photon avalanche photodiode SPAD, the drain of the second MOS transistor M2 and the fifth MOS transistor M5, and the gate of the third MOS transistor M3 and the fourth MOS transistor M4, and the source of the first MOS transistor M1 grounded. When the first MOSFET M1 receives the reset signal REC output by the delay hold circuit, it turns on and pulls the potential at the anode point of the single-photon avalanche photodiode SPAD down to ground. As a result, the reverse bias voltage across the single-photon avalanche photodiode SPAD is greater than the avalanche breakdown voltage, and it returns to the working state, waiting for the next single-photon trigger. The gate of the second MOSFET M2 is interconnected with the gate of the fifth MOSFET M5 and connected to the output of the current comparator. Its source is connected to the drain of the third MOSFET M3. The source of the fifth MOSFET M5 is connected to the power supply voltage VDD. The sources of the third MOSFET M3 and the fourth MOSFET M4 are both grounded; the third MOSFET M3 and the fourth MOSFET M4 form a current mirror structure to replicate the current Ispad generated by the avalanche branch of the single-photon avalanche photodiode SPAD; the drain of the fourth MOSFET M4 connects the replicated current Ispad with the external avalanche threshold current Iref to make a difference, and outputs the current signal Iin to the input of the current comparator. The input terminal of the first inverter INV1 is connected to the output terminal of the current comparator, and the output terminal is connected to the input terminal of the delay hold circuit; the first inverter INV1 flips the avalanche current pulse signal OUTb and uses it as the input signal of the delay hold circuit. The cathode voltage of the single-photon avalanche photodiode (SPAD) is the avalanche breakdown voltage Vbreak of the SPAD plus the power supply voltage VDD, so that the reverse bias voltage of the SPAD in the working state is greater than the avalanche breakdown voltage. The input of the current comparator is connected to the drain of the fourth MOSFET M4 and the externally input avalanche threshold current Iref. Used to detect avalanche signals, when the avalanche branch current Ispad of the single-photon avalanche photodiode SPAD is generated, it is compared with the avalanche threshold current Iref, and the avalanche current pulse signal OUTb is output to the gate of the first inverter INV1 and the fifth MOSFET M5. The delay hold circuit is used to generate a reset signal REC for the SPAD quenching circuit, which resets the reverse bias voltage of the SPAD to above the avalanche breakdown voltage, restores it to the standby state, and waits for the detection of the next avalanche signal. Before a photon arrives, the single-photon avalanche photodiode SPAD is not triggered by a photon. At this time, the avalanche current Ispad is copied by the current mirror structure and compared with the avalanche threshold current Iref. Ispad≤Iref, Iin≥0, ​​the output signal OUTb of the current comparator is high, the first MOSFET M1 and the fifth MOSFET M5 are cut off, and the second MOSFET M2 is turned on to form a low-impedance path, so that the anode potential of the single-photon avalanche photodiode SPAD is at a low level. As a result, the reverse bias voltage across the single-photon avalanche photodiode SPAD is greater than the avalanche breakdown voltage Vbreak, and the circuit is in a stable state waiting for photon detection. When a photon arrives, the single-photon avalanche photodiode SPAD generates an avalanche current Ispad. The avalanche current Ispad is replicated through a current mirror structure and compared with the avalanche threshold current Iref. Ispad > Iref, Iin < 0, the output signal OUTb of the current comparator is low, the fifth MOSFET M5 is turned on, and the second MOSFET M2 is turned off, which pulls the anode potential of the single-photon avalanche photodiode SPAD to a high level. As a result, the reverse bias voltage across the single-photon avalanche photodiode SPAD is reduced to below the avalanche breakdown voltage, and the avalanche self-sustaining effect of the single-photon avalanche photodiode SPAD stops, achieving the purpose of quenching. Meanwhile, the avalanche current pulse signal OUTb output by the current comparator is inverted by the first inverter INV1, and then delayed by the delay and hold circuit to output the reset signal REC, which turns on the first MOS transistor M1, which acts as the reset transistor, and pulls the potential at the anode point of the single-photon avalanche photodiode SPAD to ground. As a result, the reverse bias voltage across the single-photon avalanche photodiode SPAD is greater than the avalanche breakdown voltage, and it returns to the working state, waiting for the next single-photon trigger.

2. The SPAD quenching circuit based on current comparison as described in claim 1, characterized in that: The delay-hold circuit includes a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, and a second inverter INV2; wherein the sixth MOSFET M6, the seventh MOSFET M7, and the ninth MOSFET M9 are all N-type MOSFETs, and the eighth MOSFET M8 is a P-type MOSFET. The source of the sixth MOSFET M6 and the drain and source of the ninth MOSFET M9 are all grounded. The ninth MOSFET M9 is used as a MOSFET capacitor C1. The drain of the eighth MOSFET M8 is connected to the source of the seventh MOSFET M7. The source of the eighth MOSFET M8 is connected to the power supply voltage, and the gate of the eighth MOSFET M8 is connected to the external control voltage. The control voltage is used to adjust the delay time of the delay and hold circuit. The drain of the seventh MOSFET M7, the drain of the sixth MOSFET M6, and the gate of the ninth MOSFET M9 are connected to the input of the second inverter INV2. The second inverter INV2 flips the gate voltage of the ninth MOSFET M9 after charging or discharging to generate a reset signal REC. Its output is used as the output of the delay and hold circuit, and outputs the reset signal REC to the gate of the first MOSFET M1.

3. The SPAD quenching circuit based on current comparison as described in claim 1, characterized in that: The avalanche threshold current Iref = 200uA.

4. The SPAD quenching circuit based on current comparison as described in claim 1, characterized in that: The current comparator includes a tenth MOSFET M10, an eleventh MOSFET M11, a twelfth MOSFET M12, a thirteenth MOSFET M13, and a third inverter INV3; wherein, the eleventh MOSFET M11 and the twelfth MOSFET M12 are both N-type MOSFETs, and the tenth MOSFET M10 and the thirteenth MOSFET M13 are both P-type MOSFETs. The drain of the eleventh MOSFET M11 and the source of the thirteenth MOSFET M13 are connected to the power supply voltage, while the drain of the tenth MOSFET M10 and the source of the twelfth MOSFET M12 are grounded. The source of the eleventh MOSFET M11 is connected to the source of the tenth MOSFET M10, serving as the input terminal of the current comparator. The input current signal Iin is the difference between the avalanche branch current Ispad replicated by the current mirror structure and the avalanche threshold current Iref. The gate of the eleventh MOSFET M11 is also connected to the input terminal of the third inverter INV3. The gate of the thirteenth MOSFET M13 is connected to the gate of the twelfth MOSFET M12 and is connected to the input of the current comparator; the drain of the thirteenth MOSFET M13 is connected to the drain of the twelfth MOSFET M12 and is connected to the input of the third inverter INV3, and the signal Vout of the current comparison result is output to the third inverter INV3. The third inverter INV3, as the output of the current comparator, flips the received signal Vout to generate an avalanche current pulse signal OUTb, which is then output to the first inverter INV1.

5. The SPAD quenching circuit based on current comparison as described in claim 1, characterized in that, The specific workflow is as follows: Detection Phase: In the initial state, the first MOSFET M1 is off, and the single-photon avalanche photodiode SPAD is connected to the branches of the second MOSFET M2 and the third MOSFET M3, forming an avalanche branch. The single-photon avalanche photodiode SPAD is in a reverse bias state and there is no photon trigger. The anode potential of the single-photon avalanche photodiode SPAD is at a low level, and the reverse bias voltage of SPAD is higher than the avalanche breakdown voltage. At this time, the avalanche branch current Ispad and the avalanche threshold current Iref are compared by a current comparator and the output logic level is 1. The avalanche current pulse signal OUTb is at a high level, the first MOSFET M1 and the fifth MOSFET M5 are off, and the second MOSFET M2 is on, forming a low-impedance path. The circuit is in a stable state for photon detection. Avalanche Stage: When a photon enters the single-photon avalanche photodiode (SPAD), it instantly triggers an avalanche. The current in the branch of the SPAD and the second MOSFET M2 and the third MOSFET M3 increases rapidly, causing the anode potential of the SPAD to rise. The current in the avalanche branch is mirrored by the current mirror structure composed of the third MOSFET M3 and the fourth MOSFET M4, and compared with the avalanche threshold current by a current comparator, resulting in a logic level of 0. The avalanche current pulse signal OUTb is at a low level, the second MOSFET M2 is cut off, forming a high-impedance path, which cuts off the current mirror of the avalanche branch, causing the anode potential of the SPAD to rise. At the same time, the fifth MOSFET M5 is turned on, pulling the anode potential of the SPAD to a high level VDD, further accelerating the rise of the anode voltage of the SPAD. At this time, the reverse bias voltage across the SPAD drops below the avalanche breakdown voltage, the avalanche self-sustaining effect stops, and the current in the circuit decreases, achieving the purpose of quenching. Reset Phase: After quenching is completed, the avalanche current pulse signal OUTb turns on the first MOSFET M1 through the first inverter INV1 and the reset signal REC, pulling the potential at the anode of the single-photon avalanche photodiode SPAD to a low level. The fourth MOSFET M4 is turned off, and the current comparator outputs logic level 1, thereby turning on the second MOSFET M2. The avalanche branch of the single-photon avalanche photodiode SPAD is turned on, and the reverse bias voltage of the single-photon avalanche photodiode SPAD is greater than the breakdown voltage, so it is reset to the standby state and waits for the next photon trigger.

6. The SPAD quenching circuit based on current comparison as described in claim 1, characterized in that: The delay holding circuit delays the reset signal REC by the quenching time, waiting for it to be completely quenched before resetting.

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