Low-side pass transistor detection circuit

Abstract

The embodiment of the present disclosure provides a low-side lower power transistor detection circuit, and belongs to the technical field of integrated circuits. The low-side lower power transistor detection circuit comprises: a mode selection circuit, which obtains a first switch signal, a second switch signal and a third switch signal for controlling detection mode switching according to a PWM signal, a HOCP signal and a LOCP signal; a current comparison circuit, which performs switching detection on a low-side lower power transistor between a LOCP detection mode and a ZCD detection mode according to the first switch signal, the second switch signal and the third switch signal, obtains a signal comparison result and provides the signal comparison result to an output circuit through a first node; and the output circuit, which determines a detection result of the LOCP detection mode and a detection result of the ZCD detection mode according to the signal comparison result, the second switch signal and the PWM signal. The embodiment of the present disclosure is suitable for performance detection of a low-side lower power transistor.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a low-side lower power tube detection circuit. BACKGROUND

[0002] In a DC-DC circuit, there are usually high-side upper power tube overcurrent protection (HOCP), low-side lower power tube overcurrent protection (LOCP), and lower power tube zero current detection (ZCD) functions. The design purpose of the HOCP and LOCP mechanisms is to protect the power tube from overheating and burning out due to excessive load current, or affecting the service life of the chip due to overheating. The design purpose of the ZCD is to prevent the inductor current from flowing back to ground, causing energy loss and low efficiency.

[0003] The existing LOCP and ZCD usually need two independent detection circuits to independently complete the detection task, causing waste of circuit layout area and cost. SUMMARY

[0004] The purpose of embodiments of the present disclosure is to provide a low-side lower power tube detection circuit, which switches the sampling path through logic and timing control, realizes the use of the same detection circuit to complete the LOCP and ZCD detection tasks, and saves the circuit layout area and cost.

[0005] To achieve the above purpose, the low-side lower power tube detection circuit provided by embodiments of the present disclosure includes a mode selection circuit, a current comparison circuit, and an output circuit. The mode selection circuit is configured to obtain a first switch signal, a second switch signal, and a third switch signal for controlling detection mode switching according to a pulse width modulation (PWM) signal, a high-side upper power tube overcurrent protection (HOCP) signal, and a low-side lower power tube overcurrent protection (LOCP) signal. The current comparison circuit is configured to switch detection for a low-side lower power tube between an LOCP detection mode and a ZCD detection mode according to the first switch signal, the second switch signal, and the third switch signal, obtain a signal comparison result, and provide the signal comparison result to the output circuit via a first node. The output circuit is configured to determine a detection result of the LOCP detection mode and a detection result of the ZCD detection mode according to the signal comparison result, the second switch signal, and the PWM signal, and output the detection result of the LOCP detection mode via an LOCP signal output end and output the detection result of the ZCD detection mode via a ZCD signal output end.

[0006] In some embodiments of the present disclosure, the mode selection circuit comprises a first OR gate, a first RS flip-flop, a first AND gate, a first inverter, a second inverter and a third inverter. Wherein, a first input end of the first OR gate is coupled with the LOCP signal output end, a second input end of the first OR gate is coupled with the POR signal end, and an output end of the first OR gate is coupled with an R input end of the first RS flip-flop; an S input end of the first RS flip-flop is coupled with the HOCP signal end, and a Q non-output end of the first RS flip-flop is coupled with a first input end of the first AND gate; an input end of the first inverter is coupled with the PWM signal end, and an output end of the first inverter is coupled with a second input end of the first AND gate; an output end of the first AND gate is coupled with a second switch signal output end; an input end of the second inverter is coupled with the PWM signal end, an output end of the second inverter is coupled with a third switch signal output end and an input end of the third inverter; and an output end of the third inverter is coupled with a first switch signal output end.

[0007] In some embodiments of the present disclosure, the current comparison circuit comprises: a first current source, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first comparator, a first resistor, a second resistor, a first transistor module, a second transistor module, a low-side down power tube, a first inductor, a first capacitor and a third resistor, wherein a first end of the first current source is coupled to a first voltage end, and a second end of the first current source is coupled to a positive input end of the first comparator; a first end of the first switch is coupled to the second end of the first current source, and a second end of the first switch is coupled to a first end of the first transistor module; a first end of the second switch is coupled to the second end of the first current source, and a second end of the second switch is coupled to a second end of the first transistor module and a first end of the second transistor module; a first end of the third switch is coupled to the second end of the first current source, and a second end of the third switch is coupled to a first end of the first resistor; a first end of the fourth switch is coupled to the second end of the first current source and a first end of the second resistor, and a second end of the fourth switch is coupled to a negative input end of the first comparator; a first end of the fifth switch is coupled to the negative input end of the first comparator, and a second end of the fifth switch is coupled to a second voltage end; an output end of the first comparator is coupled to the first node; a second end of the first resistor is coupled to the second voltage end; a second end of the second resistor is coupled to the second voltage end; a third end of the first transistor module is coupled to a driving signal end; a second end of the second transistor module is coupled to an SW pin and a first pole of the low-side down power tube, and a third end of the second transistor module is coupled to the driving signal end; a control pole of the low-side down power tube is coupled to the driving signal end, and a second pole of the low-side down power tube is coupled to the second voltage end; a first end of the first inductor is coupled to the SW pin, and a second end of the first inductor is coupled to a first end of the first capacitor and a first end of the third resistor; a second end of the first capacitor is coupled to the second voltage end; and a second end of the third resistor is coupled to the second voltage end.

[0008] In some embodiments of the present disclosure, the output circuit comprises: a fourth inverter, a fifth inverter, a second AND gate, a third AND gate, a second RS flip-flop and a third RS flip-flop. Wherein, the input end of the fourth inverter is coupled with the second switch signal output end, and the output end of the fourth inverter is coupled with the third input end of the third AND gate; the input end of the fifth inverter is coupled with the PWM signal end, and the output end of the fifth inverter is coupled with the second input end of the second AND gate and the second input end of the third AND gate; the first input end of the second AND gate is coupled with the second switch signal output end, the third input end of the second AND gate is coupled with the first node, and the output end of the second AND gate is coupled with the S input end of the second RS flip-flop; the first input end of the third AND gate is coupled with the first node, and the output end of the third AND gate is coupled with the S input end of the third RS flip-flop; the R input end of the second RS flip-flop is coupled with the PWM signal end, and the Q output end of the second RS flip-flop is coupled with the ZCD signal output end; the R input end of the third RS flip-flop is coupled with the PWM signal end, and the Q output end of the third RS flip-flop is coupled with the LOCP signal output end.

[0009] In some embodiments of the present disclosure, the first transistor module comprises: a first transistor, a second transistor, a third transistor and a fourth transistor. Wherein, the control electrode of the first transistor is coupled with the driving signal end, the first electrode of the first transistor is coupled with the first end of the first transistor module, and the second electrode of the first transistor is coupled with the first electrode of the second transistor; the control electrode of the second transistor is coupled with the driving signal end, the second electrode of the second transistor is coupled with the first electrode of the third transistor; the control electrode of the third transistor is coupled with the driving signal end, the second electrode of the third transistor is coupled with the first electrode of the fourth transistor; the control electrode of the fourth transistor is coupled with the driving signal end, and the second electrode of the fourth transistor is coupled with the second end of the first transistor module.

[0010] In some embodiments of the present disclosure, the second transistor module comprises: a fifth transistor. Wherein, the control electrode of the fifth transistor is coupled with the driving signal end, the first electrode of the fifth transistor is coupled with the first end of the second transistor module, and the second electrode of the fifth transistor is coupled with the second end of the second transistor module.

[0011] In some embodiments of the present disclosure, the first switch signal simultaneously controls the third switch and the fourth switch, when the first switch signal is 1, the third switch and the fourth switch are both closed, when the first switch signal is 0, the third switch and the fourth switch are both opened; the second switch signal controls the second switch, when the second switch signal is 1, the second switch is closed, when the second switch signal is 0, the second switch is opened; the third switch signal simultaneously controls the first switch and the fifth switch, when the third switch signal is 1, the first switch and the fifth switch are both closed, when the third switch signal is 0, the first switch and the fifth switch are both opened.

[0012] In some embodiments of the present disclosure, when the input signal of the PWM signal end is 1, and the input signal of the HOCP signal end is 0, in the negative half cycle of the PWM signal, the detection of the ZCD detection mode of the low-side power down transistor will be performed.

[0013] In some embodiments of the present disclosure, when the input signal of the PWM signal end is 1, and the input signal of the HOCP signal end is 1, in the negative half cycle of the PWM signal, the detection of the LOCP detection mode of the low-side power down transistor will be performed.

[0014] In some embodiments of the present disclosure, the transistors in the first transistor module and the second transistor module are all NMOS transistors.

[0015] Embodiments of the present disclosure can realize both LOCP and ZCD detection modes through a set of detection circuits, thus saving circuit area.

[0016] Other features and advantages of the embodiments of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings are included to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification, and are used to explain the embodiments of the present disclosure together with the following detailed description, but do not constitute a limitation of the embodiments of the present disclosure. In the drawings:

[0018] Figure 1 is a detection circuit schematic diagram for performing LOCP and ZCD;

[0019] Figure 2 is a schematic block diagram of a low-side power down transistor detection circuit 200 according to an embodiment of the present disclosure;

[0020] Figure 3 is an exemplary circuit diagram of a low-side power down transistor detection circuit 200 according to an embodiment of the present disclosure.

[0021] The elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0022] In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort also belong to the scope of protection of the present disclosure.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together will mean that the parts are joined together either directly or through one or more intermediate parts.

[0024] In all embodiments of the present disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the on-current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as a control terminal, and the remaining two terminals of the MOS transistor are referred to as a first terminal and a second terminal, respectively. The transistors employed in the embodiments of the present disclosure are mainly switching transistors. In addition, for the convenience of unified description, in the context, the base of a bipolar junction transistor (BJT) is referred to as a control terminal, the emitter of the BJT is referred to as a first terminal, and the collector of the BJT is referred to as a second terminal. In addition, terms such as "first" and "second" are only used to distinguish one component (or part of a component) from another component (or another part of a component).

[0025] Figure 1 A detection circuit schematic diagram for performing LOCP and ZCD is shown. In the example of Figure 1 , in addition to the inductor in the dashed box, the output capacitor C OUT and the load resistor R LOAD are external components of the chip, and the other parts are internal circuits of the chip. The detection circuit for performing LOCP and ZCD is composed of a comparator, current sources I S1 , I S2 , sampling resistors R LOCP_S and RZCD_S , initialization resistor R init , R init*2 and a switch, wherein the rest is the same except R LOCP_S and R ZCD_S . In the high side of the PWM (Pulse Width Modulation) signal positive half cycle (i.e. PWM = 1), the switch Φ1 is switched on, and the comparator is in the initialization state. In the low side of the PWM signal negative half cycle (i.e. PWM = 0), the switch Φ2 is switched on, and the comparator detects the voltage change of the SW pin to perceive the inductance current value change. However, this detection scheme needs two independent detection circuits to complete the detection task independently, which causes the consumption of the circuit layout area and the waste of cost.

[0026] Embodiments of the present disclosure provide a low-side down power tube detection circuit. The low-side down power tube detection circuit only needs one set of detection circuit to realize both LOCP and ZCD detection methods, thus saving the circuit area. Figure 2 A schematic block diagram of a low-side down power tube detection circuit 200 according to an embodiment of the present disclosure is shown. As shown in Figure 2 The low-side down power tube detection circuit 200 can include a mode selection circuit 210, a current comparison circuit 220, and an output circuit 230.

[0027] The mode selection circuit 210 can be coupled to the current comparison circuit 220, the output circuit 230, a PWM signal end, a POR signal end, a HOCP signal end, and a LOCP signal output end. The mode selection circuit 210 can be configured to obtain a first switch signal Φ1, a second switch signal Φ2, and a third switch signal Φ3 for controlling the switching of the detection mode according to the PWM signal, the HOCP signal, and the LOCP signal.

[0028] The current comparison circuit 220 can be coupled to the mode selection circuit 210, the output circuit 230, a first voltage end V1, a second voltage end V2, and a drive signal end LS_Drive. The current comparison circuit 220 can be configured to switch the detection of the low-side down power tube between the LOCP detection mode and the ZCD detection mode according to the first switch signal Φ1, the second switch signal Φ2, and the third switch signal Φ3, and obtain a signal comparison result Vc and provide the signal comparison result Vc to the output circuit 230 via a first node N1.

[0029] The output circuit 230 can be coupled with the mode selection circuit 210, the current comparison circuit 220, the PWM signal end, the ZCD signal output end and the LOCP signal output end. The output circuit 230 can be configured to determine the detection result of the LOCP detection mode and the detection result of the ZCD detection mode according to the signal comparison result Vc, the second switch signal Φ2 and the PWM signal, and output the detection result of the LOCP detection mode via the LOCP signal output end and the detection result of the ZCD detection mode via the ZCD signal output end.

[0030] The low-side lower power tube detection circuit according to the embodiments of the present disclosure switches the sampling path through logic and timing control, realizes the completion of the LOCP and ZCD detection tasks by using the same detection circuit, saves the circuit layout area and cost. Compared with the detection circuit for performing LOCP and ZCD detection such as Figure 1 The low-side lower power tube detection circuit according to the embodiments of the present disclosure does not need two sets of independent detection circuits, has a simpler structure and saves the circuit area.

[0031] Figure 3 An exemplary circuit diagram of the low-side lower power tube detection circuit 200 according to the embodiments of the present disclosure is shown. As shown in Figure 3 The mode selection circuit 210 can include a first OR gate G1, a first RS flip-flop A, a first AND gate G2, a first inverter D1, a second inverter D2 and a third inverter D3. The first input end of the first OR gate G1 is coupled with the LOCP signal output end, the second input end of the first OR gate G1 is coupled with the POR signal end, and the output end of the first OR gate G1 is coupled with the R input end of the first RS flip-flop A. The S input end of the first RS flip-flop A is coupled with the HOCP signal end, and the Q non-output end of the first RS flip-flop A is coupled with the first input end of the first AND gate G2. The input end of the first inverter D1 is coupled with the PWM signal end, and the output end of the first inverter D1 is coupled with the second input end of the first AND gate G2. The output end of the first AND gate G2 is coupled with the second switch signal output end Φ2. The input end of the second inverter D2 is coupled with the PWM signal end, the output end of the second inverter D2 is coupled with the third switch signal output end Φ3 and the input end of the third inverter D3. The output end of the third inverter D3 is coupled with the first switch signal output end Φ1.

[0032] The current comparison circuit 220 can include a first current source I1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a first comparator Com, a first resistor R1, a second resistor R2, a first transistor module Mu1, a second transistor module Mu2, a low-side power down transistor LSM, a first inductor L1, a first capacitor C1, and a third resistor R3. The first end of the first current source I1 is coupled to a first voltage end V1, and the second end of the first current source I1 is coupled to the positive input end of the first comparator Com. The first end of the first switch S1 is coupled to the second end of the first current source I1, and the second end of the first switch S1 is coupled to the first end of the first transistor module Mu1. The first end of the second switch S2 is coupled to the second end of the first current source I1, and the second end of the second switch S2 is coupled to the second end of the first transistor module Mu1 and the first end of the second transistor module Mu2. The first end of the third switch S3 is coupled to the second end of the first current source I1, and the second end of the third switch S3 is coupled to the first end of the first resistor R1. The first end of the fourth switch S4 is coupled to the second end of the first current source I1 and the first end of the second resistor R2, and the second end of the fourth switch S4 is coupled to the negative input end of the first comparator Com. The first end of the fifth switch S5 is coupled to the negative input end of the first comparator Com, and the second end of the fifth switch S5 is coupled to a second voltage end V2. The output end of the first comparator Com is coupled to the first node N1. The second end of the first resistor R1 is coupled to the second voltage end V2. The second end of the second resistor R2 is coupled to the second voltage end V2. The third end of the first transistor module Mu1 is coupled to a drive signal end LS_Drive. The second end of the second transistor module Mu2 is coupled to a SW pin and the first pole of the low-side power down transistor LSM, and the third end of the second transistor module Mu2 is coupled to the drive signal end LS_Drive. The control pole of the low-side power down transistor LSM is coupled to the drive signal end LS_Drive, and the second pole of the low-side power down transistor LSM is coupled to the second voltage end V2. The first end of the first inductor L1 is coupled to the SW pin, and the second end of the first inductor L1 is coupled to the first end of the first capacitor C1 and the first end of the third resistor R3. The second end of the first capacitor C1 is coupled to the second voltage end V2. The second end of the third resistor R3 is coupled to the second voltage end V2.

[0033] The first transistor module Mu1 can include (not shown in the figure): a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4 connected in series. The control electrode of the first transistor M1 is coupled to the driving signal end LS_Drive, the first electrode of the first transistor M1 is coupled to the first end of the first transistor module Mu1, and the second electrode of the first transistor M1 is coupled to the first electrode of the second transistor M2. The control electrode of the second transistor M2 is coupled to the driving signal end LS_Drive, and the second electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3. The control electrode of the third transistor M3 is coupled to the driving signal end LS_Drive, and the second electrode of the third transistor M3 is coupled to the first electrode of the fourth transistor M4. The control electrode of the fourth transistor M4 is coupled to the driving signal end LS_Drive, and the second electrode of the fourth transistor M4 is coupled to the second end of the first transistor module Mu1.

[0034] The second transistor module Mu2 can include (not shown in the figure): a fifth transistor M5. The control electrode of the fifth transistor M5 is coupled to the driving signal end LS_Drive, the first electrode of the fifth transistor M5 is coupled to the first end of the second transistor module Mu2, and the second electrode of the fifth transistor M5 is coupled to the second end of the second transistor module Mu2.

[0035] The output circuit 230 can include: a fourth inverter D4, a fifth inverter D5, a second AND gate G3, a third AND gate G4, a second RS flip-flop B and a third RS flip-flop C. The input end of the fourth inverter D4 is coupled to the second switch signal output end Φ2, and the output end of the fourth inverter D4 is coupled to the third input end of the third AND gate G4. The input end of the fifth inverter D5 is coupled to the PWM signal end, and the output end of the fifth inverter D5 is coupled to the second input end of the second AND gate G3 and the second input end of the third AND gate G4. The first input end of the second AND gate G3 is coupled to the second switch signal output end Φ2, the third input end of the second AND gate G3 is coupled to the first node N1, and the output end of the second AND gate G3 is coupled to the S input end of the second RS flip-flop B. The first input end of the third AND gate G4 is coupled to the first node N1, and the output end of the third AND gate G4 is coupled to the S input end of the third RS flip-flop C. The R input end of the second RS flip-flop B is coupled to the PWM signal end, and the Q output end of the second RS flip-flop B is coupled to the ZCD signal output end. The R input end of the third RS flip-flop C is coupled to the PWM signal end, and the Q output end of the third RS flip-flop C is coupled to the LOCP signal output end.

[0036] In Figure 3In the example, a high voltage signal is input from the first voltage terminal V1, the second voltage terminal V2 is grounded. The HOCP signal terminal inputs the HOCP signal, when the high-side power tube overflows, HOCP = 1 and the high-side power tube is closed, and the low-side power tube is opened. When the high-side power tube does not overflow, HOCP = 0, and the behavior of the high-side power tube is not interfered. The POR signal terminal inputs the power-on reset signal, during the power-on reset process, POR = 1, and after the reset is completed, POR = 0. The PWM signal terminal inputs the PWM signal, when the positive half cycle of the square wave, PWM = 1, the high-side power tube is opened, and the low-side power tube is closed; when the negative half cycle of the square wave, PWM = 0, the high-side power tube is closed, and the low-side power tube is opened. The LOCP signal output terminal outputs the LOCP signal, when the low-side power tube overflows, LOCP = 0, and when the low-side power tube does not overflow, LOCP = 1. The transistors in the first transistor module Mu1 and the second transistor module Mu2, including the first to fifth transistors, are all NMOS transistors of the same type as the low-side power tube. The resistance value of the second resistor is 2 times the resistance value of the first resistor.

[0037] The working process of the low-side power tube detection circuit 200 according to the embodiment of the present disclosure will be described below in conjunction with the example of Figure 3

[0038] The power-on reset signal POR resets the first RS flip-flop A, and after reset, every cycle takes the PWM positive half cycle (i.e. PWM = 1) as the initial state, at this time the first switch signal output terminal outputs Φ1 = 1, controls the third switch S3 and the fourth switch S4 to be closed, and the second switch signal output terminal and the third switch signal output terminal Φ2 and Φ3 are both 0, controls the first switch S1, the second switch S2 and the fifth switch S5 to be opened, and the comparator Com is in the initialization state, and the second RS flip-flop B and the third RS flip-flop C are in the reset state.

[0039] ​HOCP is detected cycle by cycle. If no HOCP occurs in the positive half cycle of PWM, i.e. PWM = 1 and HOCP = 0, the detection of the ZCD detection mode of the low-side lower power tube will be performed in the negative half cycle of the PWM signal, i.e. PWM = 0, that is, the second and third switch signal output terminals Φ2 and Φ3 are both 1, the first, second and fifth switches S1, S2 and S5 are all closed, the first switch signal output terminal outputs Φ1 = 0, and the third and fourth switches S3 and S4 are both open. If HOCP occurs in the positive half cycle of PWM, i.e. HOCP = 1, the first RS flip-flop A latches this state, and the detection of the LOCP detection mode of the low-side lower power tube will be performed in the negative half cycle of the PWM signal, i.e. PWM = 0, that is, the third switch signal output terminal Φ3 is 1, the first and fifth switches S1 and S5 are closed, the first switch signal output terminal Φ1 and the second switch signal output terminal Φ2 are both 0, and the second, third and fourth switches S2, S3 and S4 are all open.

[0040] When HOCP changes from 1 to 0 at the beginning of the negative half cycle of the PWM signal, the LOCP signal changes to 1 when the inductor current is detected to be lower than the current limit value of the lower power tube during the LOCP detection, and then the first RS flip-flop A is reset. If PWM = 1 at this time, the upper power tube of the high side is turned on, and a new PWM cycle starts. If PWM is still 0, ZCD = 1, and the lower power tube of the low side is turned off. In this negative half cycle, the inductor current is continued to flow through the parasitic diode of the lower power tube of the low side until the new cycle starts and returns to the synchronous rectification state.

[0041] In summary, the low-side lower power tube detection circuit according to the embodiments of the present disclosure switches the sampling path through logic and timing control, realizes the completion of the LOCP and ZCD detection tasks by using the same detection circuit, saves the circuit layout area and cost. Compared with the detection circuit for performing LOCP and ZCD in the prior art Figure 1 The low-side lower power tube detection circuit according to the embodiments of the present disclosure does not need two sets of independent detection circuits, has a simpler structure and saves the circuit area.

[0042] The diagrams of the flowcharts and block diagrams in the drawings show the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams can represent a module, a segment, or a portion of code which comprises one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession can in fact be executed substantially concurrently or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations thereof, can be implemented by dedicated hardware-based systems which perform the specified functions or acts or combinations thereof, or can be implemented by a combination of dedicated hardware and computer instructions.

[0043] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular form "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Accordingly, the use of the articles "a," "an," and "the" as well as grammatical changes in the context of this document is understood to be taken as a set of equivalents in the context of this document. Similarly, the words "comprise," "comprises," and "comprising" are to be interpreted inclusively rather than exclusively. Likewise, the terms "include," "including," and "or" should be construed to be inclusive, unless otherwise indicated herein. Where the term "example" is used in this document, particularly in the context of a set of terms, the term "example" is merely an example of and is not to be construed as limiting or exhaustive.

[0044] Further aspects and scope of adaptations become apparent from the description provided herein. It should be appreciated that individual aspects of the present application can be implemented alone or in combination with one or more other aspects. It should also be appreciated that the description and specific examples herein are intended to be illustrative only and are not intended to limit the scope of the present application.

[0045] The foregoing detailed description of a number of embodiments of the present disclosure has been presented for purposes of illustration and description. It is apparent to those skilled in the art, however, that various modifications and changes can be made without departing from the spirit and scope of the present disclosure. The scope of the disclosure is defined by the appended claims.

Claims

1. A low-side power tube detection circuit, characterized in that: include: Mode selection circuit, current comparison circuit and output circuit, The mode selection circuit is configured to obtain a first switching signal, a second switching signal, and a third switching signal for controlling detection mode switching according to a pulse width modulation (PWM) signal, a high-side upper power tube over-current detection (HOCP) signal, and a low-side lower power tube over-current detection (LOCP) signal; The current comparison circuit is configured to switch and detect the low-side lower power transistor between the LOCP detection mode and the ZCD detection mode according to the first switching signal, the second switching signal, and the third switching signal, obtain a signal comparison result, and provide the signal comparison result to the output circuit via the first node; The output circuit is configured to determine a detection result of the LOCP detection mode and a detection result of the ZCD detection mode based on the signal comparison result, the second switching signal and the PWM signal, and output the detection result of the LOCP detection mode via the LOCP signal output terminal and output the detection result of the ZCD detection mode via the ZCD signal output terminal.

2. The low-side lower power tube detection circuit according to claim 1, characterized in that: The mode selection circuit includes: a first OR gate, a first RS trigger, a first AND gate, a first inverter, a second inverter and a third inverter. Wherein, the first input terminal of the first OR gate is coupled to the LOCP signal output terminal, the second input terminal of the first OR gate is coupled to the POR signal terminal, and the output terminal of the first OR gate is coupled to the R input terminal of the first RS flip-flop; The S input terminal of the first RS flip-flop is coupled to the HOCP signal terminal, and the Q non-output terminal of the first RS flip-flop is coupled to the first input terminal of the first AND gate; The input terminal of the first inverter is coupled to the PWM signal terminal, and the output terminal of the first inverter is coupled to the second input terminal of the first AND gate; The output terminal of the first AND gate is coupled to the second switch signal output terminal; The input terminal of the second inverter is coupled to the PWM signal terminal, and the output terminal of the second inverter is coupled to the third switch signal output terminal and the input terminal of the third inverter; The output terminal of the third inverter is coupled to the first switch signal output terminal.

3. The low-side lower power tube detection circuit according to claim 1, characterized in that: The current comparison circuit includes: a first current source, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first comparator, a first resistor, a second resistor, a first transistor module, a second transistor module, a low-side power transistor, a first inductor, a first capacitor and a third resistor. Wherein, the first terminal of the first current source is coupled to the first voltage terminal, and the second terminal of the first current source is coupled to the positive input terminal of the first comparator; A first terminal of the first switch is coupled to the second terminal of the first current source, and a second terminal of the first switch is coupled to the first terminal of the first transistor module; A first terminal of the second switch is coupled to the second terminal of the first current source, and a second terminal of the second switch is coupled to the second terminal of the first transistor module and the first terminal of the second transistor module; A first terminal of the third switch is coupled to the second terminal of the first current source, and a second terminal of the third switch is coupled to the first terminal of the first resistor; A first terminal of the fourth switch is coupled to the second terminal of the first current source and the first terminal of the second resistor, and a second terminal of the fourth switch is coupled to the inverting input terminal of the first comparator; A first terminal of the fifth switch is coupled to the inverting input terminal of the first comparator, and a second terminal of the fifth switch is coupled to the second voltage terminal; An output terminal of the first comparator is coupled to the first node; The second end of the first resistor is coupled to the second voltage end; The second end of the second resistor is coupled to the second voltage end; The third terminal of the first transistor module is coupled to the driving signal terminal; The second end of the second transistor module is coupled to the SW pin and the first electrode of the low-side lower power transistor, and the third end of the second transistor module is coupled to the driving signal end; The control electrode of the low-side lower power tube is coupled to the driving signal terminal, and the second electrode of the low-side lower power tube is coupled to the second voltage terminal; A first end of the first inductor is coupled to the SW pin, and a second end of the first inductor is coupled to a first end of the first capacitor and a first end of the third resistor; The second terminal of the first capacitor is coupled to the second voltage terminal; The second terminal of the third resistor is coupled to the second voltage terminal.

4. The low-side lower power tube detection circuit according to claim 1, characterized in that: The output circuit includes: a fourth inverter, a fifth inverter, a second AND gate, a third AND gate, a second RS trigger and a third RS trigger, The input terminal of the fourth inverter is coupled to the second switch signal output terminal, and the output terminal of the fourth inverter is coupled to the third input terminal of the third AND gate; The input terminal of the fifth inverter is coupled to the PWM signal terminal, and the output terminal of the fifth inverter is coupled to the second input terminal of the second AND gate and the second input terminal of the third AND gate; The first input terminal of the second AND gate is coupled to the second switch signal output terminal, the third input terminal of the second AND gate is coupled to the first node, and the output terminal of the second AND gate is coupled to the S input terminal of the second RS flip-flop; A first input terminal of the third AND gate is coupled to the first node, and an output terminal of the third AND gate is coupled to the S input terminal of the third RS flip-flop; The R input terminal of the second RS trigger is coupled to the PWM signal terminal, and the Q output terminal of the second RS trigger is coupled to the ZCD signal output terminal; An R input terminal of the third RS flip-flop is coupled to the PWM signal terminal, and a Q output terminal of the third RS flip-flop is coupled to the LOCP signal output terminal.

5. The low-side lower power tube detection circuit according to claim 3, characterized in that: The first transistor module includes: a first transistor, a second transistor, a third transistor and a fourth transistor, Wherein, the control electrode of the first transistor is coupled to the driving signal terminal, the first electrode of the first transistor is coupled to the first terminal of the first transistor module, and the second electrode of the first transistor is coupled to the first electrode of the second transistor; The control electrode of the second transistor is coupled to the driving signal terminal, and the second electrode of the second transistor is coupled to the first electrode of the third transistor; The control electrode of the third transistor is coupled to the driving signal terminal, and the second electrode of the third transistor is coupled to the first electrode of the fourth transistor; A control electrode of the fourth transistor is coupled to the driving signal terminal, and a second electrode of the fourth transistor is coupled to the second terminal of the first transistor module.

6. The low-side lower power tube detection circuit according to claim 3, characterized in that: The second transistor module includes: a fifth transistor, The control electrode of the fifth transistor is coupled to the driving signal terminal, the first electrode of the fifth transistor is coupled to the first terminal of the second transistor module, and the second electrode of the fifth transistor is coupled to the second terminal of the second transistor module.

7. The low-side lower power tube detection circuit according to claim 3, characterized in that: The first switch signal simultaneously controls the third switch and the fourth switch. When the first switch signal is 1, the third switch and the fourth switch are both closed, and when the first switch signal is 0, the third switch and the fourth switch are both opened. The second switch signal controls the second switch. When the second switch signal is 1, the second switch is closed, and when the second switch signal is 0, the second switch is opened. The third switch signal simultaneously controls the first switch and the fifth switch. When the third switch signal is 1, the first switch and the fifth switch are both closed, and when the third switch signal is 0, the first switch and the fifth switch are both opened.

8. The low-side lower power tube detection circuit according to claim 1, characterized in that: When the input signal of the PWM signal terminal is 1 and the input signal of the HOCP signal terminal is 0, the ZCD detection mode detection of the low-side lower power transistor is performed in the negative half cycle of the PWM signal.

9. The low-side lower power tube detection circuit according to claim 1, characterized in that: When the input signal of the PWM signal terminal is 1 and the input signal of the HOCP signal terminal is 1, the detection of the LOCP detection mode of the low-side lower power transistor will be performed in the negative half cycle of the PWM signal.

10. The low-side lower power tube detection circuit according to claim 3, characterized in that: The transistors in the first transistor module and the second transistor module are both NMOS transistors.

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