A design method for on-chip mode converter based on reverse design

Abstract

The present invention discloses a design method for an on-chip mode converter based on inverse design. The method is characterized by comprising the steps of designing an initial structure of the on-chip mode converter, which is sequentially an input waveguide, a polygonal design region, and an output waveguide from left to right, and inserting a plurality of discrete optimization points x at the upper boundary, the lower boundary, or the upper and lower boundaries of the design region; performing a first forward transmission simulation and a second adjoint simulation on the mode converter using a three-dimensional finite-difference time-domain method, obtaining the initial electric field and the adjoint electric field accordingly, and calculating the quality factor change value ΔFOM of the optimization point; and finally, iteratively calculating the positions of the plurality of edge optimization points on the y-axis using a calculation formula until ΔFOM is less than 1×10 ‑5 , that is, the step of designing the required on-chip mode converter, has the advantages of short time consumption, high design efficiency, and the designed product has small size, low loss, large working bandwidth and high conversion efficiency.

Description

Technical Field

[0001] The present invention relates to the intelligent design of silicon-based photonic devices, and in particular to an on-chip mode converter and a testing method based on reverse design. Background Art

[0002] The rapid development of digital information technology has placed higher demands on data center transmission capacity and energy consumption. To achieve high-capacity, low-loss, and low-cost on-chip data transmission, mode multiplexing / demultiplexing technology based on silicon-based photonic platforms has become a hot research topic in both research and industry. Silicon-based mode converters with high conversion efficiency and low loss are a key prerequisite for this technology.

[0003] Currently reported mode converters mostly use traditional design methods, utilizing specific structures such as tapered directional couplers, asymmetric Y-branches, and multimode interference couplers to achieve on-chip mode conversion. However, these three devices are typically large, and the design methods employed often rely on the designer's experience, consuming a significant amount of time on structural design and parameter optimization. Furthermore, when the design goal, i.e., the target mode, changes, the structure often needs to be redesigned and optimized. This extensive repetitive work results in low design efficiency. Therefore, challenges in device size and conversion efficiency for on-chip mode converters urgently need to be addressed. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a design method for an on-chip mode converter based on inverse design, which has short design time, high design efficiency and relatively low design complexity. The mode converter has good performance of small size, low loss, wide working bandwidth and high conversion efficiency.

[0005] The technical solution adopted by the present invention to solve the above technical problems is: a design method of an on-chip mode converter based on reverse design, comprising the following steps:

[0006] (1) The initial structure of the on-chip mode converter is composed of an input waveguide, a polygonal design area for mode conversion, and an output waveguide from left to right.

[0007] (2) establishing a plane coordinate system, inserting a number of discrete optimization points x at the upper boundary or the lower boundary or at the upper and lower boundaries of the polygonal design area described in step (1), and performing edge optimization on the mode converter by adjusting the position of the optimization point x in the y-axis direction;

[0008] (3) The light source is forward transmitted from the input waveguide to the output waveguide, and the first forward transmission simulation of the mode converter is performed using the three-dimensional finite-difference time-domain (3D-FDTD) method to obtain the initial electric field tangential component E at the optimized point in the design area. || (x) and the normal component D of the initial electric displacement vector ⊥ (x);

[0009] (4) Place the light source on the input waveguide on the cross section of the output waveguide, radiate it in reverse to the optimized point, and use the three-dimensional time-domain finite difference method to perform a second adjoint simulation to obtain the tangential component of the adjoint electric field at the optimized point in the design area. and the normal component of the accompanying electric displacement vector

[0010] (5) Calculate the quality factor change value ΔFOM at the optimization point x. The calculation formula is as follows:

[0011] Where Δx n (x) is the position change of the nth optimization point in the y-axis direction, ε si is the dielectric constant of silicon material, is the dielectric constant of silicon dioxide material, E || (x) is the tangential component of the initial electric field, D ⊥ (x) is the normal component of the initial electric displacement vector, is the tangential component of the accompanying electric field, is the normal component of the adjoint electric displacement vector, dA is integrated over the boundary of the initial design region;

[0012] (6) The edge shape of the mode converter is optimized by continuously adjusting the position of the optimization point x in the y-axis direction. Specifically, in the Python programming language, the position of the inserted optimization point x on the y-axis is iteratively calculated using the calculation formula in step (5) until the ΔFOM of all inserted discrete optimization points is less than 1×10 -5 , which means the required on-chip mode converter is designed. At this point, the normalized power of the first-order transverse electric field mode (TE1) in the output optical field approaches the target power of 1. Normalized power = output power / source power. If there is no loss, the two are equal, which is 1.

[0013] Furthermore, step (3) is specifically to transmit the light source forward from the input waveguide to the output waveguide, perform the first forward transmission simulation of the mode converter using the three-dimensional finite-difference time-domain (3D-FDTD) method, obtain the initial electric field E(x) and the initial electric displacement vector D(x) at the optimized point in the design area using Lumerical software, and then calculate the tangential component E of the initial electric field at the optimized point in the design area using Python programming language. || (x) and the normal component D of the initial electric displacement vector ⊥ (x).

[0014] Furthermore, step (4) is specifically as follows: the light source on the input waveguide is placed on the cross section of the output waveguide, radiated in reverse to the optimized point, and a second adjoint simulation is performed using the three-dimensional finite difference time domain method, and the adjoint electric field E at the optimized point in the design area is obtained using Lumerical software. adj (x) and the accompanying electric displacement vector D adj (x), and then use Python programming language to calculate the tangential component of the accompanying electric field at the optimized point in the design area and the normal component of the accompanying electric displacement vector

[0015] Furthermore, the width of the input waveguide is 0.5 μm, and the width of the output waveguide is 1.5 μm.

[0016] Furthermore, the input waveguide, the polygonal design area and the output waveguide are all made of silicon.

[0017] Furthermore, the on-chip mode converter has a total thickness of 220 nm and is covered with a 1 μm thick silicon dioxide cladding layer.

[0018] Furthermore, the coupling length of the on-chip mode converter is 12-30 μm.

[0019] Compared with the prior art, the advantages of the present invention are: a design method for an on-chip mode converter based on reverse design of the present invention utilizes the reverse design method to enable the mode converter to have advantages such as wide bandwidth, low loss, high conversion efficiency, and high design efficiency while occupying a smaller device space size; through the designed mode converter, an on-chip test structure can be designed, and the conversion efficiency of the mode converter can be directly tested without the need to connect to a complex external test system, such as without the need to connect to an infrared CCD to capture the output light field. The design method is time-saving, highly efficient, and relatively low in design complexity. The designed mode converter has the advantages of high design efficiency, wide bandwidth, low loss, and high conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The design flow chart of the on-chip mode converter based on reverse design of the present invention is adjusted accordingly after modification;

[0021] Figure 2 Schematic diagram of the structure of the TE0-TE1 converter optimized based on the adjoint method of the present invention;

[0022] Figure 3 The simulated output power of the TE0-TE1 converter of the present invention at a center wavelength of 1550nm with different coupling lengths and the output power tested at 1550nm with coupling lengths of 12μm, 16μm, and 20μm;

[0023] Figure 4 This is the simulated electric field diagram of the TE0-TE1 converter of the present invention with a coupling length of 16 μm at 1550 nm;

[0024] Figure 5 This is a simulated output power curve of the TE0-TE1 converter of the present invention with a coupling length of 16 μm within a working bandwidth of 1500 nm to 1600 nm;

[0025] Figure 6 This is a graph showing the output power of the TE0-TE1 converter of the present invention when the coupling length is 12 μm and the working bandwidth is 1500 nm to 1565 nm.

[0026] Figure 7 This is a graph showing the insertion loss of the TE0-TE1 converter of the present invention with a coupling length of 12 μm and tested within a working bandwidth of 1500 nm to 1565 nm.

[0027] Figure 8 This is a graph showing the output power of the TE0-TE1 converter of the present invention when the coupling length is 16 μm and the working bandwidth is 1500 nm to 1565 nm.

[0028] Figure 9 The insertion loss curve of the TE0-TE1 converter of the present invention is tested within a working bandwidth of 1500nm to 1565nm with a coupling length of 16μm.

[0029] Figure 10 This is a graph showing the output power of the TE0-TE1 converter of the present invention when the coupling length is 20 μm and the working bandwidth is 1500 nm to 1565 nm.

[0030] Figure 11 This is a graph showing the insertion loss of the TE0-TE1 converter of the present invention with a coupling length of 20 μm and tested within a working bandwidth of 1500 nm to 1565 nm. DETAILED DESCRIPTION

[0031] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments. 1. Specific embodiments

[0033] A design method for on-chip mode converter based on reverse design, such as Figure 1 The following steps are shown:

[0034] Step 1: Design the initial structure of the on-chip mode converter. From left to right, it consists of an input waveguide, a polygonal design area for mode conversion, and an output waveguide.

[0035] Step 2: Establish a plane coordinate system with a design area of ​​10 μm × 1.5 μm. Insert 100 discrete optimization points x at the upper and lower boundaries of the design area. Optimize the edge of the mode converter by adjusting the position of the optimization points x in the y-axis direction.

[0036] Step 3: Transmit the light source forward from the input waveguide to the output waveguide, and use the three-dimensional finite-difference time-domain (3D-FDTD) method to perform the first forward transmission simulation of the mode converter to obtain the tangential component initial electric field E at the optimized point in the design area. || (x) and the normal component of the initial magnetic field D ⊥ (x); Specifically, the light source is forward transmitted from the input waveguide to the output waveguide, and the three-dimensional finite-difference time-domain (3D-FDTD) method is used to perform the first forward transmission simulation of the mode converter. The initial electric field E(x) and the initial electric displacement vector D(x) at the optimized point in the design area are obtained using Lumerical software, and the tangential component E of the initial electric field at the optimized point in the design area is calculated using Python programming language. || (x) and the normal component D of the initial electric displacement vector ⊥ (x).

[0037] Step 4: Place the light source on the input waveguide on the cross section of the output waveguide, radiate it in reverse to the optimized point, and use the 3D finite-difference time-domain method to perform a second adjoint simulation to obtain the tangential component adjoint electric field at the optimized point in the design area. Normal component accompanies the magnetic field Specifically, the light source on the input waveguide is placed on the cross section of the output waveguide, radiated in reverse to the optimized point, and the second adjoint simulation is performed using the three-dimensional finite difference time domain method. The accompanying electric field E at the optimized point in the design area is obtained using Lumerical software.adj (x) and the accompanying electric displacement vector D adj (x), and then use Python programming language to calculate the tangential component of the accompanying electric field at the optimized point in the design area and the normal component of the accompanying electric displacement vector

[0038] Step 5: Calculate the quality factor change value ΔFOM of the optimization point x. The calculation formula is as follows:

[0039] Where Δx n (x) is the position change of the nth optimization point in the y-axis direction, ε si is the dielectric constant of silicon material, is the dielectric constant of silicon dioxide material, E || (x) is the initial electric field of the tangential component at the optimization point, D ⊥ (x) is the normal component of the initial magnetic field at the optimization point, The tangential component of the electric field at the optimization point is: To optimize the point normal component adjoint magnetic field, dA is integrated over the boundary of the initial design region;

[0040] Step 6: Optimize the edge shape of the mode converter by continuously adjusting the position of the optimization point x on the y-axis. Specifically, in the Python programming language, use the calculation formula in step 5 to iteratively calculate the position of the inserted optimization point x on the y-axis until the ΔFOM of all inserted discrete optimization points is less than 1×10 -5 , that is, the required on-chip mode converter (TE0-TE1 converter) is designed. At this point, the normalized power of the first-order transverse electric field mode (TE1) in the output optical field approaches the target power of 1. Normalized power = output power / source power. If there is no loss, the two are equal, which is 1. The fundamental transverse electric field mode (TE0) is incident from the left input waveguide. The design target can be expressed by the figure of merit (FOM), which is defined as the normalized power of the TE1 mode in the output optical field. The figure of merit change value ΔFOM is the figure of merit change measured between two adjacent changes in the position of any optimization point in the y-axis direction.

[0041] Figure 2 The schematic diagram of the TE0-TE1 converter structure after optimization based on the adjoint method is shown in the figure. The mode converter is designed using the inverse design method, and the optimal boundary parameters are obtained after 30 iterations to obtain the desired mode converter.

[0042] The input waveguide is 0.5 μm wide, and the output waveguide is 1.5 μm wide. The input waveguide, polygonal design region, and output waveguide are all made of silicon. The on-chip mode converter has a total thickness of 220 nm and is covered with a 1 μm-thick silicon dioxide cladding.

[0043] 2. Results Analysis

[0044] 1. Description of the simulated output power of the TE0-TE1 converter with different coupling lengths

[0045] Figure 3 The simulated output power of the TE0-TE1 converter at a central wavelength of 1550nm with different coupling lengths is shown, as well as the output power of the test at 1550nm with coupling lengths of 12μm, 16μm, and 20μm. The coupling length range of the mode converter is set to 12μm to 30μm. Within the coupling length range, the upper port of the TE0-TE1 converter ( Figure 4 (1) the arrow indicates the method), the lower port ( Figure 4 The output power of the middle port (indicated by the arrow in (3)) fluctuates at -3dB, and its performance is relatively stable. Figure 4 The output power (indicated by the arrow in (2)) remains below -29.4dB, and there is essentially no coupled light in the intermediate waveguide. In the figure, the output power of the upper and lower ports tested at 1550nm for coupling lengths of 12μm, 16μm, and 20μm is essentially consistent with the corresponding simulated output power. The measured output power at the intermediate port has a larger loss than the corresponding simulated output power. The different coupling lengths of the TE0-TE1 converter do not affect the output splitting ratio.

[0046] Figure 4 This is the simulated electric field diagram of the TE0-TE1 converter of the present invention with a coupling length of 16μm at 1550nm. TE0 enters from the input waveguide and is converted to TE1 after passing through the designed area. At (a) in the figure, the conversion of TE0 to TE1 is completed, and at (b), the two mode spots of TE1 are separated and enter the upper and lower waveguides at the coupling part (c) respectively. Among them, the phases of the two mode spots in the upper and lower waveguides remain unchanged and differ by π. (d) is a rectangular waveguide structure that ensures that the two mode spots in the upper and lower waveguides will not couple with each other. In the figure, (1) and (3) are the upper and lower waveguide mode spots, respectively, and (2) is the intermediate waveguide, which has almost no coupled light.

[0047] Figure 5This graph shows the simulated output power curves for the TE0-TE1 converter of the present invention with a coupling length of 16 μm within a 1500 nm to 1600 nm operating bandwidth. Within the 1500 nm to 1600 nm operating bandwidth, the output power at both the upper and lower ports fluctuates around -3 dB, while the output power at the intermediate waveguide remains below -17.2 dB. At a center wavelength of 1550 nm, the output powers at the upper, lower, and intermediate ports are -2.9 dB, -3.0 dB, and -28.9 dB, respectively. The simulated output power at the upper and lower ports of the TE0-TE1 converter remains essentially consistent.

[0048] 2. Test output power and insertion loss of each port of the TE0-TE1 converter with coupling lengths of 12μm, 16μm, and 20μm:

[0049] The mode converter test method is as follows: align the input and output ports of the SOI device with the optical fiber, then inject a tunable laser source in the 1500nm to 1600nm band into the input port and test the power of each output port.

[0050] Figure 6 This graph shows the output power of the TE0-TE1 converter tested within a 1500nm to 1565nm operating bandwidth with a coupling length of 12μm. Within a 65nm operating bandwidth, the output power at the upper port remains above -4.1dB, the output power at the lower port is above -4.4dB, and the output power at the middle port is below -18.0dB. At 1550nm, the output powers at the upper, lower, and middle ports are -3.2dB, -2.6dB, and -21.9dB, respectively.

[0051] Figure 7 This is the insertion loss curve of the TE0-TE1 converter of the present invention with a coupling length of 12μm and tested within the working bandwidth of 1500nm to 1565nm. The insertion loss (IL) expression is:

[0052] IL=10·log 10 (T up / 10+T down / 10) (3)

[0053] Among them, T up 、T down The IL value represents the normalized output power at the upper and lower ports of the TE0-TE1 converter. Within a 65nm bandwidth, the insertion loss remains above -1.2dB.

[0054] Figure 8This graph shows the output power of the TE0-TE1 converter tested within a 1500nm to 1565nm operating bandwidth with a coupling length of 16μm. Within a 65nm operating bandwidth, the upper port output power is a minimum of -4.5dB, the lower port output power is a minimum of -3.8dB, and the middle port output power is a maximum of -15.0dB. At 1550nm, the upper, lower, and middle port output powers are -3.5dB, -3.0dB, and -16.8dB, respectively.

[0055] Figure 9 The insertion loss curve of the TE0-TE1 converter of the present invention is tested in a working bandwidth of 1500nm to 1565nm with a coupling length of 16μm. In a bandwidth of 65nm, the insertion loss is kept above -0.7dB.

[0056] Figure 10 This graph shows the output power of the TE0-TE1 converter tested within a 1500nm to 1565nm operating bandwidth with a coupling length of 20μm. Within the 65nm operating bandwidth, the output power at the upper and lower ports is a minimum of -4.0dB, while the output power at the middle port is a maximum of -13.7dB. At 1550nm, the output powers at the upper, lower, and middle ports are -3.4dB, -3.6dB, and -16.0dB, respectively.

[0057] Figure 11 The insertion loss curve of the TE0-TE1 converter of the present invention is tested in a working bandwidth of 1500nm to 1565nm with a coupling length of 20μm. In a bandwidth of 65nm, the insertion loss is kept above -0.9dB.

[0058] The present invention proposes an on-chip mode converter and testing method based on reverse design. The TE0-TE1 converter utilizes an intelligent edge shape optimization design method. After 30 iterations, the optimal boundary parameters are obtained, resulting in the desired mode converter. This converter achieves high design efficiency, wide bandwidth, low loss, and high conversion efficiency. Simulations of different coupling lengths for the TE0-TE1 converter demonstrate that varying coupling lengths has no effect on output power. Experimental testing verifies that the TE0-TE1 converter can achieve high-efficiency mode conversion. The present invention achieves high performance in the TE0-TE1 converter through simulation and testing.

[0059] The above description is not intended to limit the present invention, and the present invention is not limited to the above examples. Any changes, modifications, additions or substitutions made by persons of ordinary skill in the art within the spirit and scope of the present invention shall also fall within the scope of protection of the present invention.

Claims

1. A design method for an on-chip mode converter based on reverse design, characterized in that The following steps are involved: (1) The initial structure of the on-chip mode converter is composed of an input waveguide, a polygonal design area for mode conversion, and an output waveguide from left to right. (2) establishing a plane coordinate system, inserting a number of discrete optimization points x at the upper boundary or the lower boundary or at the upper and lower boundaries of the polygonal design area described in step (1), and performing edge optimization on the mode converter by adjusting the position of the optimization point x in the y-axis direction; (3) Transmit the light source forward from the input waveguide to the output waveguide, and use the three-dimensional finite-difference time-domain method to perform the first forward transmission simulation of the mode converter to obtain the initial electric field tangential component E at the optimized point in the design area. || (x) and the normal component D of the initial electric displacement vector ⊥ (x); (4) Place the light source on the input waveguide on the cross section of the output waveguide, radiate it in reverse to the optimized point, and use the three-dimensional finite difference time domain method to perform a second adjoint simulation to obtain the tangential component of the adjoint electric field at the optimized point in the design area. and the normal component of the accompanying electric displacement vector (5) Calculate the quality factor change value △FOM at the optimization point x. The calculation formula is as follows: Where Δx n (x) is the position change of the nth optimization point in the y-axis direction, ε si is the dielectric constant of silicon material, is the dielectric constant of silicon dioxide material, E || (x) is the tangential component of the initial electric field, D ⊥ (x) is the normal component of the initial electric displacement vector, is the tangential component of the accompanying electric field, is the normal component of the adjoint electric displacement vector, dA is integrated over the boundary of the initial design region; (6) The edge shape of the mode converter is optimized by continuously adjusting the position of the optimization point x in the y-axis direction. Specifically, in the Python programming language, the position of the inserted optimization point x on the y-axis is iteratively calculated using the calculation formula in step (5) until the ΔFOM of all inserted discrete optimization points is less than 1×10 -5 , that is, designing the required on-chip mode converter.

2. The design method of an on-chip mode converter based on reverse design according to claim 1, characterized in that Step (3) is as follows: forward transmit the light source from the input waveguide to the output waveguide, perform the first forward transmission simulation of the mode converter using the three-dimensional time-domain finite difference method, obtain the initial electric field E(x) and the initial electric displacement vector D(x) at the optimized point in the design area using Lumerical software, and then calculate the tangential component E of the initial electric field at the optimized point in the design area using Python programming language. || (x) and the normal component D of the initial electric displacement vector ⊥ (x).

3. The design method of an on-chip mode converter based on reverse design according to claim 1, characterized in that Step (4) is as follows: place the light source on the input waveguide on the cross section of the output waveguide, radiate it in reverse to the optimized point, perform a second adjoint simulation using the three-dimensional finite-difference time-domain method, and use Lumerical software to obtain the adjoint electric field E at the optimized point in the design area. adj (x) and the accompanying electric displacement vector D adj (x), and then use Python programming language to calculate the tangential component of the accompanying electric field at the optimized point in the design area and the normal component of the accompanying electric displacement vector 4. The design method of an on-chip mode converter based on reverse engineering according to claim 1, characterized in that: The width of the input waveguide is 0.5 μm, and the width of the output waveguide is 1.5 μm.

5. The design method of an on-chip mode converter based on reverse design according to claim 1, characterized in that: The input waveguide, the polygonal design area and the output waveguide are all made of silicon.

6. The design method of an on-chip mode converter based on reverse design according to claim 1, characterized in that: The on-chip mode converter has a total thickness of 220 nm and is covered with a 1 μm thick silicon dioxide cladding layer.

7. The design method of an on-chip mode converter based on reverse engineering according to claim 1, characterized in that: The coupling length of the on-chip mode converter is 12-30 μm.

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