Data reading method, memory storage device and memory control circuit unit

Abstract

This invention provides a data reading method, a memory storage device, and a memory control circuit unit. The method includes: receiving a read instruction from a host system, indicating that data should be read from at least one logical unit, wherein the at least one logical unit is mapped to a first physical unit; obtaining state information of at least two adjacent memory units in the first physical unit; determining an electrical parameter offset value corresponding to the at least two adjacent memory units based on the state information; and sending a read instruction sequence based on the electrical parameter offset value, indicating that the first physical unit should be read based on at least one electrical parameter, wherein the at least one electrical parameter is controlled by the electrical parameter offset value. This reduces electrical interference between memory units and improves the stability of reading data from memory units.

Description

Technical Field

[0001] This invention relates to a memory management technology, and more particularly to a data reading method, a memory storage device, and a memory control circuit unit. Background Technology

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] However, in the pursuit of reducing the size of rewritable non-volatile memory modules, the distance between memory cells in these modules also increases, leading to more significant electrical interference between the cells. Therefore, reducing electrical interference between memory cells and improving the stability of data reading from these cells is a subject of ongoing research in the field. Summary of the Invention

[0004] This invention provides a data reading method, a memory storage device, and a memory control circuit unit, which can reduce electrical interference between storage units and improve the stability of reading data from storage units.

[0005] An exemplary embodiment of the present invention provides a data reading method for a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising a plurality of physical units, the data reading method comprising: receiving a read instruction from a host system, wherein the read instruction indicates reading data from at least one logical unit, and the at least one logical unit is mapped to a first physical unit among the plurality of physical units; obtaining state information of at least two adjacent memory units in the first physical unit; determining an electrical parameter offset value corresponding to the at least two adjacent memory units based on the state information; and sending a read instruction sequence based on the electrical parameter offset value, wherein the read instruction sequence indicates reading the first physical unit based on at least one electrical parameter, and the at least one electrical parameter is controlled by the electrical parameter offset value.

[0006] In an exemplary embodiment of the present invention, the at least two adjacent storage cells include a first storage cell and a second storage cell, wherein the first storage cell and the second storage cell are respectively located on different bit lines adjacent to each other in the rewritable non-volatile memory module.

[0007] In an exemplary embodiment of the present invention, the electrical parameter offset value includes a read level offset value, and the read level offset value is used to control the read voltage level applied to the first memory cell during the reading of data from the first memory cell.

[0008] In an exemplary embodiment of the present invention, the electrical parameter offset value includes a conduction voltage offset value, and the conduction voltage offset value is used to control the conduction voltage applied to the second memory cell during data reading from the first memory cell.

[0009] In one exemplary embodiment of the present invention, the state information of the at least two adjacent memory cells reflects the voltage range corresponding to the respective critical voltage of the at least two adjacent memory cells.

[0010] In an exemplary embodiment of the present invention, the at least two adjacent memory cells include a first memory cell and a second memory cell, and the step of determining the electrical parameter offset value corresponding to the at least two adjacent memory cells based on the state information includes: determining grouping information based on the state information of the first memory cell and the state information of the second memory cell; and determining the electrical parameter offset value corresponding to the at least two adjacent memory cells based on the grouping information.

[0011] In an exemplary embodiment of the present invention, the step of obtaining the status information of the at least two adjacent storage cells in the first entity cell includes: sending a read instruction sequence to instruct data to be read from the first entity cell; and obtaining the status information of the at least two adjacent storage cells based on the read data.

[0012] In an exemplary embodiment of the present invention, the data reading method further includes: determining whether the risk state of the rewritable non-volatile memory module exceeds the allowable range; and in response to the risk state exceeding the allowable range, activating an electrical parameter adjustment mechanism to obtain the state information of the at least two adjacent memory cells.

[0013] An exemplary embodiment of the present invention provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is configured to connect to a host system. The rewritable non-volatile memory module includes a plurality of physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: receive a read instruction from the host system, wherein the read instruction indicates reading data from at least one logical unit, and the at least one logical unit is mapped to a first physical unit among the plurality of physical units; obtain state information of at least two adjacent memory units in the first physical unit; determine an electrical parameter offset value corresponding to the at least two adjacent memory units based on the state information; and send a read instruction sequence based on the electrical parameter offset value, wherein the read instruction sequence indicates reading the first physical unit based on at least one electrical parameter, and the at least one electrical parameter is controlled by the electrical parameter offset value.

[0014] In an exemplary embodiment of the present invention, the at least two adjacent memory cells include a first memory cell and a second memory cell, and the operation of the memory control circuit unit to determine the electrical parameter offset value corresponding to the at least two adjacent memory cells based on the state information includes: determining grouping information based on the state information of the first memory cell and the state information of the second memory cell; and determining the electrical parameter offset value corresponding to the at least two adjacent memory cells based on the grouping information.

[0015] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to obtain the status information of the at least two adjacent memory cells in the first entity unit includes: sending a read instruction sequence to instruct data to be read from the first entity unit; and obtaining the status information of the at least two adjacent memory cells based on the read data.

[0016] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: determine whether the risk state of the rewritable non-volatile memory module exceeds the allowable range; and in response to the risk state exceeding the allowable range, enable an electrical parameter adjustment mechanism to obtain the state information of the at least two adjacent memory cells.

[0017] An exemplary embodiment of the present invention further provides a memory control circuit unit, which includes a host interface, a memory interface, and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical cells. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is used to: receive a read instruction from the host system, wherein the read instruction indicates reading data from at least one logical cell, and the at least one logical cell is mapped to a first physical cell among the plurality of physical cells; obtain state information of at least two adjacent memory cells in the first physical cell; determine an electrical parameter offset value corresponding to the at least two adjacent memory cells based on the state information; and send a read instruction sequence based on the electrical parameter offset value, wherein the read instruction sequence indicates reading the first physical cell based on at least one electrical parameter, and the at least one electrical parameter is controlled by the electrical parameter offset value.

[0018] In an exemplary embodiment of the present invention, the at least two adjacent memory cells include a first memory cell and a second memory cell, and the operation of the memory management circuit to determine the electrical parameter offset value corresponding to the at least two adjacent memory cells based on the state information includes: determining grouping information based on the state information of the first memory cell and the state information of the second memory cell; and determining the electrical parameter offset value corresponding to the at least two adjacent memory cells based on the grouping information.

[0019] In an exemplary embodiment of the present invention, the operation of the memory management circuit to obtain the status information of the at least two adjacent memory cells in the first entity cell includes: sending a read instruction sequence to instruct data to be read from the first entity cell; and obtaining the status information of the at least two adjacent memory cells based on the read data.

[0020] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: determine whether the risk state of the rewritable non-volatile memory module exceeds the allowable range; and, in response to the risk state exceeding the allowable range, enable an electrical parameter adjustment mechanism to obtain the state information of the at least two adjacent memory cells.

[0021] Based on the above, after receiving a read instruction from the host system, the status information of at least two adjacent memory cells in the first entity cell to be read can be obtained, and the electrical parameter offset value corresponding to the at least two adjacent memory cells can be determined according to the status information. Subsequently, a read instruction sequence can be sent according to the electrical parameter offset value to indicate reading the first entity cell based on at least one electrical parameter. In particular, the at least one electrical parameter can be controlled by the electrical parameter offset value. This reduces electrical interference between memory cells and improves the stability of reading data from the memory cells. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0026] Figure 5A This is a schematic diagram of a three-dimensional storage cell array according to an exemplary embodiment of the present invention;

[0027] Figure 5B This is a schematic diagram of the equivalent circuit of a three-dimensional storage cell array according to an exemplary embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0029] Figure 7 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0030] Figure 8 This is a schematic diagram of adjacent storage cells according to an exemplary embodiment of the present invention;

[0031] Figure 9 This is a schematic diagram illustrating different storage states of a storage unit according to an exemplary embodiment of the present invention;

[0032] Figure 10A and Figure 10BThis is a schematic diagram illustrating the grouping information of adjacent storage cells corresponding to different state combinations, as shown in an exemplary embodiment of the present invention.

[0033] Figure 10C This is a schematic diagram showing the read level offset values ​​corresponding to different group information, as illustrated in an exemplary embodiment of the present invention;

[0034] Figure 11 This is a flowchart illustrating a data reading method according to an exemplary embodiment of the present invention. Detailed Implementation

[0035] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0036] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0037] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0038] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be connected to the system bus 110.

[0039] In one exemplary embodiment, the host system 11 can be connected to the memory storage device 10 via a data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. Furthermore, the host system 11 can be connected to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0040] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 can be connected to the memory storage device 10 via wired or wireless means.

[0041] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected via the system bus 110 to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0042] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 may be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0043] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0044] Please refer to Figure 3The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0045] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0046] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0047] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 through the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0048] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0049] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0050] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0051] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programmable units, and these physical programmable units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programmable units. If a memory cell can store more than two bits, then physical programmable units on the same word line can be classified into lower physical programmable units and upper physical programmable units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programmable unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programmable unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programmable unit is greater than that of the upper physical programmable unit, and / or the reliability of the lower physical programmable unit is higher than that of the upper physical programmable unit.

[0052] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of storage units to be erased together. For example, a physical erase unit is a physical block.

[0053] In one exemplary embodiment, the memory cells in the rewritable non-volatile memory module 43 are arranged in a three-dimensional array. However, in another exemplary embodiment, the memory cells in the rewritable non-volatile memory module 43 are arranged in a two-dimensional array.

[0054] Figure 5A This is a schematic diagram of a three-dimensional storage cell array according to an exemplary embodiment of the present invention.

[0055] Please refer to Figure 5AThe storage cell array 51 includes multiple storage cells 52 for storing data, multiple bit line groups 531-534, and multiple word line layers 541-548. The bit line groups 531-534 are independent of each other (e.g., separated from each other) and arranged along a first direction (e.g., the X-axis direction). Each bit line group 531-534 includes multiple bit lines 530 that are independent of each other (e.g., separated from each other). The bit lines 530 in each bit line group are arranged along a second direction (e.g., the Y-axis direction) and extend in a third direction (e.g., the Z-axis direction). The word line layers 541-548 are independent of each other (e.g., separated from each other) and stacked along a third direction.

[0056] In one exemplary embodiment, each of the word line layers 541-548 can also be considered as a word line plane. Each memory cell 52 is configured at each intersection between each bit line 530 in the bit line groups 531-534 and the word line layers 541-548.

[0057] It should be noted that, Figure 5A The memory cell array 51 is merely an example; in other exemplary embodiments not mentioned, the total number of memory cells 52, the total number of bit line groups 531-534, and the total number of word line layers 541-548 may differ. Furthermore, in another exemplary embodiment, a bit line group may include more or fewer bit lines, and a word line layer may allow more or fewer bit line groups to pass through. Alternatively, in one exemplary embodiment, the memory cells in the rewritable non-volatile memory module 43 may be configured in other ways, without limitation by the present invention.

[0058] Figure 5B This is a schematic diagram of the equivalent circuit of a three-dimensional storage cell array according to an exemplary embodiment of the present invention.

[0059] Please refer to Figure 5A and Figure 5BTransistor units 521(1) to 521(n) may be located in word line layer 541. Transistor units 522(1) to 522(n) may be located in word line layer 542. Transistor units 523(1) to 523(n) may be located in word line layer 543. Transistor units 528(1) to 528(n) may be located in word line layer 548. One transistor unit may be equivalent to one memory unit. Bit line group 531 may include bit lines 531(1) to 531(n). Bit line 531(1) is connected in series with transistor unit 521(1), transistor unit 522(1), transistor unit 523(1)... and transistor unit 528(1). Bit line 531(2) is connected in series with transistor unit 521(2), transistor unit 522(2), transistor unit 523(2)... and transistor unit 528(2). Bit line 531(3) is connected in series with transistor unit 521(3), transistor unit 522(3), transistor unit 523(3)... and transistor unit 528(3). Similarly, bit line 531(n) is connected in series with transistor unit 521(n), transistor unit 522(n), transistor unit 523(n)... and transistor unit 528(n).

[0060] Word line 551 is located on word line layer 541. Word line 552 is located on word line layer 542. Word line 553 is located on word line layer 543. And so on, with word line 558 located on word line layer 548. Word line 551 is connected in series with transistor units 521(1) to 521(n). Word line 552 is connected in series with transistor units 522(1) to 522(n). Word line 553 is connected in series with transistor units 523(1) to 523(n). Word line 558 is connected in series with transistor units 528(1) to 528(n). It should be noted that... Figure 5B Only show Figure 5A The components of each character line layer are one part, and the rest can be deduced in the same way.

[0061] In this exemplary embodiment, the total number of transistor units connected in series on the same word line can be equal to the total number of memory units contained in a single physical unit. For example, transistor units 521(1) to 521(n) are contained in physical unit 561, transistor units 522(1) to 522(n) are contained in physical unit 562, transistor units 523(1) to 523(n) are contained in physical unit 563, and transistor units 528(1) to 528(n) are contained in physical unit 568. Taking physical unit 561 as an example, when it is desired to read the data stored in physical unit 561, the storage states of transistor units 521(1) to 521(n) can be read simultaneously; furthermore, when it is desired to store data into physical unit 561, transistor units 521(1) to 521(n) can be programmed simultaneously.

[0062] In one exemplary embodiment, the total number of storage units included in each of entity units 561-568 is equal to the total number of storage units included in a single entity programmable unit. That is, in one exemplary embodiment, entity units 561-568 are each considered as a single entity programmable unit. In one exemplary embodiment, at least one of entity units 561-568 may also include multiple entity programmable units.

[0063] Figure 6 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0064] Please refer to Figure 6 The memory control circuit unit 42 includes a memory management circuit 61, a host interface 62, and a memory interface 63. The memory management circuit 61 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 61 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 61 is equivalent to a description of the operation of the memory control circuit unit 42.

[0065] In one exemplary embodiment, the control instructions of the memory management circuit 61 are implemented in firmware format. For example, the memory management circuit 61 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0066] In one exemplary embodiment, the control instructions of the memory management circuit 61 may also be stored in program code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 61 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 61. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0067] In one exemplary embodiment, the control instructions for the memory management circuit 61 can also be implemented in hardware. For example, the memory management circuit 61 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are connected to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 61 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0068] The host interface 62 is connected to the memory management circuit 61. The memory management circuit 61 can communicate with the host system 11 through the host interface 62. The host interface 62 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 61 through the host interface 62. In addition, the memory management circuit 61 can transmit data to the host system 11 through the host interface 62. In this exemplary embodiment, the host interface 62 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 62 can also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0069] Memory interface 63 is connected to memory management circuitry 61 and used to access rewritable non-volatile memory module 43. For example, memory management circuitry 61 can access rewritable non-volatile memory module 43 through memory interface 63. That is, data to be written to rewritable non-volatile memory module 43 is converted into a format acceptable to rewritable non-volatile memory module 43 through memory interface 63. Specifically, if memory management circuitry 61 needs to access rewritable non-volatile memory module 43, memory interface 63 transmits a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated by memory management circuitry 61 and transmitted to rewritable non-volatile memory module 43 through memory interface 63. These instruction sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0070] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 64, a buffer memory 65, and a power management circuit 66.

[0071] Error checking and correction circuit 64 is connected to memory management circuit 61 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 61 receives a write command from host system 11, error checking and correction circuit 64 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 61 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 61 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 64 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0072] Buffer memory 65 is connected to memory management circuit 61 and is used to cache data. Power management circuit 66 is connected to memory management circuit 61 and is used to control the power supply of memory storage device 10.

[0073] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 6 The memory management circuit 61 may include a flash memory management circuit.

[0074] Figure 7 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0075] Please refer to Figure 7 The memory management circuit 61 can logically group the physical cells 710(0) to 710(B) in the rewritable non-volatile memory module 43 to the storage area 701 and the spare area 702.

[0076] Entity cells 710(0) to 710(A) in storage area 701 are used to store user data (e.g., from...) Figure 1 The host system 11 contains user data. For example, entity units 710(0) to 710(A) in storage area 701 may store valid and / or invalid data. Entity erase units 710(A+1) to 710(B) in free area 702 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to free area 702. In addition, entity units (or entity units that do not store valid data) in free area 702 may be erased. When new data is written, one or more entity units may be retrieved from free area 702 to store this new data. In an exemplary embodiment, free area 702 is also referred to as a free pool.

[0077] The memory management circuit 61 can configure logic units 712(0) to 712(C) to map physical units 710(0) to 710(A) in memory area 701. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logic unit may also correspond to a logical programmable unit or consist of multiple consecutive or non-consecutive logical addresses.

[0078] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data currently stored in this entity unit includes valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data currently stored in this entity unit is invalid data.

[0079] The memory management circuit 61 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and physical units in at least one logic-to-entity mapping table. Figure 1 When the host system 11 wants to read data from or write data to the memory storage device 10, the memory management circuit 61 can access the rewritable non-volatile memory module 43 according to the information in the logic-to-entity mapping table, so as to store data in or read data from the rewritable non-volatile memory module 43.

[0080] The memory management circuit 61 can be from Figure 1 The host system 11 receives a read instruction. This read instruction may instruct data to be read from at least one logical unit. The at least one logical unit may be mapped to at least one physical unit (also referred to as a first physical unit) in the rewritable non-volatile memory module 43. For example, the first physical unit may include Figure 7 At least one of the entity units 710(0) to 710(A) in the text.

[0081] The memory management circuit 61 can obtain the state information of at least two adjacent memory cells in the first physical cell. This state information can reflect the voltage range corresponding to the respective critical voltage of each of the at least two adjacent memory cells.

[0082] In one exemplary embodiment, the at least two adjacent memory cells may include a first memory cell and a second memory cell. The first memory cell and the second memory cell may be located on different adjacent bit lines in the rewritable non-volatile memory module 43. Furthermore, the total number of second memory cells may be one or more, as long as they are physically adjacent to the first memory cells (or in physical space).

[0083] The memory management circuit 61 can determine one or more electrical parameter offset values ​​corresponding to the at least two adjacent memory cells based on the status information. For example, the electrical parameter offset values ​​may include a read level offset value, a conduction voltage offset value, or a combination thereof. The memory management circuit 61 can then send one or more read instruction sequences based on these electrical parameter offset values. The read instruction sequences may instruct the reading of a first physical cell based on at least one electrical parameter to obtain the data indicated by the read instruction. In particular, the at least one electrical parameter may be controlled (e.g., determined, updated, or adjusted) by the electrical parameter offset value. For example, the electrical parameter may include a read voltage level, a conduction voltage, or a combination thereof.

[0084] In one exemplary embodiment, the electrical parameter offset value may include a read level offset value. This read level offset value can be used to control (e.g., determine, update, or adjust) the read voltage level applied to the first memory cell during data reading from the first memory cell. Therefore, according to the read instruction sequence, during data reading from the first memory cell, the rewritable non-volatile memory module 43 can adjust the read voltage level corresponding to the first memory cell based on the read level offset value and apply the adjusted read voltage level to the first memory cell. This improves the accuracy of the data read from the first memory cell.

[0085] In one exemplary embodiment, the electrical parameter offset value may also include a conduction voltage offset value. This conduction voltage offset value can be used to control (e.g., determine, update, or adjust) the conduction voltage applied to the second memory cell during data reading from the first memory cell. Therefore, according to the read instruction sequence, during data reading from the first memory cell, the rewritable non-volatile memory module 43 can adjust the conduction voltage corresponding to the second memory cell based on the conduction voltage offset value and apply the adjusted conduction voltage to the second memory cell. This improves the accuracy of the data read from the first memory cell.

[0086] Figure 8 This is a schematic diagram of adjacent storage cells according to an exemplary embodiment of the present invention.

[0087] Please refer to Figure 8Entity unit 861 includes storage units 821(1) to 821(n), entity unit 862 includes storage units 822(1) to 822(n), and entity unit 863 includes storage units 823(1) to 823(n). In a direction parallel to the word line plane, storage units 821(1) to 821(n) are connected in series via word line 851, storage units 822(1) to 822(n) are connected in series via word line 852, and storage units 823(1) to 823(n) are connected in series via word line 853. Furthermore, bit line 831(1) is connected in series with memory cells 821(1), 822(1), and 823(1); bit line 831(2) is connected in series with memory cells 821(2), 822(2), and 823(2); and bit line 831(3) is connected in series with memory cells 821(3), 822(3), and 823(3). Similarly, bit line 831(n) is connected in series with memory cells 821(n), 822(n), and 823(n). Moreover, bit lines 831(1) to 831(n) belong to the same bit line group.

[0088] exist Figure 8 In an exemplary embodiment, bit line 831(i) is adjacent to bit lines 831(i-1) (if present) and 831(i+1) (if present). Therefore, storage cell 821(i) is adjacent to storage cells 821(i-1) (if present) and 821(i+1) (if present), storage cell 822(i) is adjacent to storage cells 822(i-1) (if present) and 822(i+1) (if present), and storage cell 823(i) is adjacent to storage cells 823(i-1) (if present) and 823(i+1) (if present). Alternatively, assuming storage cell 821(i) is the first storage cell, the second storage cell may include storage cells 821(i-1) and / or 821(i+1). Or, assuming storage cell 822(i) is the first storage cell, the second storage cell may include storage cells 822(i-1) and / or 822(i+1). Alternatively, assuming that storage cell 823(i) is the first storage cell, the second storage cell may include storage cells 823(i-1) and / or 823(i+1).

[0089] by Figure 8 For example, assume the first entity unit is entity unit 861 and the first storage unit is storage unit 821(i). In response to... Figure 1 The host system 11 receives a read command, and the status information of adjacent memory cells 821(i), 821(i-1) (if present), and 821(i+1) (if present) can be obtained. Based on this status information, the memory management circuit 61 can determine one or more electrical parameter offset values ​​corresponding to memory cells 821(i), 821(i-1) (if present), and 821(i+1) (if present).

[0090] In one exemplary embodiment, the determined electrical parameter offset value includes a read level offset value corresponding to memory cell 821(i). Memory management circuitry 61 can send a read instruction sequence to rewritable non-volatile memory module 43 based on this read level offset value. This read instruction sequence can be used to instruct rewritable non-volatile memory module 43 to read data from physical cell 861. In particular, this read instruction sequence can instruct rewritable non-volatile memory module 43 to adjust the read voltage level corresponding to memory cell 821(i) based on the read level offset value and apply the adjusted read voltage level to memory cell 821(i) during data reading from physical cell 861 (or memory cell 821(i)). This improves the accuracy of data read from memory cell 821(i).

[0091] In one exemplary embodiment, the determined electrical parameter offset value may further include an on-voltage offset value corresponding to memory cells 821(i-1) (if present) and / or 821(i+1) (if present). The memory management circuit 61 may send a read instruction sequence to the rewritable non-volatile memory module 43 based on this on-voltage offset value. This read instruction sequence may be used to instruct the rewritable non-volatile memory module 43 to read data from physical cell 861. In particular, this read instruction sequence may instruct the rewritable non-volatile memory module 43, during data reading from physical cell 861 (or memory cell 821(i)), to adjust the on-voltage corresponding to memory cells 821(i-1) (if present) and / or 821(i+1) (if present) based on the on-voltage offset value and apply the adjusted on-voltage to memory cells 821(i-1) (if present) and / or 821(i+1) (if present). This also improves the accuracy of the data read from storage unit 821(i).

[0092] Figure 9 This is a schematic diagram illustrating different storage states of a storage unit according to an exemplary embodiment of the present invention.

[0093] Please refer to Figure 9Taking a TLC NAND flash memory as an example, the storage state of each memory cell in the first physical cell can be one of states 901 to 908. States 901 to 908 correspond to different voltage ranges. For example, if the storage state of a memory cell is state 901, this memory cell may currently be used to store bit "111", and the storage state of this memory cell can be represented by the state information "Er". If the storage state of a memory cell is state 902, this memory cell may currently be used to store bit "110", and the storage state of this memory cell can be represented by the state information "A". If the storage state of a memory cell is state 903, this memory cell may currently be used to store bit "101", and the storage state of this memory cell can be represented by the state information "B". If the storage state of a memory cell is state 904, this memory cell may currently be used to store bit "100", and the storage state of this memory cell can be represented by the state information "C". If the storage state of a certain storage cell is state 905, then this storage cell may currently be used to store bit "011", and the storage state of this storage cell can be represented by state information "D". If the storage state of a certain storage cell is state 906, then this storage cell may currently be used to store bit "010", and the storage state of this storage cell can be represented by state information "E". If the storage state of a certain storage cell is state 907, then this storage cell may currently be used to store bit "001", and the storage state of this storage cell can be represented by state information "F". Furthermore, if the storage state of a certain storage cell is state 908, then this storage cell may currently be used to store bit "000", and the storage state of this storage cell can be represented by state information "G". In addition, if the rewritable non-volatile memory module 406 is an MLC NAND flash memory or other types of flash memory, the possible storage states of each storage cell in the first entity unit can be changed accordingly, and the present invention does not impose any limitations. Furthermore, the bit value corresponding to each storage state can also be adjusted according to practical needs, and this invention does not impose any restrictions.

[0094] In one exemplary embodiment, the memory management circuit 61 can obtain the state information of the first memory cell and the second memory cell in the first physical unit. Figure 9For example, the status information of the first storage cell can reflect that the storage state of the first storage cell is one of storage states A to G, and the status information of the second storage cell can reflect that the storage state of the second storage cell is one of storage states A to G. For example, the memory management circuit 61 can send a read instruction sequence to the rewritable non-volatile memory module 43 to instruct the rewritable non-volatile memory module 43 to read data from the first physical cell. Based on the data returned by the rewritable non-volatile memory module 43 (e.g., Figure 9 (As shown in the storage bits), the memory management circuit 61 can obtain the state information of the first storage cell and the second storage cell respectively. For example, assuming that the storage bits read from the first storage cell and the second storage cell are "110" and "011" respectively, the memory management circuit 61 can obtain the state information reflecting the storage states of the first storage cell and the second storage cell as "A" and "D" respectively.

[0095] In one exemplary embodiment, the memory management circuit 61 may determine grouping information corresponding to the at least two adjacent memory cells based on the state information of the first memory cell and the state information of the second memory cell. The memory management circuit 61 may then determine electrical parameter offset values ​​corresponding to the at least two adjacent memory cells based on this grouping information.

[0096] Figure 10A and Figure 10B This is a schematic diagram illustrating the grouping information of adjacent storage cells corresponding to different state combinations, as shown in an exemplary embodiment of the present invention. Figure 10C This is a schematic diagram showing the read level offset values ​​corresponding to different group information, as illustrated in an exemplary embodiment of the present invention.

[0097] Please refer to Figure 10A and Figure 10BTable 1001 records the grouping information corresponding to the state combinations of adjacent memory cells located on different bit lines BL(n) and BL(n+1), and Table 1002 records the grouping information corresponding to the state combinations of adjacent memory cells located on different bit lines BL(n) and BL(n-1). For example, suppose the state information of the memory cell located on bit line BL(n) (i.e., the first memory cell), the memory cell located on bit line BL(n+1) (i.e., one of the second memory cells), and the memory cell located on BL(n-1) (i.e., the other of the second memory cells) in the first entity cell are “A”, “Er”, and “D”, respectively. According to Table 1001, the memory management circuit 61 can obtain the grouping information corresponding to the memory cell located on bit line BL(n) and the memory cell located on bit line BL(n+1) as “G0”. Similarly, according to table information 1002, memory management circuit 61 can obtain the grouping information "G1" corresponding to the memory cell located on bit line BL(n) and the memory cell located on bit line BL(n-1).

[0098] Please refer to Figure 10C Table 1003 records the read level offset values ​​corresponding to different grouping information. Continuing with the above example, based on the combination of grouping information "G0 (i.e., BL(n+1) = G0)" and "G1 (i.e., BL(n-1) = G1)", the memory management circuit 61 can refer to Table 1003 to obtain the offset values ​​used to adjust the read voltage level for reading the first memory cell, which are "-2", "-1", "-1", "0", "2", "3", and "1". Here, L0 to L6 correspond to the seven read voltage levels of the TLC NAND flash memory. Taking read voltage level L0 as an example, the offset value corresponding to read voltage level L0 is "-2", indicating that during the reading of the first memory cell, the read voltage level L0 corresponding to the first memory cell will be reduced by a basic adjustment unit of 2 voltages. For example, the read voltage level L0 corresponding to the first memory cell is reduced from the current read voltage level by a basic adjustment unit of 2 voltages.

[0099] Alternatively, taking read voltage level L5 as an example, an offset value of "3" for read voltage level L5 indicates that during the reading of the first memory cell, the read voltage level L5 corresponding to the first memory cell will be increased by a basic adjustment unit of 3 voltages. For example, the read voltage level L5 corresponding to the first memory cell is increased by a basic adjustment unit of 3 voltages from the current read voltage level. By using a read voltage level offset value corresponding to specific group information to correct the read voltage level corresponding to the first memory cell, the accuracy of the data read from the first memory cell can be effectively improved. In another exemplary embodiment, table information 1003 can also be used to record conduction voltage offset values ​​corresponding to different group information, and the present invention is not limited thereto.

[0100] In one exemplary embodiment, if the packet information corresponding to the memory cell on bit line BL(n) and the memory cell on bit line BL(n+1) is "G1", and the packet information corresponding to the memory cell on bit line BL(n) and the memory cell on bit line BL(n-1) is also "G1", then during the reading of data from the first memory cell, the memory management circuit 61 can appropriately increase the on-state voltage of the second memory cell to improve the correctness of the data read from the first memory cell. Furthermore, if the packet information corresponding to the memory cell on bit line BL(n) and the memory cell on bit line BL(n+1) is "G0", and the packet information corresponding to the memory cell on bit line BL(n) and the memory cell on bit line BL(n-1) is also "G0", then during the reading of data from the first memory cell, the memory management circuit 61 can appropriately decrease the on-state voltage of the second memory cell to improve the correctness of the data read from the first memory cell. The specific adjustment method of the on-state voltage can be set according to practical needs, and this invention does not impose any limitations.

[0101] In one exemplary embodiment, the at least two adjacent memory cells may further include memory cells located on adjacent word lines (also referred to as a third memory cell). Figure 8For example, assuming the first memory cell is memory cell 822(2) located on word line 852, the third memory cell may include memory cell 821(2) located on word line 851 and / or memory cell 823(2) located on word line 853. The memory management circuit 61 can determine the electrical parameter offset value corresponding to the at least two adjacent memory cells based on the state information of the second memory cell and / or the third memory cell. The state information of the third memory cell can reflect the voltage range corresponding to the voltage (i.e., the critical voltage) of the third memory cell. For example, depending on the state of the third memory cell, the memory management circuit 61 can dynamically adjust the read voltage level of the first memory cell and / or the on-state voltage of the third memory cell during the reading of the first memory cell. The relevant operational details have been described above and will not be repeated here.

[0102] In one exemplary embodiment, the memory management circuit 61 may enable a dynamic adjustment mechanism for electrical parameters. In this dynamic adjustment mechanism, the memory management circuit 61 may perform the aforementioned operations of determining the electrical parameter offset value corresponding to the adjacent memory cell based on the state information of that adjacent memory cell and sending a read instruction sequence based on that electrical parameter offset value. The relevant operational details have been described above and will not be repeated here. Alternatively, in one exemplary embodiment, the memory management circuit 61 may also disable (i.e., not enable) the dynamic adjustment mechanism for electrical parameters.

[0103] In one exemplary embodiment, the memory management circuitry 61 may determine whether to enable the adjustment mechanism for the electrical parameters based on the current risk status of the rewritable non-volatile memory module 43. For example, the memory management circuitry 61 may obtain the current risk status of the rewritable non-volatile memory module 43 based on at least one evaluation parameter. For example, the evaluation parameter may include various parameters related to the utilization level of at least some physical cells in the rewritable non-volatile memory module 43, such as programmed counts, erase counts, and / or bit error rates. The values ​​of these evaluation parameters may be positively correlated with the utilization level of the at least some physical cells. That is, the larger the values ​​of these evaluation parameters, the higher the utilization level of at least some physical cells in the rewritable non-volatile memory module 43, and the higher the probability that the data read from the rewritable non-volatile memory module 43 contains erroneous bits.

[0104] In one exemplary embodiment, the memory management circuit 61 can determine whether the current risk state of the rewritable non-volatile memory module 43 exceeds the permissible range. For example, the memory management circuit 61 can determine whether the values ​​of one or more evaluation parameters, such as the programmed count, erase count, and / or bit error rate, exceed the corresponding permissible values. If yes, the memory management circuit 61 can determine that the current risk state of the rewritable non-volatile memory module 43 has exceeded the permissible range. If no, the memory management circuit 61 can determine that the current risk state of the rewritable non-volatile memory module 43 has not exceeded the permissible range. In response to the current risk state of the rewritable non-volatile memory module 43 exceeding the permissible range, the memory management circuit 61 can enable the adjustment mechanism of the electrical parameters to improve the stability of reading data from the memory cells. However, if the current risk state of the rewritable non-volatile memory module 43 has not exceeded the permissible range, the memory management circuit 61 can disable the adjustment mechanism of the electrical parameters to reduce the system load.

[0105] Figure 11 This is a flowchart illustrating a data reading method according to an exemplary embodiment of the present invention.

[0106] Please refer to Figure 11 In step S1101, a read instruction is received from the host system, wherein the read instruction indicates reading data from at least one logical unit, and the at least one logical unit is mapped to a first entity unit among the plurality of entity units. In step S1102, status information of at least two adjacent memory units in the first entity unit is obtained. In step S1103, an electrical parameter offset value corresponding to the at least two adjacent memory units is determined based on the status information. In step S1104, a read instruction sequence is sent based on the electrical parameter offset value, wherein the read instruction sequence indicates reading the first entity unit based on at least one electrical parameter, and the at least one electrical parameter is controlled by the electrical parameter offset value.

[0107] However, Figure 11 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 11 Each step can be implemented as multiple pieces of code or circuits; this application does not impose any restrictions. Furthermore, Figure 11 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this case does not impose any restrictions.

[0108] In summary, the exemplary embodiments of the present invention can dynamically adjust the electrical parameter offset values ​​corresponding to at least two adjacent memory cells in the physical cell to be read. Subsequently, the rewritable non-volatile memory module can adjust at least one electrical parameter used to read the first physical cell based on this electrical parameter offset value. This reduces electrical interference between memory cells and improves the stability of reading data from the memory cells.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data reading method, characterized in that, For a rewritable non-volatile memory module, the rewritable non-volatile memory module includes multiple physical units, and the data reading method includes: Receive a read instruction from the host system, wherein the read instruction indicates that data is to be read from at least one logical unit, and the at least one logical unit is mapped to a first entity unit among the plurality of entity units; Obtain the status information of at least two adjacent memory cells in the first entity unit, wherein the at least two adjacent memory cells are located on the same word line; The electrical parameter offset value corresponding to the at least two adjacent memory cells is determined based on the state information; and A read instruction sequence is sent based on the electrical parameter offset value, wherein the read instruction sequence indicates reading the first entity unit based on at least one electrical parameter, and the at least one electrical parameter is controlled by the electrical parameter offset value.

2. The data reading method according to claim 1, wherein the at least two adjacent storage units include a first storage unit and a second storage unit, the first storage unit and the second storage unit being located on different adjacent bit lines in the rewritable non-volatile memory module.

3. The data reading method according to claim 2, wherein the electrical parameter offset value includes a read level offset value, and the read level offset value is used to control the read voltage level applied to the first storage cell during the reading of data from the first storage cell.

4. The data reading method according to claim 2, wherein the electrical parameter offset value includes a conduction voltage offset value, and the conduction voltage offset value is used to control the conduction voltage applied to the second storage cell during data reading from the first storage cell.

5. The data reading method according to claim 1, wherein the state information of the at least two adjacent storage cells reflects the voltage range corresponding to the respective critical voltage of the at least two adjacent storage cells.

6. The data reading method according to claim 1, wherein the at least two adjacent storage units include a first storage unit and a second storage unit, and the step of determining the electrical parameter offset value corresponding to the at least two adjacent storage units based on the state information includes: The grouping information is determined based on the status information of the first storage unit and the status information of the second storage unit; as well as The electrical parameter offset value corresponding to the at least two adjacent memory cells is determined based on the grouping information.

7. The data reading method according to claim 1, wherein the step of obtaining the state information of the at least two adjacent storage units in the first entity unit includes: Send a sequence of read instructions to instruct the reading of data from the first entity unit; as well as The status information of the at least two adjacent storage units is obtained based on the read data.

8. The data reading method according to claim 1 further includes: Determine whether the risk status of the rewritable non-volatile memory module exceeds the permissible range; as well as In response to the risk state exceeding the permissible range, an electrical parameter adjustment mechanism is activated to obtain the state information of the at least two adjacent memory cells.

9. A memory storage device, characterized in that, include: A connection interface unit for connecting to the host system; A rewritable non-volatile memory module comprising multiple physical units; as well as The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: Receive a read instruction from the host system, wherein the read instruction indicates that data is read from at least one logical unit, and the at least one logical unit is mapped to a first entity unit among the plurality of entity units; Obtain the status information of at least two adjacent memory cells in the first entity unit, wherein the at least two adjacent memory cells are located on the same word line; The electrical parameter offset value corresponding to the at least two adjacent memory cells is determined based on the state information; as well as A read instruction sequence is sent based on the electrical parameter offset value, wherein the read instruction sequence indicates reading the first entity unit based on at least one electrical parameter, and the at least one electrical parameter is controlled by the electrical parameter offset value.

10. The memory storage device of claim 9, wherein the at least two adjacent memory cells include a first memory cell and a second memory cell, the first memory cell and the second memory cell being located on different adjacent bit lines in the rewritable non-volatile memory module.

11. The memory storage device of claim 10, wherein the electrical parameter offset value includes a read level offset value, and the read level offset value is used to control the read voltage level applied to the first memory cell during data reading from the first memory cell.

12. The memory storage device of claim 10, wherein the electrical parameter offset value includes a conduction voltage offset value, and the conduction voltage offset value is used to control the conduction voltage applied to the second memory cell during data reading from the first memory cell.

13. The memory storage device of claim 9, wherein the state information of the at least two adjacent memory cells reflects the voltage range corresponding to the respective critical voltage of each of the at least two adjacent memory cells.

14. The memory storage device of claim 9, wherein the at least two adjacent memory cells include a first memory cell and a second memory cell, and the operation of the memory control circuit unit to determine the electrical parameter offset value corresponding to the at least two adjacent memory cells based on the state information includes: The grouping information is determined based on the status information of the first storage unit and the status information of the second storage unit; as well as The electrical parameter offset value corresponding to the at least two adjacent memory cells is determined based on the grouping information.

15. The memory storage device of claim 9, wherein the operation of the memory control circuit unit obtaining the state information of the at least two adjacent memory cells in the first physical unit includes: Send a sequence of read instructions to instruct the reading of data from the first entity unit; as well as The status information of the at least two adjacent storage units is obtained based on the read data.

16. The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to: Determine whether the risk status of the rewritable non-volatile memory module exceeds the permissible range; and In response to the risk state exceeding the permissible range, an electrical parameter adjustment mechanism is activated to obtain the state information of the at least two adjacent memory cells.

17. A memory control circuit unit, characterized in that, include: Host interface, used to connect to the host system; A memory interface for connecting to a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical units; as well as The memory management circuit is connected to the host interface and the memory interface. The memory management circuit mentioned above is used for: Receive a read instruction from the host system, wherein the read instruction indicates that data is read from at least one logical unit, and the at least one logical unit is mapped to a first entity unit among the plurality of entity units; Obtain the status information of at least two adjacent memory cells in the first entity unit, wherein the at least two adjacent memory cells are located on the same word line; The electrical parameter offset value corresponding to the at least two adjacent memory cells is determined based on the state information; as well as A read instruction sequence is sent based on the electrical parameter offset value, wherein the read instruction sequence indicates reading the first entity unit based on at least one electrical parameter, and the at least one electrical parameter is controlled by the electrical parameter offset value.

18. The memory control circuit unit of claim 17, wherein the at least two adjacent memory units include a first memory unit and a second memory unit, the first memory unit and the second memory unit being located on different adjacent bit lines in the rewritable non-volatile memory module.

19. The memory control circuit unit of claim 18, wherein the electrical parameter offset value includes a read level offset value, and the read level offset value is used to control the read voltage level applied to the first memory cell during data reading from the first memory cell.

20. The memory control circuit unit of claim 18, wherein the electrical parameter offset value includes a conduction voltage offset value, and the conduction voltage offset value is used to control the conduction voltage applied to the second memory cell during data reading from the first memory cell.

21. The memory control circuit unit of claim 17, wherein the state information of the at least two adjacent memory cells reflects the voltage range corresponding to the respective critical voltage of each of the at least two adjacent memory cells.

22. The memory control circuit unit of claim 17, wherein the at least two adjacent memory cells include a first memory cell and a second memory cell, and the operation of the memory management circuit determining the electrical parameter offset value corresponding to the at least two adjacent memory cells based on the state information includes: The grouping information is determined based on the status information of the first storage unit and the status information of the second storage unit; as well as The electrical parameter offset value corresponding to the at least two adjacent memory cells is determined based on the grouping information.

23. The memory control circuit unit of claim 17, wherein the operation of the memory management circuit obtaining the state information of the at least two adjacent memory cells in the first entity unit includes: Send a sequence of read instructions to instruct the reading of data from the first entity unit; as well as The status information of the at least two adjacent storage units is obtained based on the read data.

24. The memory control circuit unit of claim 17, wherein the memory management circuit is further configured to: Determine whether the risk status of the rewritable non-volatile memory module exceeds the permissible range; and In response to the risk state exceeding the permissible range, an electrical parameter adjustment mechanism is activated to obtain the state information of the at least two adjacent memory cells.

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