High-voltage signal generating circuit, programming system and method for preventing information leakage

Abstract

The present invention provides a high-voltage signal generating circuit, a programming system, and a method for preventing information leakage, comprising: a high-voltage signal generating module that generates a high-voltage signal and outputs a comparison result between the high-voltage signal value and a preset value; a control module that generates a feedback control signal based on the comparison result; a feedback current generating module that generates a corresponding feedback current based on the feedback control signal and input data; and a current feedback module that feeds the feedback current back to the output terminal of the high-voltage signal based on the control signal. When applied to non-volatile memory, the present invention eliminates the need for additional timing requirements, resulting in clear and consistent non-volatile memory operation timing and excellent compatibility. By only adding a relatively small logic circuit, no additional algorithm circuit is required to process input data, reducing chip design complexity, optimizing chip area, and further reducing product R&D costs.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a high-voltage signal generating circuit, and a programming system and method for preventing information leakage. Background Art

[0002] With increasing data throughput and the need for low power consumption, the demand for memory in system-on-chip (SoC) systems is increasing. It is predicted that by 2025, approximately 90% of silicon chip area will be occupied by memory devices with various functions, making embedded memory a key factor in the overall system. Non-volatile memory (NVM), known for its ability to maintain data integrity during power outages, is becoming an increasingly important component of embedded memory. It plays a positive role in improving system performance, enhancing chip reliability, and reducing costs and power consumption. NVM typically stores program code and application data. Due to the wide range of SoC applications, NVM must support multiple erase and write capabilities to accommodate the rewriting of different program code and application data to meet the actual needs of different applications. Since applications and application data are often intellectual property data packets, preventing data leakage during data exchange within NVM is becoming an increasingly pressing design requirement. Data interaction in non-volatile memory usually occurs during the data writing and data reading stages. Since the data reading time width is generally in the nanosecond level, and the data writing time width is longer than the data reading time width, generally in the microsecond or millisecond level, data information in the data writing stage is more easily monitored by a third party. Therefore, it is of great practical significance to add anti-data information leakage methods during the data writing process of non-volatile memory.

[0003] Non-volatile memory usually uses the amount of charge stored in the dielectric layer of the MOS tube to change the MOS threshold voltage, thereby changing the conduction characteristics of the MOS tube and then representing the written data. Figure 1 As shown, hot electron injection is widely used in programming non-volatile memory cells. A high-voltage bias signal is typically applied to the drain of the device. Electrons at the source are accelerated toward the drain by the transverse electric field. Upon reaching the pinch-off region, the high electric field rapidly accelerates the electrons. Some of these electrons, under the influence of the longitudinal electric field (gate voltage), penetrate the SiO2 dielectric layer and are injected into the floating gate. The advantage of hot electron injection is that it does not impose significant stress on the thin oxide layer between the floating gate and the substrate, resulting in high reliability after repeated operations and short programming times, typically in the microsecond range. However, the disadvantage is the high current load generated by the high-voltage signal, typically generated by the charge pump built into the non-volatile memory. This high current load results in high power consumption in the charge pump, which in turn results in high power consumption during erase and write operations for the entire circuit.

[0004] right Figure 1The memory cell is programmed using hot electron injection. Assuming that when writing data "1", the programming current is 10uA / bit, and when writing data "0", the programming current is theoretically 0uA / bit; the charge pump power consumption information under 32-bit wide data writing conditions under different data formats is shown in Table 1. The charge pump efficiency formula is: (V pp ×I Vpp ) / (V pwr ×I pwr )=η, where Vpp is the voltage of the output high voltage signal, which is generally 10V; I Vpp is the output high voltage signal current load; Vpwr is the power supply voltage, generally 1.5V. Usually the charge pump efficiency η is about 30%. Based on the above formula, the power supply current load Ipwr can be calculated.

[0005]

[0006] Table 1

[0007] As can be seen from Table 1, there are significant differences in power consumption when writing different data formats. Therefore, when a third party monitors power consumption, the number of "0" and "1" in the data format can be roughly calculated based on the different power consumption information. This provides a definite data information clue for secondary decryption of the data, which may lead to the leakage of intellectual property applications and application data information. Therefore, it is very necessary to add a data writing method to prevent data information leakage in the design of non-volatile memory.

[0008] In the prior art, a common method for writing data in a non-volatile memory to prevent information leakage is to add a digital logic module corresponding to a specific encryption algorithm to the non-volatile memory. When data needs to be written to the non-volatile memory, the module converts the original data to be written each time into new data with a relatively balanced "0" and "1" through an algorithm, thereby causing the charge pump power consumption to be relatively balanced during each programming and not causing large fluctuations. In this way, during the writing process of different data formats, even if a third party monitors the power consumption of the power supply, the difference in the power consumption information is not obvious, and the specific data format cannot be derived based on the different power consumption information.

[0009] However, the above method requires adding a block of digital logic to map a specific algorithm inside the non-volatile memory, which increases the area of ​​the eflash IP. Moreover, when writing data, new data needs to be generated through this digital logic module, and when reading, the read data also needs to be restored to the original data through this digital logic module, which increases the complexity of the eflash operation timing. Taking these two points into consideration, the existing anti-data information leakage method increases the complexity of chip use and chip area, further increases product R&D costs, and reduces the market competitiveness of the eflash IP.

[0010] Therefore, how to reduce the complexity of chip use, reduce chip area, and reduce R&D costs while preventing data information leakage has become one of the urgent problems to be solved by those skilled in the art. Summary of the Invention

[0011] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a high-voltage signal generating circuit, a programming system and method for preventing information leakage, which are used to solve the problems of high chip usage complexity, large chip area occupied, and high product R&D costs in the prior art.

[0012] To achieve the above-mentioned and other related objectives, the present invention provides a high-voltage signal generating circuit, which at least includes:

[0013] High voltage signal generating module, control module, feedback current generating module and current feedback module;

[0014] The high-voltage signal generating module is used to generate a high-voltage signal for controlling the storage unit to write data, and output a comparison result between the value of the high-voltage signal and a preset value;

[0015] The control module is connected to the output end of the high-voltage signal generating module and generates a feedback control signal based on the comparison result; when the value of the high-voltage signal is less than the preset value, the feedback control signal controls the feedback current generating module and the current feedback module to stop working; when the value of the high-voltage signal is greater than the preset value, the feedback control signal controls the feedback current generating module and the current feedback module to work normally;

[0016] The feedback current generating module is connected to the output end of the control module and receives input data, and generates a corresponding feedback current based on the feedback control signal and the input data;

[0017] The current feedback module is connected to the control module and the output end of the feedback current generating module, and feeds back the feedback current to the output end of the high voltage signal based on the control signal.

[0018] Optionally, the high-voltage signal generating module is implemented by a charge pump module.

[0019] More optionally, the high-voltage signal generating module includes a first AND logic unit, a charge pump unit, a feedback enabling unit and a capacitor;

[0020] The first AND logic unit receives the high voltage enable signal, the first clock signal and the output signal of the feedback enable unit, and is used to generate a second clock signal;

[0021] The charge pump unit is connected to the output end of the first AND logic unit and generates the high voltage signal based on the second clock signal;

[0022] The feedback enabling unit is connected to the output end of the charge pump unit, compares the value of the high voltage signal with a preset value, and obtains a comparison result;

[0023] The capacitor is connected to the output end of the charge pump unit.

[0024] Optionally, the control module includes a NAND logic unit, a latch unit, a second AND logic unit and an inverting logic unit;

[0025] The NAND logic unit receives a data write mode enable signal and a high voltage enable signal, and generates a clear signal when the storage unit is in a write mode and the high voltage signal generating module is working;

[0026] The data terminal of the latch unit receives a high level signal, the clock terminal is connected to the inverted signal of the comparison result, and the reset terminal is connected to the output terminal of the NAND logic unit;

[0027] The input end of the second AND logic unit is connected to the high voltage enable signal and the output end of the latch unit respectively, and outputs an inverse signal of the feedback control signal;

[0028] The inverting logic unit is connected to the output end of the second AND logic unit and outputs the feedback control signal.

[0029] Optionally, the feedback current generating module includes N feedback current generating units, each feedback current generating unit receives the feedback control signal and respectively receives the corresponding bit signal of the input data, and the output ends of each feedback current generating unit are connected together to output the feedback current; wherein N is the bit width of the input data, and N is greater than or equal to 1.

[0030] More optionally, the feedback current generating unit includes a NOR logic unit, a reference current, a first NMOS transistor and a first PMOS transistor;

[0031] The input end of the NOR logic unit is connected to the feedback control signal and the corresponding bit signal of the input data, and the output end is connected to the gate of the first NMOS transistor;

[0032] One end of the reference current is grounded, and the other end is connected to the source of the first NMOS transistor;

[0033] The drain and gate of the first PMOS transistor are connected to the drain of the first NMOS transistor, the source is connected to the power supply voltage, and the gate of the first PMOS transistor serves as an output end.

[0034] More optionally, the amplitude of the reference current simulates a programming current of a memory cell when data “1” is written.

[0035] More optionally, the current feedback module mirrors the feedback current and feeds back a current value corresponding to the input data to the high-voltage signal.

[0036] More optionally, the current feedback module includes second and third PMOS transistors and second, third, fourth, fifth, sixth, seventh, and eighth NMOS transistors;

[0037] The source of the second PMOS transistor is connected to the power supply voltage, and the gate is connected to the output end of the feedback current generating module;

[0038] The source of the third PMOS transistor is connected to the power supply voltage, the gate is connected to the inverse signal of the feedback control signal, and the drain is connected to the gate of the second PMOS transistor;

[0039] The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, the gate is connected to the inverse signal of the feedback control signal, and the source is connected to the drain of the third NMOS transistor;

[0040] The sources of the third NMOS transistor and the fourth NMOS transistor are grounded, and the gates are connected together;

[0041] The source of the fifth NMOS transistor is grounded, the gate is connected to the feedback control signal, and the drain is connected to the gates of the third NMOS and the fourth NMOS;

[0042] The source of the sixth NMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate and drain are connected to the source of the seventh NMOS transistor;

[0043] The gate and drain of the seventh NMOS transistor are connected to the source of the eighth NMOS transistor;

[0044] The gate and drain of the eighth NMOS transistor serve as output terminals of the current feedback module.

[0045] To achieve the above-mentioned and other related objectives, the present invention provides a programming system for preventing information leakage, the programming system for preventing information leakage comprising at least:

[0046] Memory and the above-mentioned high-voltage signal generating circuit;

[0047] The high-voltage signal generating circuit provides the memory with a high-voltage signal required for programming.

[0048] Optionally, the memory includes a storage array consisting of a plurality of non-volatile storage units.

[0049] To achieve the above-mentioned and other related objectives, the present invention provides a programming method for preventing information leakage, the programming method for preventing information leakage at least comprising:

[0050] In the write mode, a high voltage signal is generated, and when the value of the high voltage signal is less than a preset value, the high voltage signal is gradually increased;

[0051] When the value of the high-voltage signal is greater than the preset value, the high-voltage signal is maintained at the preset value, and a feedback current is generated based on the input data, and the feedback current is fed back to the high-voltage signal output terminal to compensate for the difference in the high-voltage signal load current caused by the different input data formats;

[0052] The high voltage signal is applied to the storage unit to control the storage unit to implement data writing.

[0053] Optionally, the programming method for preventing information leakage includes: the bit width of the input data is N, N is greater than or equal to 1, and corresponding branch currents are generated based on each bit signal of the input data, and the sum of the branch currents constitutes the feedback current; wherein, if the corresponding bit of the input data is "0", a branch current equal to the programming current of the storage unit when the data "1" is written is provided, and if the corresponding bit of the input data is "1", no current is provided.

[0054] As described above, the high-voltage signal generating circuit, the programming system and the method for preventing information leakage of the present invention have the following beneficial effects:

[0055] 1. The high-voltage signal generating circuit, information leakage prevention programming system and method of the present invention are applied to non-volatile memory without adding additional timing requirements. The operation timing of the non-volatile memory is clear and has good compatibility.

[0056] 2. The high-voltage signal generating circuit, information leakage prevention programming system and method of the present invention only add a smaller-scale logic circuit, and do not need to add additional algorithm circuits to process input data, thereby reducing the complexity of chip design, optimizing the chip area, and further reducing the product R&D cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a schematic diagram showing the programming principle of the hot electron injection method in the prior art.

[0058] Figure 2 Shown is a structural schematic diagram of the high-voltage signal generating circuit of the present invention.

[0059] Figure 3 Shown is a schematic structural diagram of the programming system for preventing information leakage of the present invention.

[0060] Component number description

[0061] 1 High-voltage signal generation circuit

[0062] 11. High voltage signal generation module

[0063] 111 First AND Logic Unit

[0064] 112 charge pump units

[0065] 113 Feedback enable unit

[0066] 12 Control Module

[0067] 121 NAND logic unit

[0068] 122 latch units

[0069] 123 Second AND logic unit

[0070] 124 Inverting Logic Unit

[0071] 125 Inverter

[0072] 13 Feedback current generation module

[0073] 131 OR logic unit

[0074] 14 Current Feedback Module

[0075] 2 Memory DETAILED DESCRIPTION

[0076] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0077] See also Figures 2 and 3 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0078] Example 1

[0079] This embodiment provides a high-voltage signal generating circuit 1, which includes:

[0080] A high-voltage signal generating module 11 , a control module 12 , a feedback current generating module 13 and a current feedback module 14 .

[0081] like Figure 2 As shown, the high-voltage signal generating module 11 is used to generate a high-voltage signal VPOS for controlling the storage unit to write data, and output a comparison result CLKEN between the value of the high-voltage signal VPOS and a preset value.

[0082] Specifically, in this embodiment, the high-voltage signal generating module 11 is implemented using a charge pump module. In actual use, any circuit structure that can generate a high-voltage signal is applicable to the present invention. As an example, the high-voltage signal generating module 11 includes a first AND logic unit 111, a charge pump unit 112, a feedback enabling unit 113, and a capacitor CL.

[0083] More specifically, the first AND logic unit 111 receives the high-voltage enable signal CPEN, the first clock signal CLKIN and the output signal of the feedback enable unit 113 (i.e., the comparison result CLKEN) to generate the second clock signal CLKPOS; when the high-voltage enable signal CPEN and the comparison result CLKEN are high, the first AND logic unit 111 outputs the second clock signal CLKPOS based on the first clock signal CLKIN.

[0084] More specifically, the charge pump unit 112 is connected to the output of the first AND logic unit 111 and generates the high-voltage signal VPOS based on the second clock signal CLKPOS. In this example, the charge pump unit 112 includes a multi-stage charge pump. In actual use, a single-stage charge pump may be used, and the present embodiment is not limited thereto. The feedback enable unit 113 is connected to the output of the charge pump unit 112 and compares the value of the high-voltage signal VPOS with a preset value to obtain a comparison result CLKEN. In this example, the feedback enabling unit 113 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a comparator CMP, which are sequentially connected in series between the output end of the charge pump unit 112 and the reference ground; the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 divide the high-voltage signal VPOS to obtain a divided voltage signal Vcomp; the inverting input end of the comparator CMP is connected to the divided voltage signal Vcomp, and the non-inverting input end is connected to a reference signal Vref, so as to obtain the comparison result CLKEN; when the value of the high-voltage signal VPOS is less than a preset value, the comparison result CLKEN is a high level; when the value of the high-voltage signal VPOS is greater than the preset value, the comparison result CLKEN is a low level.

[0085] It should be noted that, in actual use, the polarity of the input terminal of the comparator CMP and the input signal can be exchanged, and the logical relationship can be adjusted by an inverter, as long as the logic of the present invention can be implemented. This is not limited to this embodiment. Any circuit structure that can determine the relationship between the high-voltage signal VPOS and the preset value is applicable to the present invention, and is not limited to this embodiment.

[0086] More specifically, the capacitor CL is connected to the output terminal of the charge pump unit 112 for storing or stabilizing the high voltage signal VPOS. As another embodiment of the present invention, the high voltage signal generating module 11 further includes a fifth resistor RL.

[0087] like Figure 2 As shown, the control module 12 is connected to the output end of the high-voltage signal generating module 11, and generates a feedback control signal ENb based on the comparison result CLKEN; when the value of the high-voltage signal VPOS is less than the preset value, the feedback control signal ENb controls the feedback current generating module 13 and the current feedback module 14 to stop working; when the value of the high-voltage signal VPOS is greater than the preset value, the feedback control signal ENb controls the feedback current generating module 13 and the current feedback module 14 to work normally.

[0088] Specifically, in this embodiment, the control module 12 includes a NAND logic unit 121 , a latch unit 122 , a second AND logic unit 123 and an inverting logic unit 124 .

[0089] More specifically, the NAND logic unit 121 receives the data write mode enable signal PRGEN and the high voltage enable signal CPEN, and generates a clear signal CLR (active high) when the storage unit is in the write mode and the high voltage signal generating module 11 is working.

[0090] More specifically, the data terminal d of the latch unit 122 receives a high-level signal (as an example, the power supply voltage VDD is used), the clock terminal ck is connected to the inverted signal CLKENb of the comparison result CLKEN (as an example, the inverted signal is obtained through the inverter 125), and the clear terminal clr is connected to the output terminal of the NAND logic unit 121, and the output signal Latchout.

[0091] More specifically, the input end of the second AND logic unit 123 is respectively connected to the high-voltage enable signal CPEN and the output end of the latch unit 122, and outputs the inverse signal EN of the feedback control signal ENb; when either the high-voltage enable signal CPEN or the output signal Latchout of the latch unit is at a low level, the output is a low level; when the high-voltage enable signal CPEN and the output signal Latchout of the latch unit are both at a high level, the output is a high level.

[0092] More specifically, the inverting logic unit 124 is connected to the output end of the second AND logic unit 123 and outputs the feedback control signal ENb.

[0093] It should be noted that, in actual use, any circuit structure in which the feedback control signal ENb can control the feedback current generating module 13 and the current feedback module 14 to stop working when the value of the high-voltage signal VPOS is less than the preset value; and the feedback control signal ENb can control the feedback current generating module 13 and the current feedback module 14 to work normally when the value of the high-voltage signal VPOS is greater than the preset value is applicable to the present invention, and is not limited to this embodiment.

[0094] like Figure 2 As shown, the feedback current generating module 13 is connected to the output end of the control module 12 and receives input data Din, and generates a corresponding feedback current based on the feedback control signal ENb and the input data Din.

[0095] Specifically, in this embodiment, the feedback current generating module 13 includes N feedback current generating units, each feedback current generating unit receives the feedback control signal and respectively receives the corresponding bit signal of the input data Din, and the output ends of the feedback current generating units are connected together to output the feedback current; wherein N is the bit width of the input data Din, and N is greater than or equal to 1; as an example, N takes a value of 32.

[0096] More specifically, as an example, the feedback current generating unit includes a NOR logic unit 131, a reference current Ibias, a first NMOS transistor N1, and a first PMOS transistor P1. The input of the NOR logic unit 131 is connected to the feedback control signal ENb and the corresponding bit signal of the input data Din, and the output is connected to the gate of the first NMOS transistor N1. When the feedback control signal ENb and the corresponding bit signal of the input data Din are both low, the NOR logic unit 131 outputs a high level; otherwise, it outputs a low level. One end of the reference current Ibias is grounded, and the other end is connected to the source of the first NMOS transistor N1. As an example, the amplitude of the reference current Ibias simulates (or is equal to) the programming current of the memory cell when writing data "1." The drain and gate of the first PMOS transistor P1 are connected to the drain of the first NMOS transistor N1, and the source is connected to the power supply voltage VDD. The gate of the first PMOS transistor P1 serves as the output.

[0097] like Figure 2As shown, the current feedback module 14 is connected to the output ends of the control module 12 and the feedback current generating module 13 , and feeds back the feedback current to the output end of the high voltage signal VPOS based on the feedback control signal ENb.

[0098] Specifically, the current feedback module 14 mirrors the feedback current and feeds back a current value corresponding to the input data Din to the high-voltage signal VPOS.

[0099] More specifically, as an example, the current feedback module 14 includes a second PMOS transistor P2, a third PMOS transistor P3, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8; the source of the second PMOS transistor P2 is connected to the power supply voltage VDD, and the gate is connected to the output end of the feedback current generating module 13; the source of the third PMOS transistor P3 is connected to the power supply voltage VDD, the gate is connected to the inverse signal EN of the feedback control signal ENb, and the drain is connected to the gate of the second PMOS transistor P2; the drain of the second NMOS transistor P2 is connected to the drain of the second PMOS transistor P2, and the gate is connected The inverse signal EN of the feedback control signal ENb has its source connected to the drain of the third NMOS transistor N3; the sources of the third NMOS transistor N3 and the fourth NMOS transistor N4 are grounded, and their gates are connected together; the source of the fifth NMOS transistor N5 is grounded, its gate is connected to the feedback control signal ENb, and its drain is connected to the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4; the source of the sixth NMOS transistor N6 is connected to the drain of the fourth NMOS transistor N4, and its gate and drain are connected to the source of the seventh NMOS transistor N7; the gate and drain of the seventh NMOS transistor N7 are connected to the source of the eighth NMOS transistor N8; the gate and drain of the eighth NMOS transistor N8 serve as the output end of the current feedback module 14.

[0100] Example 2

[0101] like Figure 3 As shown, this embodiment provides a programming system for preventing information leakage, and the programming system for preventing information leakage includes:

[0102] High voltage signal generating circuit 1 and memory 2.

[0103] like Figure 3 As shown, the high-voltage signal generating circuit 1 provides the memory 2 with a high-voltage signal VPOS required for programming.

[0104] Specifically, the structure and principle of the high-voltage signal generating circuit 1 refer to the first embodiment, which will not be described in detail here.

[0105] like Figure 3 As shown, the memory 2 is used to store data.

[0106] Specifically, the memory includes but is not limited to a storage array composed of multiple storage units, a row decoder, a column decoder, and a readout circuit; as an example, the memory is a non-volatile memory. In actual use, any memory with the technical problems of the present invention is applicable to the present invention and will not be described one by one here.

[0107] Specifically, the high-voltage signal VPOS is applied to the source, gate or drain of the memory cell. The corresponding electrode is selected to apply the high-voltage signal VPOS based on a specific programming method, which will not be described in detail here.

[0108] Example 3

[0109] This embodiment provides a programming method for preventing information leakage, and the programming method for preventing information leakage includes:

[0110] S1) In a write mode, a high voltage signal is generated, and when the value of the high voltage signal is less than a preset value, the high voltage signal is gradually increased.

[0111] S2) When the value of the high-voltage signal is greater than the preset value, the high-voltage signal is maintained at the preset value, and a feedback current is generated based on the input data, and the feedback current is fed back to the high-voltage signal output end to compensate for the difference in the high-voltage signal load current caused by the different input data formats.

[0112] Specifically, in this embodiment, the bit width of the input data is N, N is greater than or equal to 1, and corresponding branch currents are generated based on each bit signal of the input data, and the sum of the branch currents constitutes the feedback current; wherein, if the corresponding bit of the input data is "0", a branch current equal to the programming current of the storage unit when the data "1" is written is provided, and if the corresponding bit of the input data is "1", no current is provided.

[0113] S3) applying the high voltage signal to the storage unit to control the storage unit to write data.

[0114] In this embodiment, the high-voltage signal generating circuit 1 of the first embodiment is used to implement the non-volatile memory. In actual use, any hardware circuit or software code that can implement the method of the present invention is applicable. In this embodiment, the following steps are included:

[0115] 1) When the non-volatile memory is in a data write operation, the data write mode enable signal PRGEN and the high-voltage enable signal CPEN are both high-level signals. When the high-voltage signal VPOS is in the rising phase, the voltage-divided signal Vcomp is lower than the reference voltage Vref, the comparison result CLKEN output by the comparator CMP is high-level, the second clock signal CLKPOS (i.e., the high-voltage clock signal) output by the first AND logic unit 111 is valid, and at the same time, the clock end of the data latch unit 122 in the control module 12 (the inverse signal CLKENb of the comparison result CLKEN) is low-level. The feedback control signal ENb output by the control module 12 is high-level, and its inverse signal EN is low-level. Therefore, the NMOS transistors N1, N3, and N4 in the feedback current generating module 13 and the current feedback module 14 are all in the off state, eliminating the influence of the feedback current during the rising phase of the high-voltage signal VPOS.

[0116] 2) When the high-voltage signal VPOS reaches the rated high voltage (preset value), the voltage-divided signal Vcomp is higher than the reference signal Vref, the comparison result CLKEN output by the comparator CMP is low, the second clock signal CLKPOS (i.e., the high-voltage clock signal) output by the first AND logic unit 111 is invalid, the charge pump unit 112 is in an idle state, the high-voltage signal VPOS is maintained near the rated high-voltage amplitude, and at the same time, the clock terminal of the data latch unit 122 in the control module 12 jumps to a high level, and the data terminal of the latch unit 122 is set to The d input signal (high level) is transmitted to the output terminal Q. The feedback control signal ENb output by the control module 12 is low, and its inverse signal EN is high. This causes the gate signal level of N1 in the 32 feedback current generating units to change accordingly based on the data format of the written data DIN. When the data Din is "1," the first NMOS transistor N1 is in the off state. Conversely, when the data Din is "0," the first NMOS transistor N1 is in the on state, and its current amplitude is the reference current Ibias (the current amplitude of Ibias simulates the programming current of the memory cell when the data "1" is written). This ensures that the conduction current of the second PMOS transistor P2 in the current feedback module 14 matches the DIN data format. Subsequently, through current mirroring, the conduction current of the fourth NMOS transistor N4 in the current feedback module 14 matches the DIN data format. This compensates for differences in the high-voltage signal VPOS load current caused by different DIN data formats.

[0117] As shown in Table 2, the high-voltage signal generating circuit, the programming system and method for preventing information leakage of the present invention are used to write the charge pump power consumption information when 32-bit wide data in different data formats (for example, the ibias current is set to the bitcell programming current of 10uA). As can be seen from the table below, the high-voltage signal generating circuit, the programming system and method for preventing information leakage of the present invention can dynamically adjust the conduction current flowing through the NMOS tube N4 according to the different data formats, ensuring that the load current of the high-voltage signal VPOS remains basically consistent, and there is no obvious difference in power consumption when writing different data formats. Therefore, when a third party monitors the power consumption of the power supply, it is impossible to infer the number of "0" and "1" in different data formats based on different power consumption information, thereby preventing the leakage of applications with intellectual property rights and application data information.

[0118]

[0119] Table 2

[0120] In summary, the present invention provides a high-voltage signal generating circuit, a programming system and method for preventing information leakage, comprising: a high-voltage signal generating module, a control module, a feedback current generating module and a current feedback module; the high-voltage signal generating module is used to generate a high-voltage signal for controlling the storage unit to write data, and output a comparison result between the value of the high-voltage signal and a preset value; the control module is connected to the output end of the high-voltage signal generating module, and generates a feedback control signal based on the comparison result; when the value of the high-voltage signal is less than the preset value, the feedback control signal controls the feedback current generating module and the current feedback module to stop working; when the value of the high-voltage signal is greater than the preset value, the feedback control signal controls the feedback current generating module and the current feedback module to work normally; the feedback current generating module is connected to the output end of the control module, and receives input data, and generates a corresponding feedback current based on the feedback control signal and the input data; the current feedback module is connected to the output end of the control module and the feedback current generating module, and feeds back the feedback current to the output end of the high-voltage signal based on the control signal. The high-voltage signal generating circuit, information leakage prevention programming system, and method of the present invention are applied to non-volatile memory. They eliminate the need for additional timing requirements, resulting in clear and consistent non-volatile memory operation timing and excellent compatibility. They only require a relatively small logic circuit, eliminating the need for additional algorithm circuits to process input data. This reduces chip design complexity, optimizes chip area, and further reduces product R&D costs. Therefore, the present invention effectively overcomes the shortcomings of the prior art and possesses high industrial value.

[0121] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A high voltage signal generating circuit, characterized in that: The high-voltage signal generating circuit at least includes: High voltage signal generating module, control module, feedback current generating module and current feedback module; The high-voltage signal generating module is used to generate a high-voltage signal for controlling the storage unit to write data, and output a comparison result between the value of the high-voltage signal and a preset value; The control module is connected to the output end of the high-voltage signal generating module and generates a feedback control signal based on the comparison result; when the value of the high-voltage signal is less than the preset value, the feedback control signal controls the feedback current generating module and the current feedback module to stop working; when the value of the high-voltage signal is greater than the preset value, the feedback control signal controls the feedback current generating module and the current feedback module to work normally; The feedback current generating module is connected to the output end of the control module and receives input data, and generates a corresponding feedback current based on the feedback control signal and the input data; The current feedback module is connected to the control module and the output end of the feedback current generating module, and feeds back the feedback current to the output end of the high voltage signal based on the feedback control signal.

2. The high-voltage signal generating circuit according to claim 1, wherein: The high voltage signal generating module is implemented by a charge pump module.

3. The high-voltage signal generating circuit according to claim 1 or 2, wherein: The high-voltage signal generating module includes a first AND logic unit, a charge pump unit, a feedback enabling unit and a capacitor; The first AND logic unit receives the high voltage enable signal, the first clock signal and the output signal of the feedback enable unit, and is used to generate a second clock signal; The charge pump unit is connected to the output end of the first AND logic unit and generates the high voltage signal based on the second clock signal; The feedback enabling unit is connected to the output end of the charge pump unit, compares the value of the high voltage signal with a preset value, and obtains a comparison result; The capacitor is connected to the output end of the charge pump unit.

4. The high-voltage signal generating circuit according to claim 1, wherein: The control module includes a NAND logic unit, a latch unit, a second AND logic unit and an inverting logic unit; The NAND logic unit receives a data write mode enable signal and a high voltage enable signal, and generates a clear signal when the storage unit is in a write mode and the high voltage signal generating module is working; The data terminal of the latch unit receives a high level signal, the clock terminal is connected to the inverted signal of the comparison result, and the reset terminal is connected to the output terminal of the NAND logic unit; The input end of the second AND logic unit is connected to the high voltage enable signal and the output end of the latch unit respectively, and outputs an inverse signal of the feedback control signal; The inverting logic unit is connected to the output end of the second AND logic unit and outputs the feedback control signal.

5. The high-voltage signal generating circuit according to claim 1, wherein: The feedback current generating module includes N feedback current generating units, each feedback current generating unit receives the feedback control signal and respectively receives the corresponding bit signal of the input data, and the output ends of the feedback current generating units are connected together to output the feedback current; wherein N is the bit width of the input data, and N is greater than or equal to 1.

6. The high-voltage signal generating circuit according to claim 5, wherein: The feedback current generating unit includes a NOR logic unit, a reference current, a first NMOS transistor and a first PMOS transistor; The input end of the NOR logic unit is connected to the feedback control signal and the corresponding bit signal of the input data, and the output end is connected to the gate of the first NMOS transistor; One end of the reference current is grounded, and the other end is connected to the source of the first NMOS transistor; The drain and gate of the first PMOS transistor are connected to the drain of the first NMOS transistor, the source is connected to the power supply voltage, and the gate of the first PMOS transistor serves as an output end.

7. The high-voltage signal generating circuit according to claim 6, wherein: The amplitude of the reference current simulates the programming current of the memory cell when writing data "1".

8. The high-voltage signal generating circuit according to any one of claims 1, 5-7, wherein: The current feedback module mirrors the feedback current and feeds back a current value corresponding to the input data to the high-voltage signal.

9. The high-voltage signal generating circuit according to claim 8, wherein: The current feedback module includes the second and third PMOS transistors and the second, third, fourth, fifth, sixth, seventh and eighth NMOS transistors; The source of the second PMOS transistor is connected to the power supply voltage, and the gate is connected to the output end of the feedback current generating module; The source of the third PMOS transistor is connected to the power supply voltage, the gate is connected to the inverse signal of the feedback control signal, and the drain is connected to the gate of the second PMOS transistor; The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, the gate is connected to the inverse signal of the feedback control signal, and the source is connected to the drain of the third NMOS transistor; The sources of the third NMOS transistor and the fourth NMOS transistor are grounded, and the gates are connected together; The source of the fifth NMOS transistor is grounded, the gate is connected to the feedback control signal, and the drain is connected to the gates of the third NMOS transistor and the fourth NMOS transistor; The source of the sixth NMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate and drain are connected to the source of the seventh NMOS transistor; The gate and drain of the seventh NMOS transistor are connected to the source of the eighth NMOS transistor; The gate and drain of the eighth NMOS transistor serve as output terminals of the current feedback module.

10. A programming system for preventing information leakage, characterized in that: The programming system for preventing information leakage at least includes: A memory and a high-voltage signal generating circuit according to any one of claims 1 to 9; The high-voltage signal generating circuit provides the memory with a high-voltage signal required for programming.

11. A programming method for preventing information leakage, characterized in that: The programming method for preventing information leakage at least includes: In the write mode, a high voltage signal is generated, and when the value of the high voltage signal is less than a preset value, the high voltage signal is gradually increased; When the value of the high-voltage signal is greater than the preset value, the high-voltage signal is maintained at the preset value, and a feedback current is generated based on the input data, and the feedback current is fed back to the high-voltage signal output terminal to compensate for the difference in the high-voltage signal load current caused by the different input data formats; The high voltage signal is applied to the storage unit to control the storage unit to implement data writing.

12. The programming method for preventing information leakage according to claim 11, characterized in that: The programming method for preventing information leakage includes: the bit width of the input data is N, N is greater than or equal to 1, and corresponding branch currents are generated based on each bit signal of the input data, and the sum of the branch currents constitutes the feedback current; wherein, if the corresponding bit of the input data is "0", a branch current equal to the programming current of the storage unit when the data "1" is written is provided, and if the corresponding bit of the input data is "1", no current is provided.

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