Memristor-based multimodal generalization and differentiation associative memory neural network circuit
By designing a memristor-based multimodal generalization and differentiation associative memory neural network circuit, the technical problem of learning and forgetting among multiple neurons was solved, realizing the secondary differentiation of Pavlovian associative memory, enhancing the generalization and differentiation ability of memory, adapting to multiple generalizations and differentiations, and forming long-term memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-03-16
- Publication Date
- 2026-03-06
AI Technical Summary
Existing Pavlovian theories of associative memory cannot fully account for the learning and forgetting processes among multiple neurons, especially regarding the generalization and differentiation laws, which have been poorly studied.
A multimodal generalization and differentiation associative memory neural network circuit based on memristor was designed. Through the associative learning and forgetting process between multiple neurons, the extinction inhibition and differentiation inhibition in forgetting are achieved by using the inhibition module. Combined with logic circuits and synaptic neuron modules, the secondary differentiation of Pavlovian associative memory is realized.
It realizes the associative learning and forgetting process between multiple neurons, enhances the generalization and differentiation ability of associative memory, makes the memory more in line with biological characteristics, adapts to multiple generalizations and differentiations, slows down the forgetting rate, and gradually forms long-term memory.
Smart Images
Figure CN115577758B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of neural network circuits, and more particularly to a multi-mode generalization and differentiation Pavlov associative memory neural network circuit based on memristors. Background Technology
[0002] Memristors are a class of nonlinear circuit elements exhibiting resistive memory behavior, and are considered the fourth fundamental circuit element after resistors, capacitors, and inductors. Memristors show great promise for applications in non-volatile storage, logic operations, artificial neural networks, and chaotic secure communication. The characteristics of memristors are very similar to synapses in biological neurons, making them an important module for mimicking biological learning and memory behaviors.
[0003] Physiologist Pavlov discovered the laws of conditioned reflexes through experiments on canine saliva secretion, including the laws of acquisition, extinction, generalization, and differentiation. The laws of acquisition and extinction correspond to the learning and forgetting processes in associative memory. The learning and forgetting processes between two neurons have been extensively studied and applied. However, research on the laws of acquisition, extinction, generalization, and differentiation between multiple neurons is relatively limited. Summary of the Invention
[0004] To address the technical problem that existing Pavlovian associative memory theories cannot achieve learning and forgetting among multiple neurons, this invention proposes a multi-modal generalization and differentiation associative memory neural network circuit based on memristor. Through the associative learning and forgetting process among multiple neurons, it realizes the secondary differentiation process of Pavlovian associative memory; and through the inhibition module, it realizes extinction inhibition and differentiation inhibition in forgetting.
[0005] To achieve the above objectives, the technical solution of the present invention is implemented as follows: A multi-mode generalization and differentiation associative memory neural network circuit based on memristor, comprising input signal terminals N1-N7, synaptic neuron modules I-VII, inhibition modules I-V, and an output signal terminal. Input signal terminal N1 is connected to synaptic neuron module I; input signal terminals N1 and N2 are connected to synaptic neuron module II via logic circuit I; input signal terminals N1, N2, and synaptic neuron module II are all connected to inhibition module I via logic circuit II; inhibition module I is connected to input signal terminal N3; inhibition module I and input signal terminal N3 are both connected to synaptic neuron module III via logic circuit III; input signal terminals N1 and N4 are both connected to inhibition module II. Inhibition module II and input signal terminal N4 are both connected to synaptic neuron module IV via logic circuit IV; input signal terminals N1 and N2, and synaptic neuron module II are all connected to inhibition module III; inhibition module III and input signal terminal N5 are both connected to synaptic neuron module V via logic circuit V; input signal terminals N1 and N2, and synaptic neuron module II are all connected to inhibition module IV; inhibition module IV and input signal terminal N6 are both connected to synaptic neuron module VI via logic circuit VI; input signal terminals N1 and N2, and synaptic neuron module II are all connected to inhibition module V; inhibition module V and input signal terminal N7 are connected to synaptic neuron module VII via logic circuit VII; synaptic neuron modules I through synaptic neuron module VII are connected to the output signal terminal via an OR gate.
[0006] The synaptic neuron module I includes a first proportional amplifier, with the input signal terminal N1 connected to the first proportional amplifier; the first proportional amplifier is connected to the absolute value module ABS1, and the output terminal of the absolute value module ABS1 is the output signal terminal OUT1, which is connected to an OR gate; the first proportional amplifier includes a resistor R1, an operational amplifier OP1, and a resistor R2, with the output signal terminal OUT1 connected to the resistor R1, the resistor R1 connected to the resistor R2 and the inverting input terminal of the operational amplifier OP1, the resistor R2 and the output terminal of the operational amplifier OP1, the non-inverting input terminal of the operational amplifier OP1 grounded, and the output terminal of the operational amplifier OP1 connected to the input terminal of the absolute value module ABS1.
[0007] The logic circuit I includes a first voltage-controlled unit, a second voltage-controlled unit, an AND gate D1, and a voltage summing unit SUM1. Input signal terminals N1 and N2 are both connected to AND gate D1. The output terminal of AND gate D1 is connected to the first voltage-controlled unit, and input signal terminal N2 is connected to the second voltage-controlled unit. The first and second voltage-controlled units are respectively connected to the two input terminals of the voltage summing unit SUM1. The output terminal of the voltage summing unit SUM1 is connected to the synaptic neuron module II. The first voltage-controlled unit includes a voltage-controlled switch S1. The output terminal of AND gate D1 is connected to the positive input terminal of the voltage-controlled switch S1. The first voltage-controlled switch S1... Each contact is connected to the first input terminal of the voltage summing unit SUM1 and the resistor R3, respectively. The second contact of the voltage-controlled switch S1 is connected to the positive terminal of the power supply V1. The negative terminal of the power supply V1, the resistor R3, and the inverting input terminal of the voltage-controlled switch S1 are all grounded. The second voltage-controlled unit includes a voltage-controlled switch S2. The non-inverting input terminal of the voltage-controlled switch S2 is connected to the input signal terminal N2. The first contact of the voltage-controlled switch S2 is connected to the second input terminal of the voltage summing unit SUM1 and the resistor R4, respectively. The second contact of the voltage-controlled switch S2 is connected to the positive terminal of the power supply V2. The negative terminal of the power supply V2, the resistor R4, and the inverting input terminal of the voltage-controlled switch S2 are all grounded.
[0008] The synaptic neuron module II includes a second proportional amplifier, an absolute value module ABS2, a third proportional amplifier, a first comparator, and a second comparator connected in sequence. The input terminal of the second proportional amplifier is connected to the voltage summation unit SUM1 of logic circuit I, and the output terminal of the second comparator is connected to an OR gate. The second proportional amplifier includes a memristor M1, an operational amplifier OP2, and a resistor R5. The positive terminal of the memristor M1 is connected to the output terminal of the voltage summation unit SUM1 of logic circuit I, and the negative terminal of the memristor M1 is connected to the inverting input terminal of operational amplifier OP2 and the resistor R5. The non-inverting input terminal of operational amplifier OP2 is grounded, and the resistor R5 is connected to the output terminal of operational amplifier OP2. The output terminal of operational amplifier OP2 is connected to the input terminal of absolute value module ABS2, and the output terminal of absolute value module ABS2 is connected to the third proportional amplifier. The third proportional amplifier includes a resistor R6, an operational amplifier OP3, and a resistor R7. The output terminal of absolute value module ABS2 is connected to resistor R6, and the resistor R7 is connected to the input terminal of absolute value module ABS2. 6 is connected to resistor R7 and the inverting input of operational amplifier OP3 respectively. Resistor R7 is connected to the output of operational amplifier OP3. The non-inverting input of operational amplifier OP3 is grounded. The output of operational amplifier OP3 is connected to the first comparator. The second comparator includes operational amplifier OP4. The inverting input of operational amplifier OP4 is connected to the output of operational amplifier OP3. The non-inverting input of operational amplifier OP4 is connected to the positive terminal of power supply V3. The negative terminal of power supply V3 is grounded. The output of operational amplifier OP4 is connected to the second comparator. The second comparator includes NMOS transistor T1. The gate of NMOS transistor T1 is connected to the output of operational amplifier OP4. The drain of NMOS transistor T1 is connected to resistor R8. Resistor R8 is connected to the positive terminal of power supply V4. The source of NMOS transistor T1 is connected to resistor R9. The negative terminal of power supply V4 and resistor R9 are grounded. The drain of NMOS transistor T1 is the output signal terminal OUTⅡ. The output signal terminal OUTⅡ is connected to an OR gate.
[0009] The logic circuit II includes a third comparator, AND gate D2, and NOT gate D5. The input of the third comparator is connected to the output of the absolute value module ABS2 of the synaptic neuron module II. The output of the third comparator and the output of AND gate D1 of logic circuit I are both connected to the input of AND gate D2. The output of AND gate D2 is connected to the input of NOT gate D5. The output of NOT gate D5 is connected to the suppression module I. The suppression module I includes a fourth comparator, AND gate D6, a third voltage-controlled unit, and a fourth proportional amplifier. The output of NOT gate D5 is connected to the input of the fourth comparator. The output and input signal terminal N3 of the fourth comparator are both connected to the input of AND gate D6. The output of AND gate D6 is connected to the third voltage-controlled unit. The third voltage-controlled unit is connected to the fourth proportional amplifier. The output of the fourth proportional amplifier is connected to logic circuit III. The logic circuit III includes a first adder. The system comprises a fifth proportional amplifier, a fourth voltage-controlled unit, a fifth voltage-controlled unit, an NOT gate D3, and an AND gate D4. The input signal terminal N3 is connected to the input terminal of NOT gate D3. The output terminals of NOT gate D3 and AND gate D2 are both connected to the input terminal of AND gate D4. The output terminal of AND gate D4 is connected to the fourth voltage-controlled unit. The input signal terminal N3 is connected to the fifth voltage-controlled unit. The output terminals of the fourth and fifth voltage-controlled units are connected to the first adder. The first adder is connected to the fifth proportional amplifier. The fifth proportional amplifier is connected to the synaptic neuron module III. The synaptic neuron module III includes a sixth proportional amplifier, an absolute value module ABS3, a seventh proportional amplifier, a fifth comparator, and a sixth comparator connected in sequence. The output terminal of the fifth proportional amplifier is connected to the input terminal of the sixth proportional amplifier. The output terminal of the sixth comparator is the output signal terminal OUTIII, which is connected to an OR gate.
[0010] The suppression module II includes a seventh comparator, an AND gate D4, a sixth voltage-controlled unit (VDC), and an eighth proportional amplifier. The seventh comparator is connected to the output of an NOT gate D9. The input of NOT gate D9 is connected to the input signal N1. The output and input signal N4 of the seventh comparator are connected to the input of AND gate D4. The output of AND gate D4 is connected to the input of the sixth VDC. The output of the sixth VDC is connected to the input of the eighth proportional amplifier. The output of the eighth proportional amplifier is connected to logic circuit IV. Logic circuit IV includes a second adder, a ninth proportional amplifier, a seventh VDC, an eighth VDC, an NOT gate D7, and an AND gate D8. The input signal N4 is connected to the input of NOT gate D7. The output terminals of AND gate D2 and AND gate D2 are both connected to the input terminal of AND gate D8. The output terminal of AND gate D8 is connected to the seventh voltage control unit. The input signal terminal N4 is connected to the eighth voltage control unit. The output terminals of the seventh and eighth voltage control units are connected to the second adder. The second adder is connected to the ninth proportional amplifier. The ninth proportional amplifier is connected to the synaptic neuron module IV. The synaptic neuron module IV includes a tenth proportional amplifier, an absolute value module ABS4, an eleventh proportional amplifier, a ninth comparator, and a tenth comparator connected in sequence. The output terminal of the ninth proportional amplifier is connected to the input terminal of the tenth proportional amplifier. The output terminal of the tenth comparator is the output signal terminal OUTⅣ, which is connected to an OR gate.
[0011] The third comparator includes an operational amplifier OP5. The inverting input of the operational amplifier OP5 is connected to the output of the absolute value module ABS2, the non-inverting input of the operational amplifier OP5 is grounded through power supply V5, and the output of the operational amplifier OP5 is connected to one input of the AND gate D2D.
[0012] The fourth comparator includes an NMOS transistor T2 and a PMOS transistor T3. The output of the NOT gate D5 is connected to the gate of the NMOS transistor T2. The drain of the NMOS transistor T2 is connected to the positive terminal of power supply V11 through a resistor R10. The source of the NMOS transistor T2 is connected to the positive terminal of power supply V12. The negative terminals of power supplies V11 and V12 are both grounded. The drain of the NMOS transistor T2 is connected to the gate of the PMOS transistor T3. The drain of the PMOS transistor T3 is connected to the positive terminal of power supply V13 through a resistor R11. The source of the PMOS transistor T3 is connected to the positive terminal of power supply V14. The negative terminals of power supplies V13 and V14 are both grounded. The drain of the PMOS transistor T3 is connected to one input of the AND gate D6.
[0013] The third voltage control unit includes a voltage control switch S5. The output terminal of AND gate D6 is connected to the non-inverting input terminal of voltage control switch S5. The first contact of voltage control switch S5 is connected to the fourth proportional amplifier and resistor R52 respectively. The second contact of voltage control switch S5 is connected to the positive terminal of power supply V15. The negative terminal of power supply V15, resistor R52 and the inverting input terminal of voltage control switch S5 are all grounded.
[0014] The fourth proportional amplifier includes a memristor M3, an operational amplifier OP9, and a resistor R12. The positive terminal of the memristor M3 is connected to the first contact of the voltage-controlled switch S5, and the negative terminal of the memristor M3 is connected to the inverting input terminal of the operational amplifier OP9 and the resistor R12. The non-inverting input terminal of the operational amplifier OP9 is grounded, and the resistor R12 is connected to the output terminal of the operational amplifier OP9. The output terminal of the operational amplifier OP9 is connected to the first adder.
[0015] The first adder includes resistors R13, R14, and R15, and operational amplifier OP10. Resistor R13 is connected to the output of operational amplifier OP9, resistor R14 is connected to the fourth voltage control unit and the fifth voltage control unit, resistors R13, R14, and R15 are all connected to the non-inverting input of operational amplifier OP10, resistor R15 is connected to the output of operational amplifier OP10, the inverting input of operational amplifier OP10 is grounded, and the output of operational amplifier OP10 is connected to the fifth proportional amplifier.
[0016] The fifth proportional amplifier includes resistor R16, operational amplifier OP11 and resistor R17. The output terminal of operational amplifier OP10 is connected to resistor R16. Resistor R16 is connected to resistor R17 and the inverting input terminal of operational amplifier OP11. Resistor R17 is connected to the output terminal of operational amplifier OP11. The non-inverting input terminal of operational amplifier OP11 is grounded. The output terminal of operational amplifier OP11 is connected to the sixth proportional amplifier of synaptic neuron module III.
[0017] The fourth voltage control unit includes a voltage control switch S3. The output terminal of AND gate D4 is connected to the positive input terminal of voltage control switch S3. The first contact of voltage control switch S3 is connected to resistor R14. The second contact of voltage control switch S3 is connected to the positive terminal of power supply V9. The negative terminal of power supply V9 and the inverting input terminal of voltage control switch S3 are both grounded.
[0018] The fifth voltage control unit includes a voltage control switch S4. The input signal terminal N3 is connected to the positive input terminal of the voltage control switch S4. The first contact of the voltage control switch S4 is connected to the resistor R14. The second contact of the voltage control switch S4 is connected to the positive terminal of the power supply V10. The negative terminal of the power supply V10 and the inverting input terminal of the voltage control switch S4 are both grounded.
[0019] The sixth proportional amplifier includes a memristor M2, an operational amplifier OP12, and a resistor R18. The positive terminal of the memristor M2 is connected to the output terminal of the operational amplifier OP11, and the negative terminal of the memristor M2 is connected to the inverting input terminal of the operational amplifier OP12 and the resistor R18. The non-inverting input terminal of the operational amplifier OP12 is grounded, and the resistor R18 is connected to the output terminal of the operational amplifier OP12. The output terminal of the operational amplifier OP12 is connected to the absolute value module ABS3.
[0020] The seventh proportional amplifier includes resistor R19, operational amplifier OP13, and resistor R20. The output terminal of the absolute value module ABS3 is connected to resistor R19. Resistor R19 is connected to resistor R20 and the inverting input terminal of operational amplifier OP13. Resistor R20 is connected to the output terminal of operational amplifier OP13. The non-inverting input terminal of operational amplifier OP13 is grounded. The output terminal of operational amplifier OP13 is connected to the fifth comparator.
[0021] The fifth comparator includes an operational amplifier OP14. The output of operational amplifier OP13 is connected to the inverting input of operational amplifier OP14. The non-inverting input of operational amplifier OP14 is grounded through power supply V6. The output of operational amplifier OP14 is connected to the sixth comparator.
[0022] The sixth comparator includes an NMOS transistor T4. The gate of the NMOS transistor T4 is connected to the output terminal of the operational amplifier OP14. The drain of the NMOS transistor T4 is connected to a resistor R21, which is connected to the positive terminal of the power supply V17. The source of the NMOS transistor T4 is connected to a resistor R22. The negative terminal of the power supply V17 and the resistor R22 are both grounded. The drain of the NMOS transistor T4 is the output signal terminal OUTⅢ, which is connected to an OR gate.
[0023] The seventh comparator includes an NMOS transistor T5 and a PMOS transistor T6. The output of the NOT gate D9 is connected to the gate of the NMOS transistor T5. The drain of the NMOS transistor T5 is connected to the positive terminal of power supply V20 through a resistor R23. The source of the NMOS transistor T5 is connected to the positive terminal of power supply V21. The negative terminals of power supplies V20 and V21 are both grounded. The drain of the NMOS transistor T5 is connected to the gate of the PMOS transistor T6. The drain of the PMOS transistor T6 is connected to the positive terminal of power supply V22 through a resistor R24. The source of the PMOS transistor T6 is connected to the positive terminal of power supply V23. The negative terminals of power supplies V22 and V23 are both grounded. The drain of the PMOS transistor T6 is connected to one input of the AND gate D4.
[0024] The sixth voltage control unit includes a voltage control switch S8. The output terminal of AND gate D16 is connected to the non-inverting input terminal of voltage control switch S8. The first contact of voltage control switch S8 is connected to the eighth proportional amplifier and resistor R25 respectively. The second contact of voltage control switch S8 is connected to the positive terminal of power supply V24. The negative terminal of power supply V24, resistor R25 and the inverting input terminal of voltage control switch S8 are all grounded.
[0025] The eighth proportional amplifier includes a memristor M5, an operational amplifier OP15, and a resistor R26. The positive terminal of the memristor M5 is connected to the first contact of the voltage-controlled switch S8, the negative terminal of the memristor M5 is connected to the inverting input terminal of the operational amplifier OP15 and the resistor R26, the non-inverting input terminal of the operational amplifier OP15 is grounded, the resistor R26 is connected to the output terminal of the operational amplifier OP15, and the output terminal of the operational amplifier OP15 is connected to the second adder.
[0026] The second adder includes resistors R27, R28, and R29, and operational amplifier OP16. Resistor R27 is connected to the output of operational amplifier OP15. Resistor R28 is connected to the seventh voltage control unit and the eighth voltage control unit respectively. Resistors R27, R28, and R29 are all connected to the non-inverting input of operational amplifier OP10. Resistor R27 is connected to the output of operational amplifier OP16. The inverting input of operational amplifier OP16 is grounded. The output of operational amplifier OP16 is connected to the ninth proportional amplifier.
[0027] The ninth proportional amplifier includes resistor R30, operational amplifier OP17 and resistor R31. The output terminal of operational amplifier OP16 is connected to resistor R30. Resistor R30 is connected to resistor R31 and the inverting input terminal of operational amplifier OP17. Resistor R31 is connected to the output terminal of operational amplifier OP17. The non-inverting input terminal of operational amplifier OP17 is grounded. The output terminal of operational amplifier OP17 is connected to the tenth proportional amplifier of synaptic neuron module IV.
[0028] The seventh voltage control unit includes a voltage control switch S6, the output terminal of AND gate D8 is connected to the positive input terminal of voltage control switch S6, the first contact of voltage control switch S6 is connected to resistor R28, the second contact of voltage control switch S3 is connected to the positive terminal of power supply V18, and the negative terminal of power supply V18 and the inverting input terminal of voltage control switch S6 are both grounded.
[0029] The eighth voltage control unit includes a voltage control switch S7. The input signal terminal N4 is connected to the positive input terminal of the voltage control switch S7. The first contact of the voltage control switch S7 is connected to the resistor R28. The second contact of the voltage control switch S7 is connected to the positive terminal of the power supply V19. The negative terminal of the power supply V19 and the inverting input terminal of the voltage control switch S7 are both grounded.
[0030] The tenth proportional amplifier includes a memristor M4, an operational amplifier OP18, and a resistor R32. The positive terminal of the memristor M2 is connected to the output terminal of the operational amplifier OP17, and the negative terminal of the memristor M2 is connected to the inverting input terminal of the operational amplifier OP12 and the resistor R32. The non-inverting input terminal of the operational amplifier OP18 is grounded, and the resistor R32 is connected to the output terminal of the operational amplifier OP18. The output terminal of the operational amplifier OP18 is connected to the absolute value module ABS4.
[0031] The eleventh proportional amplifier includes resistor R33, operational amplifier OP19, and resistor R34. The output of the absolute value module ABS4 is connected to resistor R33. Resistor R33 is connected to resistor R34 and the inverting input of operational amplifier OP19. Resistor R34 is connected to the output of operational amplifier OP19. The non-inverting input of operational amplifier OP19 is grounded. The output of operational amplifier OP13 is connected to the fifth comparator.
[0032] The ninth comparator includes an operational amplifier OP20. The output of operational amplifier OP19 is connected to the inverting input of operational amplifier OP20. The non-inverting input of operational amplifier OP20 is grounded through power supply V25. The output of operational amplifier OP20 is connected to the tenth comparator.
[0033] The tenth comparator includes an NMOS transistor T7. The gate of the NMOS transistor T7 is connected to the output terminal of the operational amplifier OP20. The drain of the NMOS transistor T7 is connected to a resistor R35, which is connected to the positive terminal of the power supply V26. The source of the NMOS transistor T7 is connected to a resistor R36. The negative terminal of the power supply V26 and the resistor R36 are both grounded. The drain of the NMOS transistor T7 is the output signal terminal OUTⅣ, which is connected to an OR gate.
[0034] The logic circuit V includes a tenth comparator, NOT gate D10, AND gate D11, voltage summation unit SUM2, and voltage summation unit SUM3. The input terminal of the tenth comparator is connected to the output terminal of the absolute value module ABS2 of the synaptic neuron module II. The output terminal of the tenth comparator is connected to one input terminal of AND gate D11, and the other input terminal of AND gate D11 is connected to the output terminal of AND gate D1 of logic circuit I. The input signal terminal N5 is connected to the input terminal of NOT gate D10. The output terminals of NOT gate D10 and AND gate D11 are both connected to the input terminal of voltage summation unit SUM2. The output terminal of AND gate D11 is connected to suppression module III. The output terminals of suppression module III and voltage summation unit SUM2 are both connected to the input terminal of voltage summation unit SUM3. The output terminal of voltage summation unit SUM3 is connected to the input terminal of synaptic neuron module V. The output terminal of synaptic neuron module V is the output signal terminal OUTV, which is connected to an OR gate.
[0035] The suppression module III includes a ninth voltage control unit, a twelfth proportional amplifier, and an absolute value module ABS5 connected in sequence. The input terminal of the ninth voltage control unit is connected to the output terminal of AND gate D11, and the output terminal of the absolute value module ABS5 is connected to one input terminal of the voltage summing unit SUM3.
[0036] The prominent neuron module V includes a thirteenth proportional amplifier, an absolute value module ABS6, an eleventh comparator, and a twelfth comparator connected in sequence. The output terminal of the voltage summing unit SUM3 is connected to the input terminal of the thirteenth proportional amplifier, and the output terminal of the twelfth comparator is the output signal terminal OUTⅤ.
[0037] The logic circuit VI includes a thirteenth comparator, NOT gate D12, AND gate D13, voltage summation unit SUM4, and voltage summation unit SUM5. The input terminal of the thirteenth comparator is connected to the output terminal of the absolute value module ABS2 of the synaptic neuron module II. The output terminal of the thirteenth comparator is connected to one input terminal of AND gate D13, and the other input terminal of AND gate D13 is connected to the output terminal of AND gate D1 of logic circuit I. The input signal terminal N6 is connected to the input terminal of NOT gate D12. The output terminals of NOT gate D12 and AND gate D13 are both connected to the input terminal of voltage summation unit SUM4. The output terminal of AND gate D13 is connected to the suppression module IV. The output terminals of suppression module IV and voltage summation unit SUM4 are both connected to the input terminal of voltage summation unit SUM5. The output terminal of voltage summation unit SUM5 is connected to the input terminal of synaptic neuron module VI. The output terminal of synaptic neuron module VI is the output signal terminal OUTVI, which is connected to an OR gate.
[0038] The suppression module IV includes a tenth voltage control unit, a fourteenth proportional amplifier, and an absolute value module ABS7 connected in sequence. The input terminal of the tenth voltage control unit is connected to the output terminal of AND gate D13, and the output terminal of the absolute value module ABS7 is connected to one input terminal of the voltage summing unit SUM5.
[0039] The prominent neuron module VI includes a fifteenth proportional amplifier, an absolute value module ABS8, a fourteenth comparator, and a fifteenth comparator connected in sequence. The output terminal of the voltage summing unit SUM5 is connected to the input terminal of the fifteenth proportional amplifier, and the output terminal of the fifteenth comparator is the output signal terminal OUTVI.
[0040] The logic circuit VII includes a sixteenth comparator, NOT gate D14, AND gate D15, voltage summation unit SUM6, and voltage summation unit SUM7. The input of the sixteenth comparator is connected to the output of the absolute value module ABS2 of the synaptic neuron module II. The output of the sixteenth comparator is connected to one input of AND gate D15, and the other input of AND gate D15 is connected to the output of AND gate D1 of logic circuit I. The input signal terminal N7 is connected to the input of NOT gate D14. The outputs of NOT gate D14 and AND gate D15 are both connected to the input of voltage summation unit SUM6. The output of AND gate D15 is connected to the suppression module V. The outputs of the suppression module V and voltage summation unit SUM4 are both connected to the input of voltage summation unit SUM7. The output of voltage summation unit SUM7 is connected to the input of synaptic neuron module VII. The output of synaptic neuron module VII is the output signal terminal OUTVII, which is connected to an OR gate.
[0041] The suppression module V includes an eleventh voltage control unit, a sixteenth proportional amplifier, and an absolute value module ABS9 connected in sequence. The input terminal of the eleventh voltage control unit is connected to the output terminal of AND gate D15, and the output terminal of the absolute value module ABS9 is connected to one input terminal of voltage summing unit SUM7.
[0042] The prominent neuron module VII includes a seventeenth proportional amplifier, an absolute value module ABS10, a seventeenth comparator, and an eighteenth comparator connected in sequence. The output terminal of the voltage summing unit SUM7 is connected to the input terminal of the seventeenth proportional amplifier, and the output terminal of the eighteenth comparator is the output signal terminal OUTVII.
[0043] The tenth comparator includes an operational amplifier OP6. The inverting input of the operational amplifier OP6 is connected to the absolute value module ABS2, the non-inverting input of the operational amplifier OP6 is connected to the positive terminal of the power supply V6, the negative terminal of the power supply V5 is grounded, and the output of the operational amplifier OP6 is connected to one input of the AND gate D11.
[0044] The ninth voltage control unit includes a voltage control switch S9. The output terminal of AND gate D11 is connected to the non-inverting input terminal of voltage control switch S9. The first contact of voltage control switch S9 is connected to the twelfth proportional amplifier and resistor R37 respectively. The second contact of voltage control switch S9 is connected to the positive terminal of power supply V27. The negative terminal of power supply V27, resistor R37 and the inverting input terminal of voltage control switch S9 are all grounded.
[0045] The twelfth proportional amplifier includes a memristor M7, an operational amplifier OP21, and a resistor R38. The positive terminal of the memristor M7 is connected to the first contact of the voltage-controlled switch S9, and the negative terminal of the memristor M7 is connected to the inverting input terminal of the operational amplifier OP21 and the resistor R38. The non-inverting input terminal of the operational amplifier OP21 is grounded, and the resistor R38 is connected to the output terminal of the operational amplifier OP21. The output terminal of the operational amplifier OP21 is connected to the absolute value module ABS5.
[0046] The thirteenth proportional amplifier includes a memristor M6, an operational amplifier OP22, and a resistor R39. The positive terminal of the memristor M6 is connected to the output terminal of the voltage summing unit SUM3, and the negative terminal of the memristor M6 is connected to the inverting input terminal of the operational amplifier OP22 and the resistor R39. The non-inverting input terminal of the operational amplifier OP22 is grounded, and the resistor R39 is connected to the output terminal of the operational amplifier OP22. The output terminal of the operational amplifier OP22 is connected to the input terminal of the absolute value module ABS6.
[0047] The eleventh comparator includes an operational amplifier OP23. The inverting input of the operational amplifier OP23 is connected to the output of the absolute value module ABS6, the non-inverting input of the operational amplifier OP23 is grounded through power supply V28, and the output of the operational amplifier OP23 is connected to the twelfth comparator.
[0048] The twelfth comparator includes an NMOS transistor T8. The gate of the NMOS transistor T8 is connected to the output terminal of the operational amplifier OP23. The drain of the NMOS transistor T8 is connected to a resistor R40, which is connected to the positive terminal of the power supply V29. The source of the NMOS transistor T8 is connected to a resistor R41. The negative terminal of the power supply V29 and the resistor R41 are both grounded. The drain of the NMOS transistor T8 is the output signal terminal OUTV, which is connected to an OR gate.
[0049] The thirteenth comparator includes an operational amplifier OP7. The inverting input of the operational amplifier OP7 is connected to the output of the absolute value module ABS2, the non-inverting input of the operational amplifier OP7 is grounded through power supply V7, and the output of the operational amplifier OP7 is connected to AND gate D13.
[0050] The tenth voltage control unit includes a voltage control switch S10. The output terminal of AND gate D13 is connected to the non-inverting input terminal of voltage control switch S10. The first contact of voltage control switch S10 is connected to the fourteenth proportional amplifier and resistor R42 respectively. The second contact of voltage control switch S10 is connected to the positive terminal of power supply V30. The negative terminal of power supply V30, resistor R42 and the inverting input terminal of voltage control switch S10 are all grounded.
[0051] The fourteenth proportional amplifier includes a memristor M9, an operational amplifier OP24, and a resistor R43. The positive terminal of the memristor M9 is connected to the first contact of the voltage-controlled switch S9, and the negative terminal of the memristor M9 is connected to the inverting input terminal of the operational amplifier OP24 and the resistor R43. The non-inverting input terminal of the operational amplifier OP24 is grounded, and the resistor R43 is connected to the output terminal of the operational amplifier OP24. The output terminal of the operational amplifier OP24 is connected to the absolute value module ABS7.
[0052] The fifteenth proportional amplifier includes a memristor M8, an operational amplifier OP25, and a resistor R44. The positive terminal of the memristor M8 is connected to the output terminal of the voltage summing unit SUM5, and the negative terminal of the memristor M8 is connected to the inverting input terminal of the operational amplifier OP25 and the resistor R44. The non-inverting input terminal of the operational amplifier OP25 is grounded, and the resistor R44 is connected to the output terminal of the operational amplifier OP25. The output terminal of the operational amplifier OP25 is connected to the input terminal of the absolute value module ABS8.
[0053] The fourteenth comparator includes an operational amplifier OP26. The inverting input of the operational amplifier OP26 is connected to the output of the absolute value module ABS8, the non-inverting input of the operational amplifier OP26 is grounded through power supply V31, and the output of the operational amplifier OP26 is connected to the fifteenth comparator.
[0054] The fifteenth comparator includes an NMOS transistor T9. The gate of the NMOS transistor T9 is connected to the output terminal of the operational amplifier OP26. The drain of the NMOS transistor T9 is connected to a resistor R45, which is connected to the positive terminal of the power supply V32. The source of the NMOS transistor T9 is connected to a resistor R46. The negative terminal of the power supply V32 and the resistor R46 are both grounded. The drain of the NMOS transistor T9 is the output signal terminal OUTVI, which is connected to an OR gate.
[0055] The sixteenth comparator includes an operational amplifier OP8, the inverting input of which is connected to the output of the absolute value module ABS2, the non-inverting input of which is grounded through power supply V8, and the output of the operational amplifier OP6 is connected to AND gate D13.
[0056] The eleventh voltage control unit includes a voltage control switch S11. The output terminal of AND gate D15 is connected to the non-inverting input terminal of voltage control switch S10. The first contact of voltage control switch S10 is connected to the twelfth proportional amplifier and resistor R47 respectively. The second contact of voltage control switch S10 is connected to the positive terminal of power supply V33. The negative terminal of power supply V33, resistor R47 and the inverting input terminal of voltage control switch S10 are all grounded.
[0057] The sixteenth proportional amplifier includes a memristor M11, an operational amplifier OP27, and a resistor R48. The positive terminal of the memristor M11 is connected to the first contact of the voltage-controlled switch S11, and the negative terminal of the memristor M11 is connected to the inverting input terminal of the operational amplifier OP27 and the resistor R48. The non-inverting input terminal of the operational amplifier OP27 is grounded, and the resistor R48 is connected to the output terminal of the operational amplifier OP27. The output terminal of the operational amplifier OP27 is connected to the absolute value module ABS7.
[0058] The seventeenth proportional amplifier includes a memristor M10, an operational amplifier OP28, and a resistor R49. The positive terminal of the memristor M10 is connected to the output terminal of the voltage summing unit SUM7, and the negative terminal of the memristor M10 is connected to the inverting input terminal of the operational amplifier OP28 and the resistor R49. The non-inverting input terminal of the operational amplifier OP29 is grounded, and the resistor R49 is connected to the output terminal of the operational amplifier OP28. The output terminal of the operational amplifier OP28 is connected to the input terminal of the absolute value module ABS10.
[0059] The seventeenth comparator includes an operational amplifier OP29. The inverting input of the operational amplifier OP29 is connected to the output of the absolute value module ABS10, the non-inverting input of the operational amplifier OP29 is grounded through power supply V34, and the output of the operational amplifier OP29 is connected to the eighteenth comparator.
[0060] The eighteenth comparator includes an NMOS transistor T10. The gate of the NMOS transistor T10 is connected to the output terminal of the operational amplifier OP29. The drain of the NMOS transistor T10 is connected to a resistor R50, which is connected to the positive terminal of the power supply V35. The source of the NMOS transistor T10 is connected to a resistor R51. The negative terminal of the power supply V35 and the resistor R51 are both grounded. The drain of the NMOS transistor T10 is the output signal terminal OUTⅦ, which is connected to an OR gate.
[0061] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0062] 1) Through the associative learning and forgetting process between multiple prominent neuronal modules, the secondary differentiation process of Pavlovian associative memory was realized: similar ringtones will generalize, ringtones with different attributes will undergo primary differentiation, and ringtones with the same attributes but different degrees of range will undergo secondary differentiation, making associative memory more in line with the actual situation of brain memory, which may provide a reference for more intelligent brain-like neural networks.
[0063] 2) Based on the non-volatility and threshold characteristics of memristors, Pavlovian associative memory was generalized and differentiated multiple times. The more times it was generalized, the fewer the learning and differentiation cycles there were, and the slower the forgetting rate, the more it was consolidated and may form long-term memory.
[0064] 3) By using the inhibition module to achieve extinction inhibition and differentiation inhibition in forgetting, associative memory becomes more in line with biological characteristics. Attached Figure Description
[0065] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0066] Figure 1 This is a schematic diagram of the structure of the present invention.
[0067] Figure 2 This is a simulation result diagram of learning and forgetting in this invention.
[0068] Figure 3 This is a voltage simulation result diagram showing the learning and generalization among multiple neurons in this invention.
[0069] Figure 4 This is a simulation result diagram of primary and secondary differentiation among multiple neurons in this invention.
[0070] Figure 5 The following are simulation results of multiple generalizations and differentiations in this invention: (a) is the simulation result of the first generalization and differentiation, (b) is the simulation result of the second generalization and differentiation, and (c) is the simulation result of the third generalization and differentiation.
[0071] Figure 6 The figure shows the simulation results of the inhibition voltage of the present invention to achieve differentiation inhibition. Detailed Implementation
[0072] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0073] like Figure 1 As shown, a multi-mode generalization and differentiation associative memory neural network circuit based on memristor includes input signal terminals N1-N7, synaptic neuron modules I-VII, inhibition modules I-V, and an output signal terminal. The synaptic neuron modules transmit signals from the input neurons to the output neurons, and the inhibition modules eliminate misjudgments caused by similar ringtones. Input signal terminals N1-N7 are defined as seven pre-neurons. Pre-neuron N1 corresponds to the unconditioned reflex signal (food signal) in Pavlovian associative memory, and pre-neurons N2-N7 correspond to conditioned reflex signals. Pre-neurons N2 is a 500Hz bell signal, N3 is an 800Hz bell signal, N4 is a 400Hz bell signal, N5 is a 500Hz buzzer signal, N6 is an 800Hz buzzer signal, and N7 is a 400Hz buzzer signal. In the specific implementation, the bell input signal uses a 5V amplitude pulse signal, and the buzzer input signal uses a 2.5V amplitude pulse signal. The output signal terminal OUT is the signal emitted by the postneuron after receiving stimulation, which is specifically manifested as the secretion of saliva in Pavlovian associative memory.
[0074] Input signal terminal N1 is connected to synaptic neuron module I, which transmits the food input signal to the output neuron. Input signal terminals N1 and N2 are connected to synaptic neuron module II via logic circuit I. Logic circuit I ensures that input signal terminals N1 and N2 are simultaneously input for the module to conduct. Synaptic neuron module II transmits the 500Hz bell input signal to the input neuron. Input signal terminals N1 and N2, along with synaptic neuron module II, are all connected to inhibition module I via logic circuit II. Inhibition module I is connected to input signal terminal N3. Logic circuit II ensures that inhibition module I conducts only when input signal terminals N1 and N2 are simultaneously input. Inhibition module I suppresses misjudgments caused by the 800Hz bell. Inhibition module I and input signal terminal N3 are both connected to synaptic neuron module III via logic circuit III. Logic circuit III ensures that input signal terminal N3 generalizes when input signal terminals N1 and N2 are simultaneously present. Synaptic neuron module III transmits the 800Hz bell input signal to the input neuron. Both input signal terminals N1 and N4 are connected to suppression module II. Suppression module II and input signal terminal N4 are both connected to synaptic neuron module IV via logic circuit IV. Suppression module II suppresses false alarms caused by the 400Hz electric bell. Logic circuit IV ensures that the circuit is activated only when input signal terminals N1 and N2 are input simultaneously. Synaptic neuron module IV transmits the 400Hz electric bell input signal to the input neuron. Input signal terminals N1 and N2, and synaptic neuron module II are all connected to suppression module III. Suppression module III and input signal terminal N5 are both connected to synaptic neuron module V via logic circuit V. Suppression module III suppresses false alarms caused by the 500Hz buzzer. Logic circuit V transmits the input signals from suppression module III and input signal terminal N5 to the output neuron. Synaptic neuron module V transmits the 500Hz buzzer input signal to the input neuron. Input signal terminals N1 and N2, and synaptic neuron module II are all connected to inhibition module IV. Inhibition module IV and input signal terminal N6 are both connected to synaptic neuron module VI via logic circuit VI. Inhibition module IV suppresses misjudgments caused by the 800Hz buzzer. Logic circuit VI transmits the input signals from inhibition module IV and input signal terminal N6 to the output neuron. Synaptic neuron module VI transmits the 800Hz buzzer input signal to the input neuron. Input signal terminals N1 and N2, and synaptic neuron module II are all connected to inhibition module V. Inhibition module V and input signal terminal N7 are connected to synaptic neuron module VII via logic circuit VII. Inhibition module V suppresses misjudgments caused by the 400Hz buzzer. Input signal terminal N7 transmits the 400Hz buzzer input signal to the input neuron. Logic circuit VII transmits the input signals from inhibition module IV and input signal terminal N6 to the output neuron.The synaptic neuron modules I to VII are connected to the output signal terminal via an OR gate.
[0075] like Figure 1 As shown, the synaptic neuron module I includes a first proportional amplifier, with the input signal terminal N1 connected to it. The first proportional amplifier is connected to an absolute value module ABS1, whose output terminal OUT1 is connected to an OR gate. The first proportional amplifier includes a resistor R1, an operational amplifier OP1, and a resistor R2. The output signal terminal OUT1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to one end of resistor R2 and the inverting input terminal of operational amplifier OP1. The other end of resistor R2 is connected to the output terminal of operational amplifier OP1. The non-inverting input terminal of operational amplifier OP1 is grounded, and the output terminal of operational amplifier OP1 is connected to the input terminal of absolute value module ABS1. The output terminal of absolute value module ABS1 is connected to the output signal terminal OUT1. The first proportional amplifier performs proportional calculations, and the absolute value module ABS1 takes the modulo of the output value of operational amplifier OP1, outputting a 2.8V pulse signal at output signal terminal OUT1.
[0076] The logic circuit I includes a first voltage-controlled unit, a second voltage-controlled unit, an AND gate D1, and a voltage summing unit SUM1. Input signal terminals N1 and N2 are both connected to the AND gate D1. The output terminal of the AND gate D1 is connected to the first voltage-controlled unit, and the input signal terminal N2 is connected to the second voltage-controlled unit. The first and second voltage-controlled units are respectively connected to the two input terminals of the voltage summing unit SUM1. The output terminal of the voltage summing unit SUM1 is connected to the synaptic neuron module II. The first voltage-controlled unit includes a voltage-controlled switch S1. The output terminal of AND gate D1 is connected to the non-inverting input terminal of voltage-controlled switch S1. The first contact of voltage-controlled switch S1 is connected to the first input terminal of voltage summing unit SUM1 and resistor R3. The second contact of voltage-controlled switch S1 is connected to the positive terminal of power supply V1. The negative terminal of power supply V1, resistor R3, and the inverting input terminal of voltage-controlled switch S1 are all grounded. Voltage-controlled switch S1 can only conduct when its threshold value is exceeded. The first contact outputs the voltage of V1, and the second contact inputs the voltage of V1. The second voltage-controlled unit includes a voltage-controlled switch S2. The non-inverting input terminal of voltage-controlled switch S2 is connected to the input signal terminal N2. The first contact of voltage-controlled switch S2 is connected to the second input terminal of voltage summing unit SUM1 and resistor R4. The second contact of voltage-controlled switch S2 is connected to the positive terminal of power supply V2. The negative terminal of power supply V2, resistor R4, and the inverting input terminal of voltage-controlled switch S2 are all grounded.
[0077] The synaptic neuron module II includes a second proportional amplifier, an absolute value module ABS2, a third proportional amplifier, a first comparator, and a second comparator connected in sequence. The input terminal of the second proportional amplifier is connected to the voltage summation unit SUM1 of logic circuit I. The output terminal of the second comparator is the output signal terminal OUTII, which is connected to an OR gate. The second and third proportional amplifiers perform proportional operations. The first comparator compares the output voltage of operational amplifier OP3 with the power supply V3. If it is less than the power supply V3, it outputs a high level; otherwise, it outputs a low level. The second comparator outputs power supply V4 if the output voltage of operational amplifier OP4 is greater than the threshold voltage T1; otherwise, it outputs 0V.
[0078] The second proportional amplifier includes a memristor M1, an operational amplifier OP2, and a resistor R5. The positive terminal (K-terminal) of memristor M1 is connected to the output of the voltage summing unit SUM1 of logic circuit I. The negative terminal (A-terminal) of memristor M1 is connected to the inverting input of operational amplifier OP2 and one end of resistor R5. The non-inverting input of operational amplifier OP2 is grounded. The other end of resistor R5 is connected to the output of operational amplifier OP2. The output of operational amplifier OP2 is connected to the input of absolute value module ABS2. The output of absolute value module ABS2 is connected to the third proportional amplifier. The signal output by the output of absolute value module ABS2 is the absolute value of the output voltage of operational amplifier OP2. The third proportional amplifier includes resistor R6, operational amplifier OP3, and resistor R7. The output of the absolute value module ABS2 is connected to one end of resistor R6. The other end of resistor R6 is connected to one end of resistor R7 and the inverting input of operational amplifier OP3. The other end of resistor R7 is connected to the output of operational amplifier OP3. The non-inverting input of operational amplifier OP3 is grounded, and the output of operational amplifier OP3 is connected to the first comparator. The second comparator includes operational amplifier OP4. The inverting input of operational amplifier OP4 is connected to the output of operational amplifier OP3. The non-inverting input of operational amplifier OP4 is connected to the positive terminal of power supply V3. The negative terminal of power supply V3 is grounded. The output of operational amplifier OP4 is connected to the second comparator. The second comparator includes an NMOS transistor T1. The gate of NMOS transistor T1 is connected to the output of operational amplifier OP4. The drain of NMOS transistor T1 is connected to one end of resistor R8, and the other end of resistor R8 is connected to the positive terminal of power supply V4. The source of NMOS transistor T1 is connected to one end of resistor R9. The negative terminal of power supply V4 and the other end of resistor R9 are both grounded. The drain of NMOS transistor T1 is the output signal terminal OUTⅡ, which is connected to an OR gate. The output signal terminal OUTⅡ outputs a 2.8V pulse signal.
[0079] like Figure 2As shown, the 0-5s period is the testing phase, where food is the unconditioned stimulus (input signal terminal N1 outputs a signal, and output signal terminal OUT outputs a high level); the electric bell is the conditioned stimulus (input signal terminal N2 outputs a signal, and output signal terminal OUT outputs a low level). The 5-24s period is the learning phase, where both food and the 500Hz electric bell output signals simultaneously. The 24-33s period is the testing phase, where only the 500Hz electric bell signal is applied, and output signal terminal OUT outputs a high level, indicating that the dog can salivate upon receiving the 500Hz electric bell signal. The 33s-42s period is the forgetting phase; after a period of time, the dog can no longer salivate upon receiving the 500Hz electric bell signal.
[0080] Logic circuit II includes a third comparator, AND gate D2, and NOT gate D5. The input of the third comparator is connected to the output of the absolute value module ABS2 of the synaptic neuron module II. The function of the third comparator is to compare the output voltage of the absolute value module ABS2 with the power supply V5. If it is less than the power supply V5, it outputs a high level; otherwise, it outputs a low level. The output of the third comparator and the output of AND gate D1 of logic circuit I are both connected to the input of AND gate D2. The output of AND gate D2 is connected to the input of NOT gate D5. The output of NOT gate D5 is connected to suppression module I. Suppression module I includes a fourth comparator, AND gate D6, a third voltage-controlled unit, and a fourth proportional amplifier. The output of NOT gate D5 is connected to the input of the fourth comparator. The function of the fourth comparator is to output a low level if the output voltage of NOT gate D5 is less than the threshold voltage T2; otherwise, it outputs a high level. The output and input signal terminal N3 of the fourth comparator are both connected to the input terminal of AND gate D6. The output terminal of AND gate D6 is connected to the third voltage control unit. The third voltage control unit is connected to the fourth proportional amplifier. The output terminal of the fourth proportional amplifier is connected to logic circuit III. The third voltage control unit can only conduct when its threshold value is exceeded. The function of the fourth proportional amplifier is to perform proportional calculations. Logic circuit III includes a first adder, a fifth proportional amplifier, a fourth voltage-controlled unit, a fifth voltage-controlled unit, an NOT gate D3, and an AND gate D4. Input signal terminal N3 is connected to the input terminal of NOT gate D3. The output terminals of NOT gate D3 and AND gate D2 are both connected to the input terminal of AND gate D4. The output terminal of AND gate D4 is connected to the fourth voltage-controlled unit. Input signal terminal N3 is connected to the fifth voltage-controlled unit. The output terminals of the fourth and fifth voltage-controlled units are connected to the first adder. The first adder is connected to the fifth proportional amplifier. The fifth proportional amplifier is connected to the synaptic neuron module III. The first adder adds the voltage of the suppression module I to the voltages of the fourth and fifth voltage-controlled units. The fifth proportional amplifier performs proportional calculations. The fourth and fifth voltage-controlled units only conduct when their threshold values are exceeded. The synaptic neuron module III includes a sixth proportional amplifier, an absolute value module ABS3, a seventh proportional amplifier, a fifth comparator, and a sixth comparator connected in sequence. The output terminal of the fifth proportional amplifier is connected to the input terminal of the sixth proportional amplifier. The output terminal of the sixth comparator is the output signal terminal OUTIII, which is connected to an OR gate. The sixth and seventh proportional amplifiers perform proportional calculations. The fifth comparator compares the output voltage of operational amplifier OP13 with the power supply V16. If it is less than the power supply V16, it outputs a high level; otherwise, it outputs a low level. The second comparator outputs the voltage of power supply V17 if the output voltage of operational amplifier OP14 is greater than the threshold voltage T4; otherwise, it outputs 0V. The output signal terminal OUTIII outputs a 2.8V pulse signal.
[0081] The third comparator includes an operational amplifier OP5. The inverting input of the operational amplifier OP5 is connected to the output of the absolute value module ABS2. The non-inverting input of the operational amplifier OP5 is grounded through power supply V5. The output of the operational amplifier OP5 is connected to one input of the AND gate D2D.
[0082] The fourth comparator includes an NMOS transistor T2 and a PMOS transistor T3. The output of the NOT gate D5 is connected to the gate of the NMOS transistor T2. The drain of the NMOS transistor T2 is connected to the positive terminal of power supply V11 through a resistor R10. The source of the NMOS transistor T2 is connected to the positive terminal of power supply V12. The negative terminals of power supplies V11 and V12 are both grounded. The drain of the NMOS transistor T2 is connected to the gate of the PMOS transistor T3. The drain of the PMOS transistor T3 is connected to the positive terminal of power supply V13 through a resistor R11. The source of the PMOS transistor T3 is connected to the positive terminal of power supply V14. The negative terminals of power supplies V13 and V14 are both grounded. The drain of the PMOS transistor T3 is connected to one input of the AND gate D6.
[0083] The fourth voltage control unit includes a voltage control switch S3. The output terminal of AND gate D4 is connected to the positive input terminal of voltage control switch S3. The first contact of voltage control switch S3 is connected to one end of resistor R14. The second contact of voltage control switch S3 is connected to the positive terminal of power supply V9. The negative terminal of power supply V9 and the inverting input terminal of voltage control switch S3 are both grounded.
[0084] The fifth voltage control unit includes a voltage control switch S4. The input signal terminal N3 is connected to the positive input terminal of the voltage control switch S4. The first contact of the voltage control switch S4 is connected to one end of the resistor R14. The second contact of the voltage control switch S4 is connected to the positive terminal of the power supply V10. The negative terminal of the power supply V10 and the inverting input terminal of the voltage control switch S4 are both grounded.
[0085] The third voltage control unit includes a voltage control switch S5. The output terminal of AND gate D6 is connected to the non-inverting input terminal of voltage control switch S5. The first contact of voltage control switch S5 is connected to the fourth proportional amplifier and resistor R52 respectively. The second contact of voltage control switch S5 is connected to the positive terminal of power supply V15. The negative terminal of power supply V15, resistor R52 and the inverting input terminal of voltage control switch S5 are all grounded.
[0086] The fourth proportional amplifier includes a memristor M3, an operational amplifier OP9, and a resistor R12. The positive terminal of the memristor M3 is connected to the first contact of the voltage-controlled switch S5. The negative terminal of the memristor M3 is connected to the inverting input terminal of the operational amplifier OP9 and one end of the resistor R12. The non-inverting input terminal of the operational amplifier OP9 is grounded. The other end of the resistor R12 is connected to the output terminal of the operational amplifier OP9. The output terminal of the operational amplifier OP9 is connected to the first adder.
[0087] The first adder includes resistors R13, R14, and R15, and an operational amplifier OP10. One end of resistor R13 is connected to the output of operational amplifier OP9. One end of resistor R14 is connected to the fourth voltage-controlled unit and the fifth voltage-controlled unit, respectively. The other ends of resistors R13, R14, and R15 are all connected to the non-inverting input of operational amplifier OP10. The other end of resistor R15 is connected to the output of operational amplifier OP10. The inverting input of operational amplifier OP10 is grounded. The output of operational amplifier OP10 is connected to the fifth proportional amplifier.
[0088] The fifth proportional amplifier includes resistor R16, operational amplifier OP11, and resistor R17. The output terminal of operational amplifier OP10 is connected to resistor R16. Resistor R16 is connected to resistor R17 and the inverting input terminal of operational amplifier OP11. Resistor R17 is connected to the output terminal of operational amplifier OP11. The non-inverting input terminal of operational amplifier OP11 is grounded. The output terminal of operational amplifier OP11 is connected to the sixth proportional amplifier of synaptic neuron module III.
[0089] The sixth proportional amplifier includes a memristor M2, an operational amplifier OP12, and a resistor R18. The positive terminal of the memristor M2 is connected to the output terminal of the operational amplifier OP11, and the negative terminal of the memristor M2 is connected to the inverting input terminal of the operational amplifier OP12 and the resistor R18. The non-inverting input terminal of the operational amplifier OP12 is grounded, and the resistor R18 is connected to the output terminal of the operational amplifier OP12. The output terminal of the operational amplifier OP12 is connected to the absolute value module ABS3.
[0090] The seventh proportional amplifier includes resistor R19, operational amplifier OP13, and resistor R20. The output terminal of the absolute value module ABS3 is connected to resistor R19. Resistor R19 is connected to resistor R20 and the inverting input terminal of operational amplifier OP13. Resistor R20 is connected to the output terminal of operational amplifier OP13. The non-inverting input terminal of operational amplifier OP13 is grounded. The output terminal of operational amplifier OP13 is connected to the fifth comparator.
[0091] The fifth comparator includes an operational amplifier OP14. The output of operational amplifier OP13 is connected to the inverting input of operational amplifier OP14. The non-inverting input of operational amplifier OP14 is grounded through power supply V6. The output of operational amplifier OP14 is connected to the sixth comparator.
[0092] The sixth comparator includes an NMOS transistor T4. The gate of the NMOS transistor T4 is connected to the output terminal of the operational amplifier OP14. The drain of the NMOS transistor T4 is connected to a resistor R21, which is connected to the positive terminal of the power supply V17. The source of the NMOS transistor T4 is connected to a resistor R22. The negative terminal of the power supply V17 and the resistor R22 are both grounded. The drain of the NMOS transistor T4 is the output signal terminal OUTⅢ, which is connected to an OR gate.
[0093] Suppression module II includes a seventh comparator, AND gate D4, a sixth voltage-controlled unit (VDC), and an eighth proportional amplifier. The seventh comparator is connected to the output of NOT gate D9, and the input of NOT gate D9 is connected to input signal N1. The output and input signal N4 of the seventh comparator are connected to the input of AND gate D4, the output of AND gate D4 is connected to the input of the sixth VDC, the output of the sixth VDC is connected to the input of the eighth proportional amplifier, and the output of the eighth proportional amplifier is connected to logic circuit IV. The seventh comparator and the sixth VDC only conduct when their threshold values are exceeded. The eighth proportional amplifier performs proportional calculations. The logic circuit IV includes a second adder, a ninth proportional amplifier, a seventh voltage-controlled unit, an eighth voltage-controlled unit, a NOT gate D7, and an AND gate D8. Input signal terminal N4 is connected to the input terminal of NOT gate D7. The output terminals of NOT gate D7 and AND gate D2 are both connected to the input terminal of AND gate D8. The output terminal of AND gate D8 is connected to the seventh voltage-controlled unit. Input signal terminal N4 is connected to the eighth voltage-controlled unit. The output terminals of the seventh and eighth voltage-controlled units are connected to the second adder. The second adder is connected to the ninth proportional amplifier, which is connected to the synaptic neuron module IV. The second adder adds the voltage of the inhibition module II to the voltages of the seventh and eighth voltage-controlled units. The ninth proportional amplifier performs proportional calculations. The seventh and eighth voltage-controlled units only conduct when their threshold values are exceeded. The synaptic neuron module IV includes a tenth proportional amplifier, an absolute value module ABS4, an eleventh proportional amplifier, a ninth comparator, and a tenth comparator connected in sequence. The output terminal of the ninth proportional amplifier is connected to the input terminal of the tenth proportional amplifier. The output terminal of the tenth comparator is the output signal terminal OUTⅣ, which is connected to an OR gate. The tenth and eleventh proportional amplifiers perform proportional calculations. The ninth comparator compares the output voltage of operational amplifier OP19 with power supply V25. If it is less than power supply V25, it outputs a high level; otherwise, it outputs a low level. The tenth comparator outputs the voltage of power supply V26 if the output voltage of operational amplifier OP20 is greater than the threshold voltage T7; otherwise, it outputs 0V. The output signal terminal OUTⅣ outputs a 2.8V pulse signal.
[0094] Synaptic neuron module III and synaptic neuron module IV have the same structure; the former is the output signal of an 800Hz electric bell, and the latter is the output signal of a 400Hz electric bell.
[0095] The seventh comparator includes an NMOS transistor T5 and a PMOS transistor T6. The output of the NOT gate D9 is connected to the gate of the NMOS transistor T5. The drain of the NMOS transistor T5 is connected to the positive terminal of power supply V20 through a resistor R23. The source of the NMOS transistor T5 is connected to the positive terminal of power supply V21. The negative terminals of power supplies V20 and V21 are both grounded. The drain of the NMOS transistor T5 is connected to the gate of the PMOS transistor T6. The drain of the PMOS transistor T6 is connected to the positive terminal of power supply V22 through a resistor R24. The source of the PMOS transistor T6 is connected to the positive terminal of power supply V23. The negative terminals of power supplies V22 and V23 are both grounded. The drain of the PMOS transistor T6 is connected to one input of the AND gate D4.
[0096] The sixth voltage control unit includes a voltage control switch S8. The output terminal of AND gate D16 is connected to the non-inverting input terminal of voltage control switch S8. The first contact of voltage control switch S8 is connected to the eighth proportional amplifier and resistor R25 respectively. The second contact of voltage control switch S8 is connected to the positive terminal of power supply V24. The negative terminal of power supply V24, resistor R25 and the inverting input terminal of voltage control switch S8 are all grounded.
[0097] The eighth proportional amplifier includes a memristor M5, an operational amplifier OP15, and a resistor R26. The positive terminal of the memristor M5 is connected to the first contact of the voltage-controlled switch S8, and the negative terminal of the memristor M5 is connected to the inverting input terminal of the operational amplifier OP15 and the resistor R26. The non-inverting input terminal of the operational amplifier OP15 is grounded, and the resistor R26 is connected to the output terminal of the operational amplifier OP15. The output terminal of the operational amplifier OP15 is connected to the second adder.
[0098] The second adder includes resistors R27, R28, and R29, and operational amplifier OP16. Resistor R27 is connected to the output of operational amplifier OP15. Resistor R28 is connected to the seventh voltage control unit and the eighth voltage control unit, respectively. Resistors R27, R28, and R29 are all connected to the non-inverting input of operational amplifier OP10. Resistor R27 is connected to the output of operational amplifier OP16. The inverting input of operational amplifier OP16 is grounded. The output of operational amplifier OP16 is connected to the ninth proportional amplifier.
[0099] The ninth proportional amplifier includes resistor R30, operational amplifier OP17, and resistor R31. The output terminal of operational amplifier OP16 is connected to resistor R30. Resistor R30 is connected to resistor R31 and the inverting input terminal of operational amplifier OP17. Resistor R31 is connected to the output terminal of operational amplifier OP17. The non-inverting input terminal of operational amplifier OP17 is grounded. The output terminal of operational amplifier OP17 is connected to the tenth proportional amplifier of synaptic neuron module IV.
[0100] The seventh voltage control unit includes a voltage control switch S6. The output terminal of AND gate D8 is connected to the positive input terminal of voltage control switch S6. The first contact of voltage control switch S6 is connected to resistor R28. The second contact of voltage control switch S3 is connected to the positive terminal of power supply V18. The negative terminal of power supply V18 and the inverting input terminal of voltage control switch S6 are both grounded.
[0101] The eighth voltage control unit includes a voltage control switch S7. The input signal terminal N4 is connected to the positive input terminal of the voltage control switch S7. The first contact of the voltage control switch S7 is connected to the resistor R28. The second contact of the voltage control switch S7 is connected to the positive terminal of the power supply V19. The negative terminal of the power supply V19 and the inverting input terminal of the voltage control switch S7 are both grounded.
[0102] The tenth proportional amplifier includes a memristor M4, an operational amplifier OP18, and a resistor R32. The positive terminal of the memristor M2 is connected to the output terminal of the operational amplifier OP17, and the negative terminal of the memristor M2 is connected to the inverting input terminal of the operational amplifier OP12 and the resistor R32. The non-inverting input terminal of the operational amplifier OP18 is grounded, and the resistor R32 is connected to the output terminal of the operational amplifier OP18. The output terminal of the operational amplifier OP18 is connected to the absolute value module ABS4.
[0103] The eleventh proportional amplifier includes resistor R33, operational amplifier OP19, and resistor R34. The output of the absolute value module ABS4 is connected to resistor R33. Resistor R33 is connected to resistor R34 and the inverting input of operational amplifier OP19. Resistor R34 is connected to the output of operational amplifier OP19. The non-inverting input of operational amplifier OP19 is grounded. The output of operational amplifier OP13 is connected to the fifth comparator.
[0104] The ninth comparator includes an operational amplifier OP20. The output of operational amplifier OP19 is connected to the inverting input of operational amplifier OP20. The non-inverting input of operational amplifier OP20 is grounded through power supply V25. The output of operational amplifier OP20 is connected to the tenth comparator.
[0105] The tenth comparator includes an NMOS transistor T7. The gate of the NMOS transistor T7 is connected to the output terminal of the operational amplifier OP20. The drain of the NMOS transistor T7 is connected to a resistor R35, which is connected to the positive terminal of the power supply V26. The source of the NMOS transistor T7 is connected to a resistor R36. The negative terminal of the power supply V26 and the resistor R36 are both grounded. The drain of the NMOS transistor T7 is the output signal terminal OUTⅣ, which is connected to an OR gate.
[0106] The logic circuit V includes a tenth comparator, NOT gate D10, AND gate D11, voltage summation unit SUM2, and voltage summation unit SUM3. The input of the tenth comparator is connected to the output of the absolute value module ABS2 of the synaptic neuron module II. The output of the tenth comparator is connected to one input of AND gate D11, and the other input of AND gate D11 is connected to the output of AND gate D1 of logic circuit I. The input signal terminal N5 is connected to the input of NOT gate D10. The outputs of NOT gate D10 and AND gate D11 are both connected to the input of voltage summation unit SUM2. The output of AND gate D11 is connected to suppression module III. The outputs of suppression module III and voltage summation unit SUM2 are both connected to the input of voltage summation unit SUM3. The output of voltage summation unit SUM3 is connected to the input of synaptic neuron module V. The output of synaptic neuron module V is the output signal terminal OUTV, which is connected to an OR gate. The function of the tenth comparator is to compare the output voltage of ABS2 with the power supply V6. If it is less than the voltage of power supply V6, it outputs a high level; otherwise, it outputs a low level.
[0107] The suppression module III includes a ninth voltage control unit, a twelfth proportional amplifier, and an absolute value module ABS5 connected in sequence. The input of the ninth voltage control unit is connected to the output of AND gate D11, and the output of the absolute value module ABS5 is connected to one input of the voltage summing unit SUM3. The twelfth proportional amplifier performs proportional calculations, and the absolute value module ABS5 takes the modulo of the output value of operational amplifier OP21. The synaptic neuron module V includes a thirteenth proportional amplifier, an absolute value module ABS6, an eleventh comparator, and a twelfth comparator connected in sequence. The output of the voltage summing unit SUM3 is connected to the input of the thirteenth proportional amplifier, and the output of the twelfth comparator is the output signal terminal OUTV. The thirteenth proportional amplifier performs proportional calculations, and the absolute value module ABS6 takes the modulo of the output value of operational amplifier OP22. The eleventh comparator compares the output voltage of ABS6 with the power supply V28. If it is less than the power supply V28, it outputs a high level; otherwise, it outputs a low level. The twelfth comparator outputs the voltage of power supply V29 if the output voltage of operational amplifier OP23 is greater than the threshold voltage T8; otherwise, it outputs 0V. The tenth comparator includes an operational amplifier OP6. The inverting input of the operational amplifier OP6 is connected to the absolute value module ABS2, the non-inverting input of the operational amplifier OP6 is connected to the positive terminal of the power supply V6, the negative terminal of the power supply V5 is grounded, and the output of the operational amplifier OP6 is connected to one input of the AND gate D11.
[0108] The ninth voltage control unit includes a voltage control switch S9. The output terminal of AND gate D11 is connected to the non-inverting input terminal of voltage control switch S9. The first contact of voltage control switch S9 is connected to the twelfth proportional amplifier and resistor R37 respectively. The second contact of voltage control switch S9 is connected to the positive terminal of power supply V27. The negative terminal of power supply V27, resistor R37 and the inverting input terminal of voltage control switch S9 are all grounded.
[0109] The twelfth proportional amplifier includes a memristor M7, an operational amplifier OP21, and a resistor R38. The positive terminal of the memristor M7 is connected to the first contact of the voltage-controlled switch S9, and the negative terminal of the memristor M7 is connected to the inverting input terminal of the operational amplifier OP21 and the resistor R38. The non-inverting input terminal of the operational amplifier OP21 is grounded, and the resistor R38 is connected to the output terminal of the operational amplifier OP21. The output terminal of the operational amplifier OP21 is connected to the absolute value module ABS5.
[0110] The thirteenth proportional amplifier includes a memristor M6, an operational amplifier OP22, and a resistor R39. The positive terminal of the memristor M6 is connected to the output terminal of the voltage summing unit SUM3, and the negative terminal of the memristor M6 is connected to the inverting input terminal of the operational amplifier OP22 and the resistor R39. The non-inverting input terminal of the operational amplifier OP22 is grounded, and the resistor R39 is connected to the output terminal of the operational amplifier OP22. The output terminal of the operational amplifier OP22 is connected to the input terminal of the absolute value module ABS6.
[0111] The eleventh comparator includes an operational amplifier OP23. The inverting input of the operational amplifier OP23 is connected to the output of the absolute value module ABS6, the non-inverting input of the operational amplifier OP23 is grounded through power supply V28, and the output of the operational amplifier OP23 is connected to the twelfth comparator.
[0112] The twelfth comparator includes an NMOS transistor T8. The gate of the NMOS transistor T8 is connected to the output terminal of the operational amplifier OP23. The drain of the NMOS transistor T8 is connected to a resistor R40, which is connected to the positive terminal of the power supply V29. The source of the NMOS transistor T8 is connected to a resistor R41. The negative terminal of the power supply V29 and the resistor R41 are both grounded. The drain of the NMOS transistor T8 is the output signal terminal OUTV, which is connected to an OR gate.
[0113] The logic circuit VI includes a thirteenth comparator, NOT gate D12, AND gate D13, voltage summation unit SUM4, and voltage summation unit SUM5. The input of the thirteenth comparator is connected to the output of the absolute value module ABS2 of the synaptic neuron module II. The output of the thirteenth comparator is connected to one input of AND gate D13, and the other input of AND gate D13 is connected to the output of AND gate D1 of logic circuit I. The input signal terminal N6 is connected to the input of NOT gate D12. The outputs of NOT gate D12 and AND gate D13 are both connected to the input of voltage summation unit SUM4. The output of AND gate D13 is connected to the suppression module IV. The outputs of suppression module IV and voltage summation unit SUM4 are both connected to the input of voltage summation unit SUM5. The output of voltage summation unit SUM5 is connected to the input of synaptic neuron module VI. The output of synaptic neuron module VI is the output signal terminal OUTVI, which is connected to an OR gate.
[0114] The suppression module IV includes a tenth voltage control unit, a fourteenth proportional amplifier, and an absolute value module ABS7 connected in sequence. The input terminal of the tenth voltage control unit is connected to the output terminal of AND gate D13, and the output terminal of the absolute value module ABS7 is connected to one input terminal of the voltage summing unit SUM5.
[0115] The prominent neuron module VI includes a fifteenth proportional amplifier, an absolute value module ABS8, a fourteenth comparator, and a fifteenth comparator connected in sequence. The output terminal of the voltage summing unit SUM5 is connected to the input terminal of the fifteenth proportional amplifier, and the output terminal of the fifteenth comparator is the output signal terminal OUTVI.
[0116] The thirteenth comparator includes an operational amplifier OP7. The inverting input of the operational amplifier OP7 is connected to the output of the absolute value module ABS2. The non-inverting input of the operational amplifier OP7 is grounded through power supply V7. The output of the operational amplifier OP7 is connected to AND gate D13.
[0117] The tenth voltage control unit includes a voltage control switch S10. The output terminal of AND gate D13 is connected to the non-inverting input terminal of voltage control switch S10. The first contact of voltage control switch S10 is connected to the fourteenth proportional amplifier and resistor R42 respectively. The second contact of voltage control switch S10 is connected to the positive terminal of power supply V30. The negative terminal of power supply V30, resistor R42 and the inverting input terminal of voltage control switch S10 are all grounded.
[0118] The fourteenth proportional amplifier includes a memristor M9, an operational amplifier OP24, and a resistor R43. The positive terminal of the memristor M9 is connected to the first contact of the voltage-controlled switch S9, and the negative terminal of the memristor M9 is connected to the inverting input terminal of the operational amplifier OP24 and the resistor R43. The non-inverting input terminal of the operational amplifier OP24 is grounded, and the resistor R43 is connected to the output terminal of the operational amplifier OP24. The output terminal of the operational amplifier OP24 is connected to the absolute value module ABS7.
[0119] The fifteenth proportional amplifier includes a memristor M8, an operational amplifier OP25, and a resistor R44. The positive terminal of the memristor M8 is connected to the output terminal of the voltage summing unit SUM5, and the negative terminal of the memristor M8 is connected to the inverting input terminal of the operational amplifier OP25 and the resistor R44. The non-inverting input terminal of the operational amplifier OP25 is grounded, and the resistor R44 is connected to the output terminal of the operational amplifier OP25. The output terminal of the operational amplifier OP25 is connected to the input terminal of the absolute value module ABS8.
[0120] The fourteenth comparator includes an operational amplifier OP26. The inverting input of the operational amplifier OP26 is connected to the output of the absolute value module ABS8, the non-inverting input of the operational amplifier OP26 is grounded through power supply V31, and the output of the operational amplifier OP26 is connected to the fifteenth comparator.
[0121] The fifteenth comparator includes an NMOS transistor T9. The gate of the NMOS transistor T9 is connected to the output terminal of the operational amplifier OP26. The drain of the NMOS transistor T9 is connected to a resistor R45, which is connected to the positive terminal of the power supply V32. The source of the NMOS transistor T9 is connected to a resistor R46. The negative terminal of the power supply V32 and the resistor R46 are both grounded. The drain of the NMOS transistor T9 is the output signal terminal OUTVI, which is connected to an OR gate.
[0122] The logic circuit VII includes a sixteenth comparator, NOT gate D14, AND gate D15, voltage summation unit SUM6, and voltage summation unit SUM7. The input of the sixteenth comparator is connected to the output of the absolute value module ABS2 of the synaptic neuron module II. The output of the sixteenth comparator is connected to one input of AND gate D15, and the other input of AND gate D15 is connected to the output of AND gate D1 of logic circuit I. The input signal terminal N7 is connected to the input of NOT gate D14. The outputs of NOT gate D14 and AND gate D15 are both connected to the input of voltage summation unit SUM6. The output of AND gate D15 is connected to the suppression module V. The outputs of the suppression module V and voltage summation unit SUM4 are both connected to the input of voltage summation unit SUM7. The output of voltage summation unit SUM7 is connected to the input of synaptic neuron module VII. The output of synaptic neuron module VII is the output signal terminal OUTVII, which is connected to an OR gate.
[0123] The suppression module V includes an eleventh voltage control unit, a sixteenth proportional amplifier, and an absolute value module ABS9 connected in sequence. The input terminal of the eleventh voltage control unit is connected to the output terminal of AND gate D15, and the output terminal of the absolute value module ABS9 is connected to one input terminal of the voltage summing unit SUM7.
[0124] The prominent neuron module VII includes a seventeenth proportional amplifier, an absolute value module ABS10, a seventeenth comparator, and an eighteenth comparator connected in sequence. The output terminal of the voltage summing unit SUM7 is connected to the input terminal of the seventeenth proportional amplifier, and the output terminal of the eighteenth comparator is the output signal terminal OUTVII.
[0125] The sixteenth comparator includes an operational amplifier OP8. The inverting input of the operational amplifier OP8 is connected to the output of the absolute value module ABS2. The non-inverting input of the operational amplifier OP8 is grounded through power supply V8. The output of the operational amplifier OP6 is connected to AND gate D13.
[0126] The eleventh voltage control unit includes a voltage control switch S11. The output terminal of AND gate D15 is connected to the non-inverting input terminal of voltage control switch S10. The first contact of voltage control switch S10 is connected to the twelfth proportional amplifier and resistor R47 respectively. The second contact of voltage control switch S10 is connected to the positive terminal of power supply V33. The negative terminal of power supply V33, resistor R47 and the inverting input terminal of voltage control switch S10 are all grounded.
[0127] The sixteenth proportional amplifier includes a memristor M11, an operational amplifier OP27, and a resistor R48. The positive terminal of the memristor M11 is connected to the first contact of the voltage-controlled switch S11, and the negative terminal of the memristor M11 is connected to the inverting input terminal of the operational amplifier OP27 and the resistor R48. The non-inverting input terminal of the operational amplifier OP27 is grounded, and the resistor R48 is connected to the output terminal of the operational amplifier OP27. The output terminal of the operational amplifier OP27 is connected to the absolute value module ABS7.
[0128] The seventeenth proportional amplifier includes a memristor M10, an operational amplifier OP28, and a resistor R49. The positive terminal of the memristor M10 is connected to the output terminal of the voltage summing unit SUM7, and the negative terminal of the memristor M10 is connected to the inverting input terminal of the operational amplifier OP28 and the resistor R49. The non-inverting input terminal of the operational amplifier OP29 is grounded, and the resistor R49 is connected to the output terminal of the operational amplifier OP28. The output terminal of the operational amplifier OP28 is connected to the input terminal of the absolute value module ABS10.
[0129] The seventeenth comparator includes an operational amplifier OP29. The inverting input of the operational amplifier OP29 is connected to the output of the absolute value module ABS10. The non-inverting input of the operational amplifier OP29 is grounded through power supply V34. The output of the operational amplifier OP29 is connected to the eighteenth comparator.
[0130] The eighteenth comparator includes an NMOS transistor T10. The gate of the NMOS transistor T10 is connected to the output terminal of the operational amplifier OP29. The drain of the NMOS transistor T10 is connected to a resistor R50, which is connected to the positive terminal of the power supply V35. The source of the NMOS transistor T10 is connected to a resistor R51. The negative terminal of the power supply V35 and the resistor R51 are both grounded. The drain of the NMOS transistor T10 is the output signal terminal OUTⅦ, which is connected to an OR gate.
[0131] like Figure 3 As shown, 0-15s is the testing phase, 15-45s is the learning phase, and 45-95s is the generalization phase. After learning the food signal and the 500Hz electric bell signal, the 400Hz electric bell signal, the 800Hz electric bell signal, the 500Hz buzzer signal, the 400Hz buzzer signal, and the 800Hz buzzer signal can all make the dog drool.
[0132] like Figure 4 As shown, the 100-220s stage is the differentiation phase. After two training sessions, the 800Hz buzzer signal cannot produce saliva; after three training sessions, the 400Hz buzzer signal cannot produce saliva; and after four training sessions, the 500Hz buzzer signal cannot produce saliva. This illustrates how food and a 500Hz electric bell can learn to generalize and produce saliva. After 2-4 training sessions, different bell signals with different attributes are differentiated; this is primary differentiation. After six training sessions, the 800Hz electric bell signal cannot produce saliva; and after seven training sessions, the 400Hz electric bell signal cannot produce saliva. This illustrates how different frequencies of the same attribute of bell sounds can be differentiated after 6-7 training sessions; this is secondary differentiation, which requires more training than primary differentiation. Figure 6 As shown, the output signal of V(OP9) is a suppression voltage, used to separate two similar ringtones.
[0133] like Figure 5 As shown in (a), 0-180s represents the initial learning, generalization, differentiation, and forgetting process of food and a 500Hz electric bell. Figure 5 As shown in (b), the period from 247 to 400 seconds represents the second learning, generalization, differentiation, and forgetting process of food and the 500Hz electric bell. Figure 5 As shown in (c), 400-539 s represents the third learning, generalization, differentiation, and forgetting process of food and the 500Hz electric bell. During the third learning, the learning cycle is shorter than the first and second, indicating a faster learning speed; the third differentiation cycle is shorter than the first and second, indicating a faster differentiation speed; the forgetting cycle required for the third and second times is longer than that for the first time, indicating a slower forgetting speed.
[0134] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A memristor-based multi-modal generalization and differentiation associative memory neural network circuit, characterized by, The input signal end N1-N7, the synaptic neuron module I-VII, the inhibitory module I-V, and the output signal end are connected through an OR gate. The input signal end N1-N7 are seven pre-neurons, the pre-neuron N1 corresponds to the unconditioned reflex signal in Pavlov's associative memory, the pre-neurons N2-N7 correspond to the conditioned reflex signal, the pre-neuron N2 is a 500 Hz electric bell signal, the pre-neuron N3 is an 800 Hz electric bell signal, the pre-neuron N4 is a 400 Hz electric bell signal, the pre-neuron N5 is a 500 Hz buzzer signal, the pre-neuron N6 is an 800 Hz buzzer signal, the pre-neuron N7 is a 400 Hz buzzer signal, and the output signal end is a signal received by a post-neuron after stimulation.
2. The memristor-based multimodal generalization and differentiation associative memory neural network circuit of claim 1, wherein, The synaptic neuron module I includes a first proportional amplifier, the input signal end N1 is connected to the first proportional amplifier, the first proportional amplifier is connected to an absolute value module ABS1, the output end of the absolute value module ABS1 is an output signal end OUT1, and the output signal end OUT1 is connected to an OR gate.
3. The memristor-based multimodal generalization and differentiation associative memory neural network circuit of claim 2, wherein, The logic circuit I comprises a first voltage control unit, a second voltage control unit, an AND gate D1 and a voltage summing unit SUM1, the input signal end N1 and the input signal end N2 are connected with the AND gate D1, the output end of the AND gate D1 is connected with the first voltage control unit, the input signal end N2 is connected with the second voltage control unit, the first voltage control unit and the second voltage control unit are connected with two input ends of the voltage summing unit SUM1 respectively, and the output end of the voltage summing unit SUM1 is connected with the synaptic neuron module II; the first voltage control unit comprises a voltage control switch S1, the output end of the AND gate D1 is connected with the positive phase input end of the voltage control switch S1, the first contact of the voltage control switch S1 is connected with the first input end of the voltage summing unit SUM1 and a resistor R3 respectively, the second contact of the voltage control switch S1 is connected with the positive pole of a power supply V1, the negative pole of the power supply V1, the resistor R3 and the inverting input end of the voltage control switch S1 are grounded; the second voltage control unit comprises a voltage control switch S2, the positive phase input end of the voltage control switch S2 is connected with the input signal end N2, the first contact of the voltage control switch S2 is connected with the second input end of the voltage summing unit SUM1 and a resistor R4 respectively, the second contact of the voltage control switch S2 is connected with the positive pole of a power supply V2, the negative pole of the power supply V2, the resistor R4 and the inverting input end of the voltage control switch S2 are grounded.
4. The memristor-based multi-modal generalization and differentiation associative memory neural network circuit of any one of claims 1-3, wherein, The synaptic neuron module II comprises a second proportional amplifier, an absolute value module ABS2, a third proportional amplifier, a first comparator and a second comparator connected in sequence, the input end of the second proportional amplifier is connected with the voltage summation unit SUM1 of the logic circuit I, and the output end of the second comparator is connected with the OR gate; the second proportional amplifier comprises a memristor M1, an operational amplifier OP2 and a resistor R5, the positive end of the memristor M1 is connected with the output end of the voltage summation unit SUM1 of the logic circuit I, the negative end of the memristor M1 is connected with the inverting input end of the operational amplifier OP2 and the resistor R5 respectively, the non-inverting input end of the operational amplifier OP2 is grounded, the resistor R5 and the output end of the operational amplifier OP2 are connected, the output end of the operational amplifier OP2 is connected with the input end of the absolute value module ABS2, and the output end of the absolute value module ABS2 is connected with the third proportional amplifier; the third proportional amplifier comprises a resistor R6, an operational amplifier OP3 and a resistor R7, the output end of the absolute value module ABS2 is connected with the resistor R6, the resistor R6 is connected with the resistor R7 and the inverting input end of the operational amplifier OP3 respectively, the resistor R7 is connected with the output end of the operational amplifier OP3, the non-inverting input end of the operational amplifier OP3 is grounded, and the output end of the operational amplifier OP3 is connected with the first comparator; the second comparator comprises an operational amplifier OP4, the inverting input end of the operational amplifier OP4 is connected with the output end of the operational amplifier OP3, the non-inverting input end of the operational amplifier OP4 is connected with the positive electrode of the power supply V3, the negative electrode of the power supply V3 is grounded, and the output end of the operational amplifier OP4 is connected with the second comparator; the second comparator comprises an NMOS transistor T1, the gate of the NMOS transistor T1 is connected with the output end of the operational amplifier OP4, the drain of the NMOS transistor T1 is connected with a resistor R8, the resistor R8 is connected with the positive electrode of a power supply V4, the source of the NMOS transistor T1 is connected with a resistor R9, the negative electrode of the power supply V4 and the resistor R9 are grounded, the drain of the NMOS transistor T1 is an output signal end OUTII, and the output signal end OUTII is connected with the OR gate.
5. The memristor-based multimodal generalization and differentiation associative memory neural network circuit of claim 4, wherein, The logic circuit II comprises a third comparator, an AND gate D2 and a NOT gate D5, the input end of the third comparator is connected with the output end of the absolute value module ABS2 of the synaptic neuron module II, the output end of the third comparator and the output end of the AND gate D1 of the logic circuit I are both connected with the input end of the AND gate D2, the output end of the AND gate D2 is connected with the input end of the NOT gate D5, the output end of the NOT gate D5 is connected with the inhibition module I; the inhibition module I comprises a fourth comparator, an AND gate D6, a third voltage control unit and a fourth proportional amplifier, the output end of the NOT gate D5 is connected with the input end of the fourth comparator, the output end of the fourth comparator and the input signal end N3 are both connected with the input end of the AND gate D6, the output end of the AND gate D6 is connected with the third voltage control unit, the third voltage control unit is connected with the fourth proportional amplifier, the output end of the fourth proportional amplifier is connected with the logic circuit III; the logic circuit III comprises a first adder, a fifth proportional amplifier, a fourth voltage control unit, a fifth voltage control unit, a NOT gate D3 and an AND gate D4, the input signal end N3 is connected with the input end of the NOT gate D3, the output end of the NOT gate D3 and the output end of the AND gate D2 are both connected with the input end of the AND gate D4, the output end of the AND gate D4 is connected with the fourth voltage control unit, the input signal end N3 is connected with the fifth voltage control unit, the output ends of the fourth voltage control unit and the fifth voltage control unit are connected with the first adder, the first adder is connected with the fifth proportional amplifier, the fifth proportional amplifier is connected with the synaptic neuron module III; the synaptic neuron module III comprises a sixth proportional amplifier, an absolute value module ABS3, a seventh proportional amplifier, a fifth comparator and a sixth comparator connected in sequence, the output end of the fifth proportional amplifier is connected with the input end of the sixth proportional amplifier, the output end of the sixth comparator is an output signal end OUTIII, the output signal end OUTIII is connected with an OR gate.
6. The memristor-based multimodal generalization and differentiation associative memory neural network circuit of claim 5, wherein, The inhibition module II comprises a seventh comparator, an AND gate D4, a sixth voltage control unit and an eighth proportional amplifier, the seventh comparator is connected with the output end of the NOT gate D9, the input end of the NOT gate D9 is connected with the input signal N1, the output end of the seventh comparator and the input signal end N4 are connected with the input end of the AND gate D4, the output end of the AND gate D4 is connected with the input end of the sixth voltage control unit, the output end of the sixth voltage control unit is connected with the input end of the eighth proportional amplifier, the output end of the eighth proportional amplifier is connected with the logic circuit IV; the logic circuit IV comprises a second adder, a ninth proportional amplifier, a seventh voltage control unit, an eighth voltage control unit, a NOT gate D7 and an AND gate D8, the input signal end N4 is connected with the input end of the NOT gate D7, the output end of the NOT gate D7 and the output end of the AND gate D2 are all connected with the input end of the AND gate D8, the output end of the AND gate D8 is connected with the seventh voltage control unit, the input signal end N4 is connected with the eighth voltage control unit, the output ends of the seventh voltage control unit and the eighth voltage control unit are connected with the second adder, the second adder is connected with the ninth proportional amplifier, and the ninth proportional amplifier is connected with the synaptic neuron module IV; the synaptic neuron module IV comprises a tenth proportional amplifier, an absolute value module ABS4, an eleventh proportional amplifier, a ninth comparator and a tenth comparator which are connected in sequence, the output end of the ninth proportional amplifier is connected with the input end of the tenth proportional amplifier, the output end of the tenth comparator is an output signal end OUT IV, and the output signal end OUT IV is connected with an OR gate.
7. The memristor-based multi-modal generalization and differentiation associative memory neural network circuit of claim 6, wherein, The third comparator comprises an operational amplifier OP5, the inverting input end of the operational amplifier OP5 is connected with the output end of the absolute value module ABS2, the non-inverting input end of the operational amplifier OP5 is grounded through the power supply V5, and the output end of the operational amplifier OP5 is connected with one input end of the AND gate D2; The fourth comparator comprises an NMOS transistor T2 and a PMOS transistor T3, the output end of the NOT gate D5 is connected with the gate of the NMOS transistor T2, the drain of the NMOS transistor T2 is connected with the anode of the power supply V11 through the resistor R10, the source of the NMOS transistor T2 is connected with the anode of the power supply V12, the cathodes of the power supply V11 and the power supply V12 are both grounded, the drain of the NMOS transistor T2 is connected with the gate of the PMOS transistor T3, the drain of the PMOS transistor T3 is connected with the anode of the power supply V13 through the resistor R11, the source of the PMOS transistor T3 is connected with the anode of the power supply V14, the cathodes of the power supply V13 and the power supply V14 are both grounded, and the drain of the PMOS transistor T3 is connected with one input end of the AND gate D6; The third voltage control unit comprises a voltage control switch S5, the output end of the AND gate D6 is connected with the non-inverting input end of the voltage control switch S5, the first contact of the voltage control switch S5 is connected with the fourth proportional amplifier and the resistor R52 respectively, the second contact of the voltage control switch S5 is connected with the anode of the power supply V15, the cathode of the power supply V15, the resistor R52 and the inverting input end of the voltage control switch S5 are all grounded. The fourth proportional amplifier comprises a memristor M3, an operational amplifier OP9 and a resistor R12, the positive terminal of the memristor M3 is connected with the first contact of a voltage-controlled switch S5, the negative terminal of the memristor M3 is connected with the inverting input terminal of the operational amplifier OP9 and the resistor R12 respectively, the non-inverting input terminal of the operational amplifier OP9 is grounded, the resistor R12 and the output terminal of the operational amplifier OP9 are connected, and the output terminal of the operational amplifier OP9 is connected with the first adder; The first adder comprises a resistor R13, a resistor R14, a resistor R15 and an operational amplifier OP10, the resistor R13 is connected with the output terminal of the operational amplifier OP9, the resistor R14 is connected with a fourth voltage-controlled unit and a fifth voltage-controlled unit respectively, the resistor R13, the resistor R14 and the resistor R15 are connected with the non-inverting input terminal of the operational amplifier OP10, the resistor R15 is connected with the output terminal of the operational amplifier OP10, the inverting input terminal of the operational amplifier OP10 is grounded, and the output terminal of the operational amplifier OP10 is connected with a fifth proportional amplifier; The fifth proportional amplifier comprises a resistor R16, an operational amplifier OP11 and a resistor R17, the output terminal of the operational amplifier OP10 is connected with the resistor R16, the resistor R16 is connected with the resistor R17 and the inverting input terminal of the operational amplifier OP11 respectively, the resistor R17 is connected with the output terminal of the operational amplifier OP11, the non-inverting input terminal of the operational amplifier OP11 is grounded, and the output terminal of the operational amplifier OP11 is connected with a sixth proportional amplifier of the synaptic neuron module III; The fourth voltage-controlled unit comprises a voltage-controlled switch S3, the output terminal of an AND gate D4 is connected with the non-inverting input terminal of the voltage-controlled switch S3, the first contact of the voltage-controlled switch S3 is connected with the resistor R14, the second contact of the voltage-controlled switch S3 is connected with the positive electrode of a power supply V9, and the negative electrode of the power supply V9 and the inverting input terminal of the voltage-controlled switch S3 are grounded; The fifth voltage-controlled unit comprises a voltage-controlled switch S4, the input signal terminal N3 is connected with the non-inverting input terminal of the voltage-controlled switch S4, the first contact of the voltage-controlled switch S4 is connected with the resistor R14, the second contact of the voltage-controlled switch S4 is connected with the positive electrode of a power supply V10, and the negative electrode of the power supply V10 and the inverting input terminal of the voltage-controlled switch S4 are grounded; The sixth proportional amplifier comprises a memristor M2, an operational amplifier OP12 and a resistor R18, the positive terminal of the memristor M2 is connected with the output terminal of the operational amplifier OP11, the negative terminal of the memristor M2 is connected with the inverting input terminal of the operational amplifier OP12 and the resistor R18 respectively, the non-inverting input terminal of the operational amplifier OP12 is grounded, the resistor R18 and the output terminal of the operational amplifier OP12 are connected, and the output terminal of the operational amplifier OP12 is connected with an absolute value module ABS3; The seventh proportional amplifier comprises a resistor R19, an operational amplifier OP13 and a resistor R20, the output end of the absolute value module ABS3 is connected with the resistor R19, the resistor R19 is connected with the resistor R20 and the inverting input end of the operational amplifier OP13 respectively, the resistor R20 is connected with the output end of the operational amplifier OP13, the non-inverting input end of the operational amplifier OP13 is grounded, and the output end of the operational amplifier OP13 is connected with the fifth comparator; The fifth comparator comprises an operational amplifier OP14, the output end of the operational amplifier OP13 is connected with the inverting input end of the operational amplifier OP14, the non-inverting input end of the operational amplifier OP14 is grounded through the power supply V6, and the output end of the operational amplifier OP14 is connected with the sixth comparator; The sixth comparator comprises an NMOS transistor T4, the gate of the NMOS transistor T4 is connected with the output end of the operational amplifier OP14, the drain of the NMOS transistor T4 is connected with a resistor R21, the resistor R21 is connected with the positive pole of a power supply V17, the source of the NMOS transistor T4 is connected with a resistor R22, the negative pole of the power supply V17 and the resistor R22 are grounded, the drain of the NMOS transistor T4 is an output signal end OUTIII, and the output signal end OUTIII is connected with an OR gate; The seventh comparator comprises an NMOS transistor T5 and a PMOS transistor T6, the output end of the NOT gate D9 is connected with the gate of the NMOS transistor T5, the drain of the NMOS transistor T5 is connected with the positive pole of a power supply V20 through a resistor R23, the source of the NMOS transistor T5 is connected with the positive pole of a power supply V21, the negative poles of the power supply V20 and the power supply V21 are grounded, the drain of the NMOS transistor T5 is connected with the gate of the PMOS transistor T6, the drain of the PMOS transistor T6 is connected with the positive pole of a power supply V22 through a resistor R24, the source of the PMOS transistor T6 is connected with the positive pole of a power supply V23, the negative poles of the power supply V22 and the power supply V23 are grounded, and the drain of the PMOS transistor T6 is connected with one input end of the AND gate D4; The sixth voltage control unit comprises a voltage control switch S8, the output end of the AND gate D16 is connected with the non-inverting input end of the voltage control switch S8, the first contact of the voltage control switch S8 is connected with the eighth proportional amplifier and a resistor R25 respectively, the second contact of the voltage control switch S8 is connected with the positive pole of a power supply V24, the negative pole of the power supply V24, the resistor R25 and the inverting input end of the voltage control switch S8 are grounded; The eighth proportional amplifier comprises a memristor M5, an operational amplifier OP15 and a resistor R26, the positive end of the memristor M5 is connected with the first contact of the voltage control switch S8, the negative end of the memristor M5 is connected with the inverting input end of the operational amplifier OP15 and the resistor R26 respectively, the non-inverting input end of the operational amplifier OP15 is grounded, the resistor R26 and the output end of the operational amplifier OP15 are connected, and the output end of the operational amplifier OP15 is connected with the second adder; The second adder comprises resistors R27, R28, R29 and an operational amplifier OP16, the resistor R27 is connected with the output terminal of the operational amplifier OP15, the resistor R28 is connected with the seventh voltage control unit and the eighth voltage control unit respectively, the resistors R27, R28 and R29 are connected with the positive input terminal of the operational amplifier OP10, the resistor R27 is connected with the output terminal of the operational amplifier OP16, the inverting input terminal of the operational amplifier OP16 is grounded, and the output terminal of the operational amplifier OP16 is connected with the ninth proportional amplifier; The ninth proportional amplifier comprises a resistor R30, an operational amplifier OP17 and a resistor R31, the output terminal of the operational amplifier OP16 is connected with the resistor R30, the resistor R30 is connected with the resistor R31 and the inverting input terminal of the operational amplifier OP17 respectively, the resistor R31 is connected with the output terminal of the operational amplifier OP17, the positive input terminal of the operational amplifier OP17 is grounded, and the output terminal of the operational amplifier OP17 is connected with the tenth proportional amplifier of the synaptic neuron module IV; The seventh voltage control unit comprises a voltage control switch S6, the output terminal of the AND gate D8 is connected with the positive input terminal of the voltage control switch S6, the first contact of the voltage control switch S6 is connected with the resistor R28, the second contact of the voltage control switch S3 is connected with the positive electrode of the power supply V18, and the negative electrode of the power supply V18 and the inverting input terminal of the voltage control switch S6 are grounded; The eighth voltage control unit comprises a voltage control switch S7, the input signal terminal N4 is connected with the positive input terminal of the voltage control switch S7, the first contact of the voltage control switch S7 is connected with the resistor R28, the second contact of the voltage control switch S7 is connected with the positive electrode of the power supply V19, and the negative electrode of the power supply V19 and the inverting input terminal of the voltage control switch S7 are grounded; The tenth proportional amplifier comprises a memristor M4, an operational amplifier OP18 and a resistor R32, the positive terminal of the memristor M2 is connected with the output terminal of the operational amplifier OP17, the negative terminal of the memristor M2 is connected with the inverting input terminal of the operational amplifier OP12 and the resistor R32 respectively, the positive input terminal of the operational amplifier OP18 is grounded, the resistor R32 and the output terminal of the operational amplifier OP18 are connected, and the output terminal of the operational amplifier OP18 is connected with the absolute value module ABS4; The eleventh proportional amplifier comprises a resistor R33, an operational amplifier OP19 and a resistor R34, the output terminal of the absolute value module ABS4 is connected with the resistor R33, the resistor R33 is connected with the resistor R34 and the inverting input terminal of the operational amplifier OP19 respectively, the resistor R34 is connected with the output terminal of the operational amplifier OP19, the positive input terminal of the operational amplifier OP19 is grounded, and the output terminal of the operational amplifier OP13 is connected with the fifth comparator; The ninth comparator comprises an operational amplifier OP20, the output terminal of the operational amplifier OP19 is connected with the inverting input terminal of the operational amplifier OP20, the positive input terminal of the operational amplifier OP20 is grounded through the power supply V25, and the output terminal of the operational amplifier OP20 is connected with the tenth comparator; The tenth comparator comprises an NMOS transistor T7, a gate of the NMOS transistor T7 is connected with an output terminal of an operational amplifier OP20, a drain of the NMOS transistor T7 is connected with a resistor R35, the resistor R35 is connected with a positive pole of a power supply V26, a source of the NMOS transistor T7 is connected with a resistor R36, a negative pole of the power supply V26 and the resistor R36 are grounded, and the drain of the NMOS transistor T7 is an output signal terminal OUTIV, which is connected with an OR gate.
8. The memristor-based multi-modal generalization and differentiation associative memory neural network circuit of any one of claims 3, 5-7, wherein, The logic circuit V comprises the tenth comparator, a NOT gate D10, an AND gate D11, a voltage summing unit SUM2, a voltage summing unit SUM3, an input terminal of the tenth comparator is connected with an output terminal of the absolute value module ABS2 of the synaptic neuron module II, an output terminal of the tenth comparator is connected with one input terminal of the AND gate D11, another input terminal of the AND gate D11 is connected with an output terminal of the AND gate D1 of the logic circuit I, an input signal terminal N5 is connected with an input terminal of the NOT gate D10, an output terminal of the NOT gate D10 and an output terminal of the AND gate D11 are connected with input terminals of the voltage summing unit SUM2, the output terminal of the AND gate D11 is connected with the inhibition module III, output terminals of the inhibition module III and the voltage summing unit SUM2 are connected with input terminals of the voltage summing unit SUM3, an output terminal of the voltage summing unit SUM3 is connected with an input terminal of the synaptic neuron module V, and an output terminal of the synaptic neuron module V is an output signal terminal OUTV, which is connected with an OR gate. The inhibition module III comprises a ninth voltage control unit, a twelfth proportional amplifier and an absolute value module ABS5 connected in sequence, an input terminal of the ninth voltage control unit is connected with the output terminal of the AND gate D11, and an output terminal of the absolute value module ABS5 is connected with one input terminal of the voltage summing unit SUM3. The synaptic neuron module V comprises a thirteenth proportional amplifier, an absolute value module ABS6, an eleventh comparator and a twelfth comparator connected in sequence, an output terminal of the voltage summing unit SUM3 is connected with an input terminal of the thirteenth proportional amplifier, and an output terminal of the twelfth comparator is the output signal terminal OUTV. The logic circuit VI comprises a thirteenth comparator, a NOT gate D12, an AND gate D13, a voltage summing unit SUM4 and a voltage summing unit SUM5, the input end of the thirteenth comparator is connected with the output end of the absolute value module ABS2 of the synaptic neuron module II, the output end of the thirteenth comparator is connected with one input end of the AND gate D13, the other input end of the AND gate D13 is connected with the output end of the AND gate D1 of the logic circuit I; the input signal end N6 is connected with the input end of the NOT gate D12, the output end of the NOT gate D12 and the output end of the AND gate D13 are all connected with the input end of the voltage summing unit SUM4, the output end of the AND gate D13 is connected with the inhibition module IV, the output end of the inhibition module IV and the voltage summing unit SUM4 are all connected with the input end of the voltage summing unit SUM5, the output end of the voltage summing unit SUM5 is connected with the input end of the synaptic neuron module VI, the output end of the synaptic neuron module VI is the output signal end OUTVI, and the output signal end OUTVI is connected with the OR gate; The inhibition module IV comprises a tenth voltage control unit, a fourteenth proportional amplifier and an absolute value module ABS7 connected in sequence, the input end of the tenth voltage control unit is connected with the output end of the AND gate D13, and the output end of the absolute value module ABS7 is connected with one input end of the voltage summing unit SUM5; The synaptic neuron module VI comprises a fifteenth proportional amplifier, an absolute value module ABS8, a fourteenth comparator and a fifteenth comparator connected in sequence, the output end of the voltage summing unit SUM5 is connected with the input end of the fifteenth proportional amplifier, and the output end of the fifteenth comparator is the output signal end OUTVI; The logic circuit VII comprises a sixteenth comparator, a NOT gate D14, an AND gate D15, a voltage summing unit SUM6 and a voltage summing unit SUM7, the input end of the sixteenth comparator is connected with the output end of the absolute value module ABS2 of the synaptic neuron module II, the output end of the sixteenth comparator is connected with one input end of the AND gate D15, the other input end of the AND gate D15 is connected with the output end of the AND gate D1 of the logic circuit I; the input signal end N7 is connected with the input end of the NOT gate D14, the output end of the NOT gate D14 and the output end of the AND gate D15 are all connected with the input end of the voltage summing unit SUM6, the output end of the AND gate D15 is connected with the inhibition module V, the output end of the inhibition module V and the voltage summing unit SUM4 are all connected with the input end of the voltage summing unit SUM7, the output end of the voltage summing unit SUM7 is connected with the input end of the synaptic neuron module VII, the output end of the synaptic neuron module VII is the output signal end OUTVII, and the output signal end OUTVII is connected with the OR gate; The inhibition module V comprises an eleventh voltage control unit, a sixteenth proportional amplifier and an absolute value module ABS9 connected in sequence, the input end of the eleventh voltage control unit is connected with the output end of the AND gate D15, and the output end of the absolute value module ABS9 is connected with one input end of the voltage summing unit SUM7; The synaptic neuron module VII comprises a seventeenth proportional amplifier, an absolute value module ABS10, a seventeenth comparator and an eighteenth comparator connected in sequence, the output end of the voltage summation unit SUM7 is connected with the input end of the seventeenth proportional amplifier, and the output end of the eighteenth comparator is the output signal end OUTVII.
9. The memristor-based multi-modal generalization and differentiation associative memory neural network circuit of claim 8, wherein, The tenth comparator comprises an operational amplifier OP6, the inverting input end of the operational amplifier OP6 is connected with the absolute value module ABS2, the non-inverting input end of the operational amplifier OP6 is connected with the positive pole of the power supply V6, the negative pole of the power supply V5 is grounded, and the output end of the operational amplifier OP6 is connected with one input end of the AND gate D11; The ninth voltage control unit comprises a voltage control switch S9, the output end of the AND gate D11 is connected with the non-inverting input end of the voltage control switch S9, the first contact of the voltage control switch S9 is connected with the twelfth proportional amplifier and the resistor R37 respectively, the second contact of the voltage control switch S9 is connected with the positive pole of the power supply V27, and the negative pole of the power supply V27, the resistor R37 and the inverting input end of the voltage control switch S9 are grounded; The twelfth proportional amplifier comprises a memristor M7, an operational amplifier OP21 and a resistor R38, the positive end of the memristor M7 is connected with the first contact of the voltage control switch S9, the negative end of the memristor M7 is connected with the inverting input end of the operational amplifier OP21 and the resistor R38 respectively, the non-inverting input end of the operational amplifier OP21 is grounded, the resistor R38 and the output end of the operational amplifier OP21 are connected, and the output end of the operational amplifier OP21 is connected with the absolute value module ABS5; The thirteenth proportional amplifier comprises a memristor M6, an operational amplifier OP22 and a resistor R39, the positive end of the memristor M6 is connected with the output end of the voltage summation unit SUM3, the negative end of the memristor M6 is connected with the inverting input end of the operational amplifier OP22 and the resistor R39 respectively, the non-inverting input end of the operational amplifier OP22 is grounded, the resistor R39 and the output end of the operational amplifier OP22 are connected, and the output end of the operational amplifier OP22 is connected with the input end of the absolute value module ABS6; The eleventh comparator comprises an operational amplifier OP23, the inverting input end of the operational amplifier OP23 is connected with the output end of the absolute value module ABS6, the non-inverting input end of the operational amplifier OP23 is grounded through the power supply V28, and the output end of the operational amplifier OP23 is connected with the twelfth comparator; The twelfth comparator comprises an NMOS transistor T8, the gate of the NMOS transistor T8 is connected with the output end of the operational amplifier OP23, the drain of the NMOS transistor T8 is connected with the resistor R40, the resistor R40 is connected with the positive pole of the power supply V29, the source of the NMOS transistor T8 is connected with the resistor R41, the negative pole of the power supply V29 and the resistor R41 are grounded, and the drain of the NMOS transistor T8 is the output signal end OUTV, and the output signal end OUTV is connected with an OR gate. The thirteenth comparator comprises an operational amplifier OP7, the inverting input terminal of the operational amplifier OP7 is connected with the output terminal of the absolute value module ABS2, the non-inverting input terminal of the operational amplifier OP7 is grounded through the power supply V7, and the output terminal of the operational amplifier OP7 is connected with the AND gate D13; The tenth voltage control unit comprises a voltage control switch S10, the output terminal of the AND gate D13 is connected with the non-inverting input terminal of the voltage control switch S10, the first contact of the voltage control switch S10 is connected with the fourteenth proportional amplifier and the resistor R42 respectively, the second contact of the voltage control switch S10 is connected with the positive pole of the power supply V30, and the negative pole of the power supply V30, the resistor R42 and the inverting input terminal of the voltage control switch S10 are grounded; The fourteenth proportional amplifier comprises a memristor M9, an operational amplifier OP24 and a resistor R43, the positive terminal of the memristor M9 is connected with the first contact of the voltage control switch S9, the negative terminal of the memristor M9 is connected with the inverting input terminal of the operational amplifier OP24 and the resistor R43 respectively, the non-inverting input terminal of the operational amplifier OP24 is grounded, the resistor R43 and the output terminal of the operational amplifier OP24 are connected, and the output terminal of the operational amplifier OP24 is connected with the absolute value module ABS7; The fifteenth proportional amplifier comprises a memristor M8, an operational amplifier OP25 and a resistor R44, the positive terminal of the memristor M8 is connected with the output terminal of the voltage sum unit SUM5, the negative terminal of the memristor M8 is connected with the inverting input terminal of the operational amplifier OP25 and the resistor R44 respectively, the non-inverting input terminal of the operational amplifier OP25 is grounded, the resistor R44 and the output terminal of the operational amplifier OP25 are connected, and the output terminal of the operational amplifier OP25 is connected with the input terminal of the absolute value module ABS8; The fourteenth comparator comprises an operational amplifier OP26, the inverting input terminal of the operational amplifier OP26 is connected with the output terminal of the absolute value module ABS8, the non-inverting input terminal of the operational amplifier OP26 is grounded through the power supply V31, and the output terminal of the operational amplifier OP26 is connected with the fifteenth comparator; The fifteenth comparator comprises an NMOS transistor T9, the gate of the NMOS transistor T9 is connected with the output terminal of the operational amplifier OP26, the drain of the NMOS transistor T9 is connected with the resistor R45, the resistor R45 is connected with the positive pole of the power supply V32, the source of the NMOS transistor T9 is connected with the resistor R46, the negative pole of the power supply V32 and the resistor R46 are grounded, and the drain of the NMOS transistor T9 is the output signal terminal OUT VI, and the output signal terminal OUT VI is connected with the OR gate; The sixteenth comparator comprises an operational amplifier OP8, the inverting input terminal of the operational amplifier OP8 is connected with the output terminal of the absolute value module ABS2, the non-inverting input terminal of the operational amplifier OP8 is grounded through the power supply V8, and the output terminal of the operational amplifier OP6 is connected with the AND gate D13. The eleventh voltage control unit comprises a voltage control switch S11, an output end of the gate D15 is connected with a positive input end of the voltage control switch S10, a first contact of the voltage control switch S10 is connected with the twelfth proportional amplifier and the resistor R47 respectively, a second contact of the voltage control switch S10 is connected with a positive pole of the power supply V33, a negative pole of the power supply V33, the resistor R47 and an inverting input end of the voltage control switch S10 are grounded; The sixteenth proportional amplifier comprises the memristor M11, the operational amplifier OP27 and the resistor R48, a positive end of the memristor M11 is connected with the first contact of the voltage control switch S11, a negative end of the memristor M11 is connected with the inverting input end of the operational amplifier OP27 and the resistor R48 respectively, a positive input end of the operational amplifier OP27 is grounded, the resistor R48 and an output end of the operational amplifier OP27 are connected, and the output end of the operational amplifier OP27 is connected with the absolute value module ABS7; The seventeenth proportional amplifier comprises the memristor M10, the operational amplifier OP28 and the resistor R49, a positive end of the memristor M10 is connected with an output end of the voltage sum unit SUM7, a negative end of the memristor M10 is connected with the inverting input end of the operational amplifier OP28 and the resistor R49 respectively, a positive input end of the operational amplifier OP29 is grounded, the resistor R49 and an output end of the operational amplifier OP28 are connected, and the output end of the operational amplifier OP28 is connected with an input end of the absolute value module ABS10; The seventeenth comparator comprises the operational amplifier OP29, an inverting input end of the operational amplifier OP29 is connected with an output end of the absolute value module ABS10, a positive input end of the operational amplifier OP29 is grounded through the power supply V34, and an output end of the operational amplifier OP29 is connected with the eighteenth comparator; The eighteenth comparator comprises the NMOS tube T10, a gate of the NMOS tube T10 is connected with the output end of the operational amplifier OP29, a drain of the NMOS tube T10 is connected with the resistor R50, the resistor R50 is connected with a positive pole of the power supply V35, a source of the NMOS tube T10 is connected with the resistor R51, a negative pole of the power supply V35 and the resistor R51 are grounded, and the drain of the NMOS tube T10 is an output signal end OUTVII, and the output signal end OUTVII is connected with the OR gate.
Citation Information
Patent Citations
Bavlov dual-mode switching learning memory circuit based on memristor
CN110910723A