semiconductor element

Abstract

A semiconductor device includes a first semiconductor region; and a first electrode on the first semiconductor region, wherein the first semiconductor region includes a first layer and a second layer, the second layer includes a first portion and a second portion adjacent to the first portion, the first portion has a first thickness, the second portion has a second thickness, the second thickness is less than the first thickness, the first layer includes a first material and a first dopant, the first material includes a plurality of elements, the first dopant has a first concentration, the second layer includes a second material and a second dopant, the second material includes a plurality of elements, the second dopant has a second concentration, one of the plurality of elements of the first material of the first layer is different from the plurality of elements of the second material of the second layer.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number: 201811451716.8, application date: November 30, 2018, invention title: semiconductor element). Technical Field

[0002] The present invention relates to a semiconductor device, and more particularly to a semiconductor device comprising a first semiconductor region, wherein the first semiconductor region comprises a first layer and a second layer. Background Technology

[0003] Light-emitting diodes (LEDs) are widely used in solid-state lighting. Compared to traditional incandescent bulbs and fluorescent lamps, LEDs have advantages such as low power consumption and long lifespan. Therefore, LEDs have gradually replaced traditional light sources and are used in various fields, such as traffic signals, backlight modules, street lighting, and medical equipment. Summary of the Invention

[0004] This invention provides a semiconductor device. The semiconductor device includes: a first semiconductor region; a second semiconductor region located on the first semiconductor region; an active region located between the first semiconductor region and the second semiconductor region; and a first electrode located on the first semiconductor region; wherein the first semiconductor region includes a first layer and a second layer located between the first layer and the active region, the second layer includes a first portion and a second portion adjacent to the first portion, the first portion overlapping the active region in a stacking direction and having a first thickness, the second portion having a second thickness less than the first thickness, the first layer including a first material and a first dopant, the first material including multiple elements and the first dopant having a first concentration, the second layer including a second material and a second dopant, the second material including multiple elements and the second dopant having a second concentration, one of the multiple elements of the first material of the first layer being different from the multiple elements of the second material of the second layer, the first concentration of the first dopant of the first layer being greater than the second concentration of the second dopant of the second layer, and the first electrode located on the second portion of the second layer.

[0005] The present invention also provides a semiconductor device. The semiconductor device includes: a first semiconductor region; a second semiconductor region located on the first semiconductor region; an active region located between the first semiconductor region and the second semiconductor region; a spacer layer located between the first semiconductor region and the active region, the spacer layer including a first intermediate layer and a second intermediate layer located on the first intermediate layer, the first intermediate layer including a dopant of a certain concentration, the second intermediate layer including a dopant of a certain concentration, the concentration of the dopant in the first intermediate layer being higher than the concentration of the dopant in the second intermediate layer; and a first electrode located on the first semiconductor region; wherein the first semiconductor region includes a first layer located under the spacer layer, the first layer including a first dopant of a first concentration, and the first concentration being higher than the concentration of the dopant in the first intermediate layer. Attached Figure Description

[0006] Figure 1 This is a cross-sectional view of a semiconductor element according to a first embodiment of the present invention;

[0007] Figure 2 This is a top view of a semiconductor element according to a second embodiment of the present invention;

[0008] Figure 3 This is a cross-sectional view of a semiconductor element according to a third embodiment of the present invention;

[0009] Figure 4 This is a graph showing the relationship between elemental concentration or ion intensity and depth for a portion of a semiconductor element according to the fifth embodiment of the present invention.

[0010] Figure 5 This is a cross-sectional view of a semiconductor element according to the sixth embodiment of the present invention.

[0011] Symbol Explanation

[0012] 1, 2, 3, 4: Semiconductor components

[0013] 10: Substrate

[0014] 20: First semiconductor region

[0015] 30: Second semiconductor region

[0016] 40: Active region

[0017] 50: First electrode

[0018] 60: Second electrode

[0019] 21: First Floor

[0020] 22: Second layer

[0021] 221: First Part

[0022] 222: Second Part

[0023] D: Stacking direction

[0024] t1: First thickness

[0025] t2: Second thickness

[0026] t3: Third thickness

[0027] 223: Sidewall

[0028] d1: Minimum distance

[0029] 51: First electrode pad

[0030] 52: First extension part

[0031] D1: First Direction

[0032] W1, W2, W3, W4: Width

[0033] d 11 First minimum distance

[0034] d 12 Second minimum distance

[0035] 61: Second electrode pad

[0036] 62: Second extension part

[0037] 70: Spacer layer

[0038] 80: Aluminum-containing layer Detailed Implementation

[0039] The following embodiments will illustrate the concept of the invention with the accompanying drawings. In the drawings or description, similar or identical parts are referred to by the same reference numerals, and the shape or thickness of elements may be enlarged or reduced in the drawings. It should be particularly noted that elements not shown in the drawings or described in the specification may be in forms known to those skilled in the art.

[0040] In this invention, unless otherwise specified, the general formula AlGaN represents Al x1 Ga (1-x1) N, where 0 ≤ x1 ≤ 1; the general formula InGaN represents In x2 Ga 1–x2 N, where 0 ≤ x² ≤ 1; the general formula InAlGaN represents In x3 Al y1 Ga 1-x3-y1N, where 0≤x3≤1, 0≤y1≤1. Adjusting the content of elements can achieve different purposes, such as, but not limited to, adjusting the energy level or, when the semiconductor device includes a light-emitting element, adjusting the main emission wavelength of the light-emitting element.

[0041] In the following embodiments, terms used to indicate direction, such as "up," "down," "front," "back," "left," and "right," refer only to the direction shown in the accompanying drawings. Therefore, directional terms are used for illustration and not to limit the invention.

[0042] The composition of each layer and dopants in the semiconductor device of the present invention can be analyzed by any suitable method, such as secondary ion mass spectrometry (SIMS).

[0043] The thickness of each layer in the semiconductor element of the present invention can be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscopy (SEM), to correspond to the depth positions of each layer, for example, on a SIMS map.

[0044] The semiconductor device of the present invention includes a light-emitting element. The light-emitting element includes a light-emitting diode or a laser.

[0045] Figure 1 This is a cross-sectional view of a semiconductor element according to a first embodiment of the present invention. In this embodiment, the semiconductor element 1 includes a substrate 10, a first semiconductor region 20 located on the substrate 10, a second semiconductor region 30 located on the first semiconductor region 20, and an active region 40 located between the first semiconductor region 20 and the second semiconductor region 30. The semiconductor element 1 also includes a first electrode 50 and a second electrode 60. The first electrode 50 is located on and electrically connected to the first semiconductor region 20. The second electrode 60 is located on and electrically connected to the second semiconductor region 30.

[0046] Please see Figure 1, the first semiconductor region 20 includes a first layer 21 and a second layer 22. The first layer 21 is located between the substrate 10 and the active region 40. The second layer 22 is located between the first layer 21 and the active region 40. The second layer 22 includes a first portion 221 and a second portion 222 adjacent to the first portion 221. The first portion 221 overlaps with the active region 40 in a stacking direction D. The first electrode 50 is located on the second portion 222 of the second layer 22 and does not overlap with the first portion 221 of the second layer 22 in the stacking direction D. Specifically, the first electrode 50 overlaps with the second portion 222 in the stacking direction D. The first portion 221 has a first thickness t1. The second portion 222 has a second thickness t2 less than the first thickness t1. The first electrode 50 is closer to the second portion 222 than the first layer 21. The first thickness t1 is not less than 100 nanometers (nm), preferably not greater than 1000 nm. Preferably, the first thickness t1 is between 200 nm and 1000 nm (including the end values). If the first thickness t1 is greater than 1000 nm, the forward voltage of the semiconductor element 1 will become higher. The second thickness t2 is not less than 30 nm, and preferably not greater than 400 nm. If the second thickness t2 is less than 30 nm, the current diffusion of the semiconductor element 1 will deteriorate and the forward voltage will become higher.

[0047] The first layer 21 includes a first material and a first dopant. The first material includes multiple elements. The first dopant has a first concentration. The second layer 22 includes a second material and a second dopant. The second material includes multiple elements. The second dopant has a second concentration. One of the multiple elements of the first material of the first layer 21 is different from the element of the second material of the second layer 22. The first material has an energy level. The second material has an energy level. In one embodiment, in order to improve the light-emitting efficiency, the energy level of the first material is greater than the energy level of the second material. In one embodiment, the first material includes a III-V group semiconductor material, and the second material includes a III-V group semiconductor material. In one embodiment, the multiple elements of the first material include aluminum (Al), gallium (Ga), and nitrogen (N), the multiple elements of the second material include gallium (Ga) and nitrogen (N), and substantially do not contain aluminum (Al). In this embodiment, the first material includes Al a Ga 1-a N, where 0 < a ≤ 0.1, and preferably, 0 < a ≤ 0.05. The second material includes GaN and substantially does not contain aluminum (Al).

[0048] In one embodiment, the first concentration of the first dopant in the first layer 21 is greater than the second concentration of the second dopant in the second layer 22. Preferably, the ratio of the first concentration of the first dopant in the first layer 21 to the second concentration of the second dopant in the second layer 22 is not greater than 10, and more preferably, not less than 1.1, and more preferably, between 1.2 and 8 (inclusive). The first concentration of the first dopant in the first layer 21 is not less than 1 × 10⁻⁶. 18 / cm 3 Preferably, it should not exceed 1×10 22 / cm 3 More preferably, the first concentration of the first dopant in the first layer 21 is between 5 × 10⁻⁶. 18 / cm 3 Up to 1×10 20 / cm 3 Between (including the endpoints). If the first concentration of the first dopant in the first layer 21 is greater than 1 × 10⁻⁶. 20 / cm 3 If the forward voltage of semiconductor device 1 increases, the luminous efficiency of semiconductor device 1 will also decrease. If the first concentration of the first dopant in the first layer 21 is less than 1 × 10⁻⁶, the forward voltage of semiconductor device 1 will increase, and the luminous efficiency of semiconductor device 1 will also decrease. 18 / cm 3 If this happens, the current diffusion of semiconductor element 1 will deteriorate. The second concentration of the second dopant in the second layer 22 is not less than 1 × 10⁻⁶. 18 / cm 3 Preferably, it is no greater than 1×10 21 / cm 3 More preferably, the second concentration of the second dopant in the second layer 22 is between 5 × 10⁻⁶. 18 / cm 3 and 5×10 19 / cm 3 Between (including the end values). If the second concentration of the second dopant in the second layer 22 is less than 5 × 10⁻⁶. 18 / cm 3 If this happens, the electrostatic discharge (ESD) protection capability of semiconductor device 1 will deteriorate. In this embodiment, the first dopant of the first layer 21 is the same as the second dopant of the second layer 22. In this embodiment, the first layer 21 and the second layer 22 have the same conductivity type. In this embodiment, the first layer 21 and the second layer 22 are n-type. In this embodiment, the first dopant includes, but is not limited to, silicon (Si), and the second dopant includes, but is not limited to, silicon (Si).

[0049] In this embodiment, since the first electrode 50 is closer to the second layer 22 than the first layer 21, and the first material of the first layer 21 contains an element that is different from the element of the second material of the second layer, and the second concentration of the second dopant in the second layer 22 is lower than the first concentration of the first dopant in the first layer 21, the semiconductor device 1 has both improved luminous efficiency and lower forward voltage.

[0050] In one embodiment, the first layer 21 has a third thickness t3, which is greater than the first thickness t1 of the first portion 221 of the second layer 22 in order to reduce the forward voltage of the semiconductor device 1. The ratio of the third thickness t3 of the first layer 21 to the first thickness t1 of the first portion 221 is not less than 2, and preferably not greater than 10. By controlling the ratio of the third thickness t3 to the first thickness t1, the semiconductor device 1 has improved current diffusion performance. In one embodiment, the third thickness t3 is not less than 500 nm, and preferably not greater than 3000 nm. Preferably, to further reduce the forward voltage of the semiconductor device 1, the third thickness t3 is between 1000 nm and 2000 nm (inclusive).

[0051] Please see Figure 1 The second layer 22 includes a sidewall 223 above the second portion 222. Viewed in cross-section of the semiconductor element 1, the sidewall 223 is located between the first portion 221 and the first electrode 50. Viewed in cross-section of the semiconductor element 1, to improve current diffusion in the semiconductor element 1, a minimum distance d1 between the sidewall 223 and the first electrode 50 is greater than a second thickness t2. Preferably, to further improve current diffusion in the semiconductor element 1, the ratio of the minimum distance d1 to the second thickness t2 is greater than 10, and more preferably, greater than 40, and more preferably, not greater than 200. In one embodiment, to prevent or reduce leakage current in the semiconductor element 1, the minimum distance d1 between the sidewall 223 and the first electrode 50 is not less than 5000 nm. In one embodiment, the minimum distance d1 between the sidewall 223 and the first electrode 50 is not less than 10000 nm.

[0052] Figure 2 This is a top view of a semiconductor element 2 according to a second embodiment of the present invention. The semiconductor element 2 of the second embodiment of the present invention has a structure substantially the same as that of the semiconductor element 1 of the first embodiment, and the differences between the two will be described below. In this embodiment, the first electrode 50 includes a first electrode pad 51 and a first extension portion 52 extending from the first electrode pad 51. The first electrode pad 51 has a width W1 along a first direction D1. The first extension portion 52 has a width W2 along the first direction D1. The width W1 of the first extension portion 52 is smaller than the width W2 of the first electrode pad 51. There is a first minimum distance d between the sidewall 223 and the first electrode pad 51. 11There is a second minimum distance d between the sidewall 223 and the first extension portion 52. 12 The preferred second minimum distance d 12 Less than the first minimum distance d 11 In one embodiment, to prevent or reduce leakage current of semiconductor element 2, a first minimum distance d is used. 11 Not less than 10000 nm, second minimum distance d 12 Not less than 5000 nm. In this embodiment, the second electrode 60 includes a second electrode pad 61 and two second extension portions 62 extending from the second electrode pad 61. The second electrode pad 61 has a width W3 along the first direction D1. Each second extension portion 62 has a width W4 along the first direction D1. The width W4 of each second extension portion 62 is smaller than the width W3 of the second electrode pad 61.

[0053] Figure 3 This is a cross-sectional view of a semiconductor element 3 according to a third embodiment of the present invention. The semiconductor element 3 of the third embodiment of the present invention has a structure substantially the same as that of the semiconductor element 1 of the first embodiment, and the differences between the two will be described below. In this embodiment, the semiconductor element 3 further includes a spacer layer 70 located between the second layer 22 and the active region 40. Preferably, the spacer layer 70 includes an energy level that is lower than the energy level of the first layer 21. In one embodiment, the spacer layer 70 includes In b Al c Ga 1-b-c N, where 0 ≤ b ≤ 1, 0 ≤ c ≤ 1. In one embodiment, the material of spacer layer 70 is the same as the second material of second layer 22. In one embodiment, spacer layer 70 comprises GaN. Spacer layer 70 comprises a third dopant having a third concentration. In this embodiment, the third dopant is the same as the second dopant of second layer 22. In this embodiment, to further reduce the forward voltage and improve the electrostatic discharge immunity of semiconductor device 3, the third concentration of the third dopant in spacer layer 70 is lower than the second concentration of the second dopant in second layer 22. In one embodiment, the third concentration of the third dopant in spacer layer 70 is not less than 1 × 10⁻⁶. 17 / cm 3 And preferably, not exceeding 5×10 18 / cm 3To further reduce the forward voltage of semiconductor device 3, the ratio of the second concentration of the second dopant in the second layer 22 to the third concentration of the third dopant in the spacer layer 70 is greater than the ratio of the first concentration of the first dopant in the first layer 21 to the second concentration of the second dopant in the second layer 22. Preferably, the ratio of the second concentration of the second dopant in the second layer 22 to the third concentration of the third dopant in the spacer layer 70 is not less than 10, and more preferably, not greater than 50. To further reduce the forward voltage of semiconductor device 3, the ratio of the second concentration of the second dopant in the second layer 22 to the third concentration of the third dopant in the spacer layer 70 is at least 3 times the ratio of the first concentration of the first dopant in the first layer 21 to the second concentration of the second dopant in the second layer 22, and more preferably, between 5 times and 50 times (inclusive). In one embodiment, the spacer layer 70 has a fourth thickness, which is less than the third thickness t3. Preferably, the fourth thickness is not less than 50 nm, and more preferably, not greater than 1000 nm, and even more preferably, between 100 nm and 500 nm (inclusive). If the fourth thickness is less than 50 nm, the electrostatic discharge immunity of the semiconductor element 3 will deteriorate, and the forward voltage of the semiconductor element 3 will increase. In this embodiment, by simultaneously including a spacer layer 70 and a first electrode 50 being closer to the second layer 22 than the first layer 21, and the first material of the first layer 21 containing an element different from the second material of the second layer, and the second concentration of the second dopant in the second layer 22 being lower than the first concentration of the first dopant in the first layer 21, the semiconductor element 3 simultaneously has improved luminous efficiency, lower forward voltage, and better electrostatic discharge immunity.

[0054] In a fourth embodiment of the present invention (not shown), the semiconductor element of the fourth embodiment comprises a structure substantially the same as that of the semiconductor element 3 of the third embodiment, and the differences between the two will be described below. In this embodiment, the spacer layer 70 comprises a first intermediate layer (not shown) and a second intermediate layer (not shown) located on the first intermediate layer, wherein the first intermediate layer comprises a dopant of a certain concentration, the second intermediate layer comprises a dopant of a certain concentration, and the concentration of the dopant in the first intermediate layer is greater than the concentration of the dopant in the second intermediate layer. In this embodiment, the dopant in the first intermediate layer is the same as the dopant in the second intermediate layer. In this embodiment, the dopant in the first intermediate layer comprises, but is not limited to, Si. The dopant in the second intermediate layer comprises, but is not limited to, Si. The concentration of the dopant in the first intermediate layer is not less than 5 × 10⁻⁶. 17 / cm 3 Preferably, it should not exceed 5×10 18 / cm 3 The concentration of dopant in the second intermediate layer is not less than 1 × 10⁻⁶. 17 / cm 3 Preferably, it is no greater than 1×1018 / cm 3 In one embodiment, the material of the first intermediate layer is substantially the same as the material of the second intermediate layer. In this embodiment, the materials of the first intermediate layer and the second intermediate layer include GaN.

[0055] In a fifth embodiment (not shown in the figure) of the present invention, the structure included in the semiconductor element of the fifth embodiment of the present invention is substantially the same as the structure included in the semiconductor element of the fourth embodiment, and the differences therebetween will be described below. Figure 4 It is a graph showing the relationship between the concentration of silicon element and the intensity of aluminum element with depth for a partial range of the semiconductor element of the fifth embodiment of the present invention, where the graph is measured by a secondary ion mass spectrometer. Some elements of the semiconductor element are not shown in Figure 4 For example, nitrogen (N) and gallium (Ga). In this embodiment, the spacer layer 70 includes a plurality of alternating first intermediate layers and a plurality of second intermediate layers. A single first intermediate layer and the single second intermediate layer adjacent thereto are regarded as a pair. In one embodiment, the number of pairs of the first intermediate layer and the second intermediate layer is not less than 2, and preferably, not more than 10. In one embodiment, the first intermediate layer includes a thickness between 15 nm and 40 nm (including the end values). The second intermediate layer includes a thickness between 15 nm and 40 nm (including the end values). Since the spacer layer 70 includes two intermediate layers, and the two intermediate layers include dopants with different concentrations, the electrostatic discharge resistance and the light emission efficiency of the semiconductor element can be further improved simultaneously.

[0056] Figure 5 It is a cross-sectional view of the semiconductor element of the sixth embodiment of the present invention. The structure included in the semiconductor element 4 of the sixth embodiment of the present invention is substantially the same as the structure included in the semiconductor element of the fifth embodiment, and the differences therebetween will be described below. In this embodiment, the semiconductor element 4 further includes an aluminum-containing layer 80 located under the first semiconductor region 20. The aluminum-containing layer 80 includes an energy level that is greater than the energy level of the first layer 21. The aluminum-containing layer 80 can reduce the leakage current of the semiconductor element 4. In one embodiment, the aluminum-containing layer 80 includes Al d Ga 1-d N, where 0 < d ≤ 0.3, and a < d, where the first material of the first layer 21 includes Al a Ga 1-a N. In one embodiment, the thickness of the aluminum-containing layer 80 is less than the third thickness t3 of the first layer 21. The thickness of the aluminum-containing layer 80 is not less than 15 nm, and preferably, not more than 60 nm. In this embodiment, the aluminum-containing layer 80 is unintentionally doped.

[0057] In the present invention, the second semiconductor region 30 of the semiconductor element in any embodiment includes a contact layer, and the contact layer includes a p-type dopant. Preferably, the concentration of the p-type dopant in the contact layer is not less than 1×10 18 / cm 3 , preferably, not less than 1×10 19 / cm 3 , more preferably, between 1×10 19 / cm 3 and 5×10 22 / cm 3 (including the end values). The material of the contact layer includes III-V semiconductor materials, such as Al e Ga 1-e N, where 0≤e≤1. In another embodiment, the contact layer includes GaN. The thickness of the contact layer is not greater than 15 nm, preferably, not less than 3 nm.

[0058] In the present invention, the active region 40 of the semiconductor element in any embodiment includes a plurality of well layers (not shown in the figure) and a plurality of barrier layers (not shown in the figure) that alternate. Each barrier layer has an energy level. Each well layer has an energy level. In one embodiment, the energy level of one of the barrier layers is not less than the energy level of one of the well layers, and preferably, higher than the energy level of one of the well layers. Preferably, the energy level of each barrier layer is not less than the energy level of each well layer, and preferably, higher than the energy level of each well layer. The well layer includes III-V semiconductor materials. In this embodiment, the well layer includes In f Ga 1-f N, where 0<f≤1. In another embodiment, the well layer includes Al g Ga 1-g N, where 0<g≤1, and preferably, 0<g≤0.4. The barrier layer includes Al h Ga 1-h N, where 0≤h≤1. In one embodiment, 0<h≤0.6. In another embodiment, the barrier layer includes GaN. The thickness of each barrier layer is greater than the thickness of one of the well layers. Preferably, the thickness of each barrier layer is greater than the thickness of each well layer. Preferably, the thickness of each barrier layer is not greater than 15 nm and not less than 3 nm. The thickness of each well layer is not greater than 5 nm and not less than 1 nm. A single well layer and the single barrier layer adjacent thereto are regarded as a pair. The number of pairs of well layers and barrier layers is not less than 4, and preferably, not greater than 15.

[0059] In one embodiment, the size of the semiconductor element is 200 microns × 480 microns. For the active region 40 of the semiconductor element, taking the semiconductor element 1 in the first embodiment as an example, its area is approximately 92,600 square microns (μm 2Furthermore, when semiconductor device 1 operates at approximately 20 milliamperes (mA), the forward voltage of semiconductor device 1 is approximately 3 volts (V), and the current density of active region 40 is approximately 0.2 amperes per square millimeter (A / mm²). 2 In one embodiment, the semiconductor element has a size of 130 micrometers × 240 micrometers, and the active region 40 of the semiconductor element, for example, semiconductor element 3,4, has an area of ​​approximately 14250 square micrometers (μm). 2 Under the condition that the operating current range of semiconductor devices 3 and 4 is between 0.1mA and 5mA (inclusive), preferably between 0.1mA and 2mA (inclusive), and more preferably between 0.5mA and 1mA (inclusive), the forward voltage of semiconductor devices 3 and 4 is between 2.6V and 2.8V (inclusive), and the current density of active region 40 is between 0.007A / mm². 2 Up to 0.35A / mm 2 (Including the endpoints), preferably, it is between 0.007 A / mm. 2 Up to 0.14A / mm 2 (Including the endpoints), and preferably between 0.035A / mm 2 Up to 0.07A / mm 2 Below a current density (including the terminal value). In one embodiment, the semiconductor device operates at a current density between 0.005 A / mm². 2 Up to 0.6A / mm 2 (Including the endpoints), preferably, it is between 0.005A / mm. 2 Up to 0.3A / mm 2 (Including the end values), and preferably between 0.005A / mm 2 Up to 0.1A / mm 2 Below the current density (including terminal value).

[0060] In this invention, the semiconductor element in any embodiment further includes a buffer layer (not shown) located between the substrate 10 and the first semiconductor region 20. The buffer layer is used to reduce defects and improve the quality of the epitaxial layer grown thereon. In one embodiment, the buffer layer includes Al. i Ga 1–i N, where 0 ≤ i ≤ 1. In one embodiment, the buffer layer comprises GaN. In another embodiment, the buffer layer comprises AlN. The buffer layer can be formed by epitaxy or physical vapor deposition (PVD). Physical vapor deposition includes sputtering or electron beam evaporation.

[0061] In this invention, the substrate 10 of the semiconductor element in any embodiment has a sufficient thickness to support the layers and structures located thereon, for example, not less than 50 μm, and more preferably not more than 300 μm. In one embodiment, the substrate 10 comprises sapphire, which includes a surface and periodic protrusions formed on the surface. In another embodiment, the substrate 10 comprises a conductive material, including Si, germanium (Ge), copper (Cu), molybdenum (Mo), molybdenum tungsten alloy (MoW), gallium nitride (GaN), zinc oxide (ZnO), or copper tungsten (CuW).

[0062] In this invention, the first electrode 50 and the second electrode 60 of the semiconductor element in any embodiment are used to connect to an external power source and conduct a current between them. The materials of the first electrode 50 and the second electrode 60 include transparent conductive materials or metallic materials. Transparent conductive materials include transparent conductive oxides, including indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (Zn2SnO4, ZTO), gallium-doped zinc oxide (GZO), tungsten-doped indium oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO). Metallic materials include gold (Au), platinum (Pt), germanium gold nickel (GeAuNi), titanium (Ti), beryllium gold (BeAu), germanium gold (GeAu), aluminum (Al), zinc gold (ZnAu), or nickel (Ni).

[0063] In one embodiment, the first electrode 50 and the second electrode 60 are located on opposite sides of the substrate 10. In this embodiment, the substrate 10 comprises a conductive material.

[0064] Methods for performing epitaxial growth include, but are not limited to, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxial growth (HVPE), or liquid-phase epitaxy (LPE). Preferably, the method for performing epitaxial growth includes MOCVD.

[0065] If any embodiment of the semiconductor element includes a light-emitting element, the peak wavelength of the light emitted by the light-emitting element is located in the visible light or invisible light range, and preferably in the blue light or ultraviolet light range. Preferably, the peak wavelength is located between 250 nm and 570 nm (inclusive), and more preferably, between 350 nm and 480 nm (inclusive).

[0066] In another embodiment of the invention, the elements or structures in the foregoing embodiments may be modified or combined with each other. For example, Figure 3 The semiconductor element 3 shown includes, for example, Figure 5 The aluminum-containing layer 80 is shown.

[0067] It should be noted that the embodiments listed in this invention are only illustrative and not intended to limit the scope of the invention. Any obvious modifications or alterations made to this invention do not depart from its spirit and scope. Components that are the same or similar in different embodiments, or components with the same reference numerals in different embodiments, have the same physical or chemical properties. Furthermore, the embodiments described above can be combined or substituted with each other where appropriate, and are not limited to the specific embodiments described. The connection relationships between specific components and other components described in detail in one embodiment can also be applied to other embodiments, and all fall within the scope of protection of the claims of this invention as stated above.

Claims

1. A semiconductor element, characterized in that, Include: First semiconductor region; The second semiconductor region is located on the first semiconductor region; The active region located between the first semiconductor region and the second semiconductor region; The first electrode is located on the first semiconductor region; The first semiconductor region comprises a first layer and a second layer located between the first layer and the active region. The first layer contains a first dopant having a first concentration, and the second layer contains a second dopant having a second concentration, wherein the second concentration of the second dopant in the second layer is between 5 × 10⁻⁶. 18 / cm 3 and 5×10 19 / cm 3 Between and including end values; and A spacer layer is located between the second layer and the active region. This spacer layer contains a third dopant with a third concentration, wherein the third concentration of the third dopant in the spacer layer is less than the second concentration of the second dopant in the second layer, the ratio of the second concentration of the second dopant in the second layer to the third concentration of the third dopant in the spacer layer is greater than the ratio of the first concentration of the first dopant in the first layer to the second concentration of the second dopant in the second layer, and the ratio of the second concentration of the second dopant in the second layer to the third concentration of the third dopant in the spacer layer is not less than 10. The second layer includes a first part and a second part. The first part overlaps with the active region in the stacking direction, and the second part is adjacent to the first part. The first electrode is located on the second part of the second layer.

2. The semiconductor device of claim 1, wherein the spacer layer comprises a first intermediate layer and a second intermediate layer located on the first intermediate layer, wherein the first intermediate layer comprises a dopant having a concentration, the second intermediate layer comprises a dopant having a concentration, and the concentration of the dopant in the first intermediate layer is greater than the concentration of the dopant in the second intermediate layer.

3. The semiconductor device of claim 1, wherein the ratio of the second concentration of the second dopant in the second layer to the third concentration of the third dopant in the spacer layer is at least three times the ratio of the first concentration of the first dopant in the first layer to the second concentration of the second dopant in the second layer.

4. The semiconductor device of claim 3, wherein the ratio of the second concentration of the second dopant in the second layer to the third concentration of the third dopant in the spacer layer is a value between 5 and 50 times, including the end value, of the ratio of the first concentration of the first dopant in the first layer to the second concentration of the second dopant in the second layer.

5. The semiconductor device of claim 1, wherein the third concentration of the third dopant in the spacer layer is between 1 × 10⁻⁶. 17 / cm 3 and 5×10 18 / cm 3 Between and including end values.

6. The semiconductor device of claim 1, wherein the ratio of the second concentration of the second dopant in the second layer to the third concentration of the third dopant in the spacer layer is not greater than 50.

7. The semiconductor device of claim 1, wherein the spacer layer includes an energy level, the first layer includes an energy level, and the energy level of the spacer layer is lower than the energy level of the first layer.

8. A semiconductor element, characterized in that, Include: First semiconductor region; The second semiconductor region is located on the first semiconductor region; The active region located between the first semiconductor region and the second semiconductor region; The first electrode is located on the first semiconductor region; The first semiconductor region includes a first layer and a second layer located between the first layer and the active region. The first layer includes a first dopant having a first concentration, and the second layer includes a second dopant having a second concentration. A spacer layer is located between the second layer and the active region, wherein the spacer layer includes a first intermediate layer and a second intermediate layer located on the first intermediate layer, wherein the first intermediate layer contains a dopant of a certain concentration, the second intermediate layer contains a dopant of a certain concentration, and the concentration of the dopant in the first intermediate layer is greater than the concentration of the dopant in the second intermediate layer. The second layer includes a first part and a second part. The first part overlaps with the active region in the stacking direction, and the second part is adjacent to the first part. The first electrode is located on the second part of the second layer.

9. The semiconductor device of claim 2 or 8, wherein the concentration of the dopant in the first intermediate layer is between 5 × 10⁻⁶. 17 / cm 3 and 5×10 18 / cm 3 Between and including end values.

10. The semiconductor device of claim 9, wherein the concentration of the dopant in the second intermediate layer is between 1 × 10⁻⁶. 17 / cm 3 and 1×10 18 / cm 3 Between and including end values.

11. The semiconductor device of claim 2 or 8, wherein the first concentration of the first dopant in the first layer is greater than the concentration of the dopant in the first intermediate layer.

12. The semiconductor device of claim 2 or 8, wherein the material of the first intermediate layer is the same as the material of the second intermediate layer.

13. The semiconductor device of claim 2 or 8, wherein the spacer layer further comprises a plurality of the first intermediate layers and a plurality of the second intermediate layers, the first intermediate layers and the second intermediate layers being alternately disposed.

14. The semiconductor device of claim 1 or 8, wherein the first concentration of the first dopant in the first layer is between 1 × 10⁻⁶. 18 / cm 3 Up to 1×10 20 / cm 3 The values ​​between them include end values.

15. The semiconductor device of claim 1 or 8, wherein the ratio of the first concentration of the first dopant in the first layer to the second concentration of the second dopant in the second layer is not greater than 10.

16. The semiconductor device of claim 15, wherein the ratio of the first concentration of the first dopant in the first layer to the second concentration of the second dopant in the second layer is not less than 1.

1.

17. The semiconductor device of claim 1 or 8, further comprising an aluminum-containing layer located beneath the first semiconductor region, the aluminum-containing layer comprising an energy level, the first layer comprising an energy level, the energy level of the aluminum-containing layer being greater than the energy level of the first layer.

18. The semiconductor device according to claim 17, wherein the aluminum-containing layer contains Al d Ga 1-d N, and the first layer contains Al a Ga 1-a N, where 0 < a ≤ 0.1 and / or 0 < d ≤ 0.

3.

19. The semiconductor device of claim 18, wherein a <d。 20. The semiconductor device of claim 1 or 8, wherein the first layer includes an energy level, the second layer includes an energy level, and the energy level of the first layer is greater than the energy level of the second layer.

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