All-digital phase-locked loop and its correction method

Abstract

The present disclosure relates to an all-digital phase-locked loop and a correction method thereof. The present invention provides an all-digital phase-locked loop and a correction method thereof, wherein the all-digital phase-locked loop can include a digitally controlled oscillator, a time-to-digital converter coupled to the digitally controlled oscillator, and a normalization circuit coupled to the time-to-digital converter. The digitally controlled oscillator can be used to generate a clock signal according to a frequency control signal, the time-to-digital converter can be used to generate a digital output signal according to a phase difference between the clock signal and a reference signal, and the normalization circuit can be used to convert the digital output signal into a clock phase value according to a gain parameter. In particular, the normalization circuit can adjust the gain parameter according to a phase difference value between the clock phase value and a reference phase value.

Description

Technical Field

[0001] This invention relates to an all-digital phase-locked loop, and more particularly to an all-digital phase-locked loop and its correction method, such as a gain correction method for a time-to-digital converter within the all-digital phase-locked loop. Background Technology

[0002] In the operation of an all-digital phase-locked loop (PLL), a time-to-digital converter (TD-to-RTD) acts as a phase detector, converting the phase difference between a reference signal and the output signal of a digitally controlled oscillator into digital code, enabling subsequent processing in the digital domain. However, the TD-to-RTD retains some characteristics of analog circuits; for example, its resolution may vary due to factors such as process-voltage-temperature (PVT) variations. Since the TD-to-RTD resolution affects the setpoints of certain parameters in the all-digital PLL, estimation errors in the TD-to-RTD resolution can impact the overall performance of the all-digital PLL.

[0003] Therefore, a novel architecture and related correction method are needed so that parameters related to the time-to-digital converter (e.g., the gain of the time-to-digital converter) can converge properly to the correct or optimal values ​​under various manufacturing variations and temperatures. Summary of the Invention

[0004] One objective of this invention is to provide an all-digital phase-locked loop (ADPLL) and its correction method to converge parameters related to the time-to-digital converter (e.g., the gain of the time-to-digital converter) to the correct or optimal values ​​with little or no side effects.

[0005] At least one embodiment of the present invention provides an all-digital phase-locked loop (PLL), wherein the PLL may include a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The DCO can be used to generate a clock signal according to a frequency control signal, the TDC can be used to generate a digital output signal according to the phase difference between the clock signal and a reference signal, and the normalization circuit can be used to convert the digital output signal into a clock phase value according to a gain parameter. In particular, the normalization circuit can adjust the gain parameter according to a phase difference value between the clock phase value and a reference phase value.

[0006] At least one embodiment of the present invention provides a correction method for an all-digital phase-locked loop (PLL), wherein the correction method may include: generating a clock signal using a digitally controlled oscillator in the PLL according to a frequency control signal; generating a digital output signal using a time-to-digital converter in the PLL according to a phase difference between the clock signal and a reference signal; converting the digital output signal into a clock phase value using a normalization circuit in the PLL according to a gain parameter; and adjusting the gain parameter using the normalization circuit according to a phase difference value between the clock phase value and a reference phase value.

[0007] The fully digital phase-locked loop and its correction method provided in the embodiments of the present invention can determine the directionality of the gain parameter error based on the phase difference value and the signal output by the time-to-digital converter, and establish a feedback correction mechanism so that the gain parameter K TDC It can gradually converge to the correct value. Furthermore, the correction method of this invention is not limited by the resolution of the time-to-digital converter, nor does it significantly increase additional costs. Therefore, this invention solves the problems of related technologies without or with minimal side effects. Attached Figure Description

[0008] Figure 1 This is a schematic diagram illustrating the estimation of the resolution of a time-to-digital converter according to an embodiment of the present invention.

[0009] Figure 2 The circuit architecture of a time-to-digital converter according to one embodiment of the present invention.

[0010] Figure 3 for Figure 2 The circuit architecture shown involves certain signals.

[0011] Figure 4 This is for the normalized operation of a time-to-digital converter according to an embodiment of the present invention.

[0012] Figure 5 This is a simplified schematic diagram of a fully digital phase-locked loop according to one embodiment of the present invention.

[0013] Figure 6 This refers to certain signals under ideal conditions after locking, according to an embodiment of the present invention.

[0014] Figure 7 This refers to certain signals when the time-to-digital converter gain has a -20% error, according to an embodiment of the present invention.

[0015] Figure 8 This refers to certain signals when the time-to-digital converter gain has a +20% error, according to an embodiment of the present invention.

[0016] Figure 9 According to an embodiment of the present invention Figure 5 An example of a minimum mean square circuit is shown.

[0017] Figure 10 This describes the workflow of a calibration method for a fully digital phase-locked loop according to one embodiment of the present invention. Detailed Implementation

[0018] In the operation of an all-digital phase-locked loop (ADPLL), assuming the period of the clock signal CKV output by the digitally controlled oscillator (DCO) is T... V Furthermore, the time-to-digital converter (TDC) relies on the phase difference between the clock signal CKV and the reference signal FREF (e.g., the time difference Δt between the rising edge of the clock signal CKV and the rising edge of the reference signal FREF). r Generate a digital output signal N r This fully digital phase-locked loop requires the digital output signal N to be processed. r Normalization is performed to convert the digital output signal N r Convert to a number between 0 and 1 (For example, the phase difference between the clock signal CKV and the reference signal FREF can be expressed as...) times T V This is to facilitate subsequent operations. However, the results of the above normalization will be affected by the resolution Δt of the time-to-digital converter. res(For example, the time difference corresponding to the least significant bit of the digital output signal of the time-to-digital converter, or the unit delay of the time-to-digital converter) has an impact, among which The resolution Δt of the time-to-digital converter res The process voltage-temperature (PVT) of semiconductors will vary, so the above-mentioned normalization operation also needs to be corrected according to the change in resolution.

[0019] Figure 1 To estimate the resolution Δt of a time-to-digital converter according to an embodiment of the present invention res A schematic diagram. (See example.) Figure 1 As shown, this time-to-digital converter can detect the time difference Δt between the rising edge of the clock signal CKV and the reference signal FREF. r Furthermore, it detects the time difference Δt between the falling edge of the clock signal CKV and the reference signal FREF. f .like Figure 1 As shown, Δt r With Δt f The difference between them is half a cycle T of the clock signal CKV. V / 2, and the time-to-digital converter (or its subsequent processing circuitry) can utilize the time-to-digital converter based on Δt r With Δt f The resolution Δt of the time-to-digital converter can be roughly calculated from the respective digital output signals. res .

[0020] Figure 2 The circuit architecture of a time-to-digital converter 20 according to one embodiment of the present invention is as follows: Figure 3 for Figure 2 The circuit architecture shown involves certain signals. It should be noted that... Figure 2 The circuit architecture shown is merely an example of the time-to-digital converter 20 and is not intended to limit the invention. Figure 2 As shown, the time-to-digital converter 20 may include multiple inverters connected in series to form an inverter chain. Since each of these inverters introduces a signal delay, the respective output signals D of these inverters will vary. <0> D <1> D <2> ... D <l-1>and D <l>Each of the clock signals CKV input to the first inverter has its own corresponding delay time, such as... Figure 3 D in <0> D <1> D <2> D <3> D <4> D <5> D <6> and D <7> As shown, the delay introduced by one of the inverters is the resolution Δt of the time-to-digital converter 20. res In this embodiment, the output signal D <0> D <1> D <2> ... D <l-1>and D <l>All inputs are fed to the input terminal (labeled "D") of the flip-flop, and output from the output terminal (labeled "Q") of the flip-flop when triggered by the rising edge of the reference signal FREF. Figure 3 As shown in Q<0:L>. In this embodiment, the output signal Q<0:L> changes from 0 to 1 (e.g., Q... <1> Q is 0 <2> The part that is 1) represents the falling edge of the clock signal CKV, and the output signal Q<0:L> changes from 1 to 0 (e.g., Q). <5> For 1 and Q <6> The portion that is 0 represents the rising edge of the clock signal CKV. Next, the time-to-digital converter 20 can use its internal pseudo-thermometer-code edge detector 22 (e.g., a detector used to detect transitions from 0 to 1 and from 1 to 0 in a digital sequence) to detect the output signal Q<0:L> and output a binary digital output signal N accordingly. r and N f Let Δt represent the time difference between the rising edge of the clock signal CKV and the reference signal FREF, respectively. r and the time difference Δt between the falling edge of the clock signal CKV and the reference signal FREF f (e.g., Δt) r ≈N r ×Δt res And Δt f ≈N f ×Δt res ), for example N r =6 and N f =2. It should be noted that... Figure 2 The circuit architecture of the time-to-digital converter 20 shown is for illustrative purposes only and is not intended to limit the invention. For example, the number of bits in the output signal of the time-to-digital converter 20 can be varied according to system requirements, and L can be any positive integer.

[0021] Figure 4 This is for the normalized operation of a time-to-digital converter 20 according to an embodiment of the present invention. For example... Figure 4 As shown, the time-to-digital converter 20 can convert the digital output signal N obtained from the above operation into digital output signal N. r and N f The data is transmitted to a normalization circuit 30. First, the normalization circuit 30 can utilize a first calculation unit 31 (labeled "periodic averaging" for ease of understanding) to perform... Figure 1 The calculation shown is to obtain the average value of the period of the clock signal CKV. and the resolution Δt of the time-to-digital converter 20 res Then, the second calculation unit 32 (labeled as) is used (For ease of understanding) / Δt res The reciprocal is output in 12-bit binary form (e.g., signal PERINV), and then multiplier 33 is used to output the digital signal N. r Multiply by the signal PERINV to generate W F Bit (e.g., W) F The result of multiplying (=15) is then processed by the third calculation unit 34 (labeled as "2^W"). F –(x)」) Convert the multiplication result into unsigned 2's complement form and output it as signal ε, where W F A binary signal ε can be represented using discrete data (e.g., the k-th data point) as follows:

[0022]

[0023] It should be noted that when the duty cycle of the pulse signal CKV is not 50%, the average value of the pulse signal CKV period obtained above is used. and the resolution Δt of the time-to-digital converter 20 res The operation would require relatively complex hardware to implement. Furthermore, the above estimation method is also limited by the resolution Δt of the time-to-digital converter 20. res Therefore, estimation errors can lead to a decrease in the performance of the all-digital phase-locked loop (e.g., excessive output jitter / spurt).

[0024] For the sake of simplicity, all the following explanations will be in decimal form. Figure 5 This is a simplified schematic diagram of an all-digital phase-locked loop 50 according to one embodiment of the present invention. The all-digital phase-locked loop 50 may include a time-to-digital converter 500, a digitally controlled oscillator 510 (illustrated as a circle containing a sine wave for ease of understanding), a normalization circuit 520, an accumulator 530 (labeled "Σ" for ease of understanding), a low-pass filter (LPF) 540 (illustrated as a square with a low-pass response waveform for ease of understanding), and an adder 550 (illustrated as a circle containing a plus sign for ease of understanding). In this embodiment, the parameter FCW_F can be set as the ratio between the target frequency of the clock signal CKV and the frequency of the reference signal FREF, and the accumulator 530 continuously accumulates the parameter FCW_F, outputting the accumulated result as a reference phase. The time-to-digital converter can be coupled to the digitally controlled oscillator and used to generate a digital output signal N based on the phase difference between the clock signal CKV and the reference signal FREF. r [k](e.g., N) r The value of the reference signal FREF in the k-th cycle. A normalization circuit can be coupled to this time-to-digital converter and can be used based on a gain parameter K. TDC Convert the digital output signal into a clock phase value (For example The value of the clock phase value in the k-th cycle of the reference signal FREF. It can be regarded as a digital output signal N r [k] is the result after normalization. Adder 550 can subtract the above reference phase from a real-time phase (e.g., the sum of the real-time ratio between the real-time frequency of clock signal CKV and the frequency of reference signal FREF) to obtain a phase difference value. (For example The value of the reference signal FREF in the kth cycle is used to generate a frequency control signal for the low-pass filter 540 to control the digitally controlled oscillator 510 to generate a clock signal CKV based on the frequency control signal, so that the real-time frequency of the clock signal CKV gradually converges to the target frequency.

[0025] It should be noted that the digital output signal N generated by the time-to-digital converter 500 r [k] and its normalized clock phase value This is only used to represent the fractional part of the real-time phase, while the integer part of the real-time phase can be implemented using a counter. Since the operation of using a counter to generate the integer part of the real-time phase is a well-known technique in the art and does not affect the implementation of the correction of the time-to-digital converter 500 and the normalization circuit 520 in this invention, for the sake of simplicity, the counter is not shown in the diagram, and related details are not described here. Similarly, Figure 5 The reference phase value output by the accumulator 530 shown (For example The value of the reference signal FREF in the kth cycle is also used only to represent the fractional part of the aforementioned reference phase for the sake of simplicity.

[0026] exist Figure 5 In the illustrated embodiment, the normalization circuit 520 may include a multiplier 521 for converting the digital output signal N... r [k] multiplied by the gain parameter K TDC To generate clock phase value And the gain parameter K TDC The correct value can be calculated using the following formula:

[0027]

[0028] Where t res This can represent the resolution of the time-to-digital converter 500 (e.g., the aforementioned Δt). res ), and T DCO This can represent the period of the clock signal CKV output by the digitally controlled oscillator 510 (e.g., the T mentioned above). V or Due to the resolution t of the time-to-digital converter 500 res It is quite sensitive to PVT variation (e.g., at 25°C t) res The time is 13 picoseconds (ps), but at a temperature of 25°C, t res (10 ps), therefore the gain parameter K varies between different temperatures. TDC There will be a gain error, and the gain parameter K TDC Gain errors can cause unwanted frequency components, such as fractional purs, to appear.

[0029] For example, assuming the reference signal FREF has a frequency of 40MHz, the ratio between the target frequency of the clock signal CKV and the frequency of the reference signal FREF (FCW) is 125.25, and the expected resolution t... res The target frequency f of the clock signal CKV is 10 ps. DCO If it is 5010MHz, then K TDC It is approximately 0.05.

[0030] Figures 6 to 8 Clock phase based on the frequencies of clock signal CKV and reference signal FREF Reference phase and phase difference Values ​​under different circumstances. For example... Figure 6 As shown, in each cycle of the reference signal FREF, the digital output signal N... r The reference phases are 5, 10, 15, and 0 in sequence. The values ​​are 0.25, 0.5, 0.75, and 0 in that order. (Regarding the gain parameter K...) TDC In the absence of gain error (e.g., the true resolution t) res The corresponding gain parameter (i.e., t) res / T DCO ) and for the gain parameter K TDC (The preset value is 0.05), clock phase The values ​​are 0.25, 0.5, 0.75, and 0 in sequence, therefore the phase difference is... All remain at 0. When the gain parameter K is preset. TDC With an error of -20% (e.g., 0.04), this will cause clock phase... The phase difference is 0.2, 0.4, 0.6 and 0 in sequence. Even in the locked state, there is still a positive phase difference (e.g., 0.05, 0.1, 0.15, and 0), such as... Figure 7 As shown. When the gain parameter K is preset. TDC With an error of +20% (e.g., 0.06), this will cause clock phase... The phase difference is 0.3, 0.6, 0.8 and 0 in sequence. Even in the locked state, there is still a negative phase difference (e.g., -0.05, -0.1, -0.15, and 0), such as Figure 8 As shown.

[0031] From the examples above, we can see that the gain parameter K... TDC With digital output signal N r [k] and phase difference It has a correlation. For example, the larger the value of N, the more correlated it is. r [k] will result in a larger phase difference. For example, the gain parameter K TDC A positive gain error will result in a negative phase difference. And the gain parameter K TDC A negative gain error will result in a positive phase difference.

[0032] Therefore, embodiments of the present invention provide a correction method and a corresponding architecture to convert the digital output signal N r [k] and / or phase difference Used to correct the gain parameter K TDC .

[0033] like Figure 5 As shown, in addition to multiplier 521, normalization circuit 520 may further include multiplier 522 and a least mean square (LMS) circuit 523 (denoted as "LMS" for simplicity), wherein the least mean square circuit 523 is coupled between multipliers 521 and 522. In this embodiment, normalization circuit 520 can be based on clock phase value With reference phase value Phase difference value between Adjust the gain parameter K TDC Specifically, when the phase difference value Positive (e.g.) Figure 7 As shown), K represents the gain parameter. TDC There is a negative error (e.g., gain parameter K). TDC Less than t res / T DCO Therefore, the normalization circuit 520 can improve the gain parameter K. TDC ; and when the phase difference value Negative (e.g.) Figure 8 As shown), K represents the gain parameter. TDC There is a positive error (e.g., gain parameter K). TDC Greater than t res / T DCO The normalization circuit 520 can reduce the gain parameter K. TDC .

[0034] In this embodiment, the normalization circuit 520 can be based on the phase difference value. and digital output signal N r Adjust the gain parameter K TDC For example, the normalization circuit 520 can be based on the phase difference value. With digital output signal N r product Adjust the gain parameter K TDC .like Figure 5 As shown, the normalization circuit 520 can use a multiplier to calculate the phase difference value. With digital output signal N r product For the basis of the minimum mean square circuit 523 The calculation results are used to adjust the gain parameter K. TDC .

[0035] Figure 9 According to an embodiment of the present invention Figure 5 The example shown is of the minimum mean square circuit 523. Figure 9 As shown, the least mean square circuit 523 may include a multiplier 524 and an accumulator 525 (denoted as "Σ" for ease of understanding). In this embodiment, the least mean square circuit 523 can be used to calculate the phase difference value. With digital output signal N r product And the current gain parameter K used in the current cycle (e.g., the (k-1)th cycle of the reference signal FREF). TDC [k-1] Generates the next gain parameter K for the next cycle (e.g., the kth cycle of the reference signal FREF). TDC [k]. For example, the multiplier 522 can multiply 19-bit... With 6-bit digital output signal N r [k] multiply to produce a 25-bit product. Multiplier 524 can multiply the above product The result is further multiplied by a predetermined value μ, and the accumulator 525 can add the result of the multiplication to the gain parameter K. TDC [k-1] is used to obtain the 16-bit gain parameter K. TDC [k], where the predetermined value μ can be any suitable constant, and the related operations can be represented in discrete data as follows:

[0036]

[0037] It should be noted that the above calculation method and Figure 9 The architecture shown is only a minimum mean square circuit 523 with gain parameter K. TDC This is one example of an adjustment, and not a limitation thereof. Anything that can be adjusted based on the phase difference value... and / or digital output signal N r [k] will change the gain parameter K TDC Gradually adjust / converge to t res / T DCO All implementation methods described herein fall within the scope of this invention.

[0038] Figure 10 The present invention describes the workflow of a calibration method for a fully digital phase-locked loop according to one embodiment of the present invention, wherein the calibration method can be applied to... Figure 5 The fully digital phase-locked loop 50 is shown. It should be noted that one or more steps can be performed separately, provided it does not affect the overall result. Figure 10 The process shown may be added, modified, or deleted, and these steps do not necessarily have to be followed exactly. Figure 10 Execute in the order shown.

[0039] In step 1010, the all-digital phase-locked loop 50 uses a digitally controlled oscillator 510 to generate a clock signal CKV based on a frequency control signal.

[0040] In step 1020, the all-digital phase-locked loop 50 uses the time-to-digital converter 500 to generate a digital output signal N based on the phase difference between the clock signal CKV and the reference signal FREF. r [k].

[0041] In step 1030, the all-digital phase-locked loop 50 utilizes the normalization circuit 520 based on the gain parameter K. TDC Digital output signal N r [k] is converted to clock phase value.

[0042] In step 1040, the all-digital phase-locked loop 50 utilizes the normalization circuit 520 based on the clock phase value With reference phase value The phase difference value between Adjust the gain parameter K TDC .

[0043] In summary, embodiments of the present invention provide a fully digital phase-locked loop and its correction method, which can correct based on phase difference values. and the signal N output by the time-to-digital converter r Determine the gain parameter K TDC The directionality of the error is determined, and a feedback correction mechanism is established to ensure that the gain parameter K... TDC It can gradually converge to the correct value. Furthermore, the correction mechanism proposed in this invention is not limited by the resolution of the time-to-digital converter; in particular, the accuracy during correction can be determined by the bit design of the computational units within the normalization circuit 520 (e.g., multipliers 521 and 522, and the least mean square circuit 523). Therefore, this invention can, without or with minimal side effects, reduce the accuracy of time-to-digital converter-related parameters (e.g., the gain K of the time-to-digital converter). TDC It converges to the correct or optimal value.

[0044] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0045] [Symbol Explanation]

[0046] CKV: Clock Signal

[0047] FREF: Reference signal

[0048] Δt r ,Δt f Time difference

[0049] T V :cycle

[0050] 20: Time-to-Digital Converter

[0051] D <0> D <1> D <2> D <3> D <4> D <5> D <6> D <7> ~D <l-1> ,D <l>Output signal

[0052] Q <0> Q <1> Q <2> ~Q <l-1> ,Q <l>Output signal

[0053] N r N f Digital output signal

[0054] 30: Regularized circuit

[0055] 31: First Calculation Unit

[0056] 32: Second Calculation Unit

[0057] 33: Multiplier

[0058] 34: Third Calculation Unit

[0059] PERINV,ε: Signal

[0060] 50: Fully digital phase-locked loop

[0061] 500: Time-to-Digital Converter

[0062] 510: Digitally Controlled Oscillator

[0063] 520: Normalized Circuit

[0064] 521, 522: Multiplier

[0065] 523: Minimum Mean Square Circuit

[0066] 524: Multiplier

[0067] 525: Accumulator

[0068] 530: Accumulator

[0069] 540: Low-pass filter

[0070] 550: Adder

[0071] FCW_F: Parameters

[0072] Clock phase value

[0073] Reference phase value

[0074] Phase difference value

[0075] N r [k]: Digital output signal

[0076] K TDC Gain parameters

[0077] 1010, 1020, 1030, 1040: Steps< / l> < / l-1> < / l> < / l-1> < / l> < / l>

Claims

1. A fully digital phase-locked loop, comprising: A digitally controlled oscillator is used to generate a clock signal based on a frequency control signal; A time-to-digital converter, coupled to the digitally controlled oscillator, is used to generate a digital output signal based on the phase difference between the clock signal and a reference signal; and A normalization circuit, coupled to the time-to-digital converter, is used to convert the digital output signal into a clock phase value according to a gain parameter; The normalization circuit adjusts the gain parameter based on a phase difference between the clock phase value and a reference phase value. The normalization circuit multiplies the phase difference value with the digital output signal to generate a product, and the adjustment amount of the gain parameter is proportional to the product.

2. The all-digital phase-locked loop according to claim 1, wherein the normalization circuit multiplies the digital output signal by the gain parameter to generate the clock phase value.

3. The all-digital phase-locked loop according to claim 1, wherein when the phase difference value is positive, the normalization circuit increases the gain parameter; and when the phase difference value is negative, the normalization circuit decreases the gain parameter.

4. The all-digital phase-locked loop according to claim 1, wherein the normalization circuit includes a least-mean-square (LMS) circuit for generating a next gain parameter for the next cycle based on the product of the phase difference value and the digital output signal and the current gain parameter used in the current cycle.

5. A calibration method for a fully digital phase-locked loop, comprising: A clock signal is generated by a digitally controlled oscillator in the all-digital phase-locked loop based on a frequency control signal; A time-to-digital converter in the all-digital phase-locked loop generates a digital output signal based on the phase difference between the clock signal and a reference signal; The digital output signal is converted into a clock phase value using a normalization circuit in the all-digital phase-locked loop based on a gain parameter; and The normalization circuit adjusts the gain parameter based on a phase difference between the clock phase value and a reference phase value, wherein the normalization circuit multiplies the phase difference value with the digital output signal to produce a product, and the adjustment amount of the gain parameter is proportional to the product.

6. The correction method according to claim 5, wherein the step of converting the digital output signal into the clock phase value using the normalization circuit in the all-digital phase-locked loop according to the gain parameter comprises: The normalization circuit is used to multiply the digital output signal by the gain parameter to generate the clock phase value.

7. The correction method according to claim 5, wherein the step of adjusting the gain parameter using the normalization circuit based on the phase difference value between the clock phase value and the reference phase value includes: When the phase difference is positive, the gain parameter is increased using the normalization circuit.

8. The correction method according to claim 5, wherein the step of adjusting the gain parameter using the normalization circuit based on the phase difference value between the clock phase value and the reference phase value includes: When the phase difference value is negative, the gain parameter is reduced using the normalization circuit.

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