A Processor Operation Error Detection Method and System Based on Core Control Flow Information

Abstract

This invention proposes a processor runtime error detection method and system based on main core control flow information. The method includes: saving the control flow information of program segments in the form of a control flow table during the main core's operation; and using this control flow information to guide branch prediction during the check core's operation to improve the check core's efficiency. For each program segment, the main core and check core should have the same control flow. Therefore, using the main core's control flow information to guide the check core's branch prediction achieves 100% branch prediction accuracy, eliminates the overhead of branch prediction failures, and thus improves the check core's performance.

Description

Technical Field

[0001] This invention belongs to the field of microprocessor reliability design. It uses the control flow information of the main core to guide the branch prediction of the check core, thereby improving the performance of the check core and reducing the error detection latency. Background Technology

[0002] Since the revolution in automotive semiconductors and in-vehicle information technology, the number of electronic control units (ECUs) in each car has increased, leading to higher and higher requirements for the reliability of automotive electronics. However, automotive chips face harsh and complex operating environments such as high temperature and high humidity, causing on-vehicle processors to generate errors more frequently compared to general electronic systems, thus posing a severe test to the reliability of automotive chips. Dual-core lockstep, which runs the same program on two processor cores and compares the outputs of the two cores for error detection, incurs significantly higher area and power consumption overhead. However, its high error detection speed and error coverage can meet the reliability requirements of automotive chips. Compared to the homogeneous design of dual-core lockstep, heterogeneous parallel error detection uses a series of low-performance check cores to repeatedly run program segments of the high-performance main core in parallel for error detection. To improve performance, the chip area and power consumption increase superlinearly. The sum of the area and power consumption of these low-performance cores is smaller than that of the high-performance core, enabling error coverage similar to that of dual-core lockstep with lower power consumption and area overhead.

[0003] Error detection during main core runtime is achieved by using multiple low-power sequential cores (checker cores) to run program segments of a high-performance out-of-order core (main core) in parallel. This method divides the program running on the main core into multiple program segments, assigning each segment to a different checker core for repeated execution. Each checker core is a small core, with performance lower than the main core, but because multiple checker cores can run in parallel, their overall performance can match that of the main core. In sequential processors, simple branch predictors are typically used, usually including a branch target buffer (BTB), a pattern history table (PHT), and a return address stack (RAS). The branch predictor needs to predict the branch target based on the branch results of previous branch instructions. Since the program segments assigned to each checker core are not consecutive, this reduces the accuracy of branch prediction, and a high error rate in branch prediction degrades the performance of the checker core. Summary of the Invention

[0004] Since the checker kernel only starts running after the main kernel has finished executing the program segment, the control flow information of the program segment can be known before the checker kernel runs the program segment. Therefore, the control flow information of the main kernel can be used to guide the branch prediction of the checker kernel, speed up error detection, and improve the performance of the checker kernel.

[0005] Specifically, this invention addresses the problem of low branch prediction accuracy in heterogeneous parallel error detection, which reduces check kernel performance. It proposes a processor-based error detection method based on main core control flow information, comprising:

[0006] Step 1: Obtain a processing system with a main core and a check core, wherein the main core and the check core have the same instruction set architecture;

[0007] Step 2: Extract the load memory log and control flow generated by the main core running program segment. The load memory log includes the load address and load data corresponding to the load instruction, and the control flow table includes the target address and program counter value corresponding to the control flow instruction.

[0008] Step 3: When the program segment starts running, the state of the main core is copied to the check core, so that the check core starts running in the same state as the main core. During the execution of the program segment by the check core, for load instructions, the check core directly accesses the load memory log to obtain the load data as the load result, and determines whether the address of the load result is the same as the load address in the load memory log. If they are different, it indicates that an error has occurred. For branch prediction, the check core directly accesses the control flow table to obtain the target address of the current control flow instruction as the branch prediction result, and determines whether the branch prediction result is the same as the target address corresponding to the current control flow instruction in the control flow table. If they are different, it indicates that an error has occurred. When the check core finishes running the program segment, it determines whether the state of the check core when it finishes running the program segment is the same as the state of the main core when it finishes running the program segment. If they are different, it indicates that an error has occurred.

[0009] The processor execution error detection method based on main core control flow information, wherein the program segment generation process in step 3 includes: when the main core runs the program to be executed, whenever a load instruction is submitted, the load address and load data are saved to the load memory log corresponding to the current check core; when the load memory log is full, the current state of the main core is used as a checkpoint to divide the program segment; whenever a control flow instruction is submitted, the program counter value and target address of the control flow instruction are saved to the control flow table; when the control flow table is full, the current state of the main core is used as a checkpoint to divide the program segment.

[0010] The processor runtime error detection method based on main core control flow information, wherein step 3 includes:

[0011] Whenever the main core submits a control flow instruction, it adds its program counter and target address value to the control flow instruction target queue of the corresponding checker core. Each time the checker core fetches an instruction, it compares the program counter value of the item pointed to by the head pointer of the control flow instruction target queue with the program counter value of the fetch unit. If they are equal, the target address is given to the fetch unit as the branch prediction result, which is used as the address for the next instruction fetch. The pointer of the control flow instruction target queue is then moved forward.

[0012] This invention also proposes a processor operation error detection system based on main core control flow information, including:

[0013] The initial module is used to obtain a processing system with a main core and a check core, wherein the main core and the check core have the same instruction set architecture;

[0014] The control flow extraction module is used to extract the load memory log and control flow generated by the main core running program segment. The load memory log includes the load address and load data corresponding to the load instruction. The control flow table includes the target address and program counter value corresponding to the control flow instruction.

[0015] The detection module copies the state of the main core to the check core at the start of the program segment's execution, ensuring the check core starts running in the same state as the main core. During the check core's execution of the program segment, for load instructions, it directly accesses the load memory log to obtain the load data as the load result and checks if the address of the load result is the same as the load address in the load memory log; if they are different, an error has occurred. For branch prediction, the check core directly accesses the control flow table to obtain the target address of the current control flow instruction as the branch prediction result and checks if the branch prediction result is the same as the target address corresponding to the current control flow instruction in the control flow table; if they are different, an error has occurred. When the check core finishes running the program segment, it checks if its state at the time of termination is the same as the main core's state at the time of termination; if they are different, an error has occurred.

[0016] The processor operation error detection system based on main core control flow information includes a program segment generation process in the detection module as follows: when the main core runs the program to be executed, whenever a load instruction is submitted, the load address and load data are saved to the load memory log corresponding to the current check core. When the load memory log is full, the current state of the main core is used as a checkpoint to divide the program segment. Whenever a control flow instruction is submitted, the program counter value and target address of the control flow instruction are saved to the control flow table. When the control flow table is full, the current state of the main core is used as a checkpoint to divide the program segment.

[0017] The aforementioned processor operation error detection system based on main core control flow information, wherein the detection module is used for:

[0018] Whenever the main core submits a control flow instruction, it adds its program counter and target address to the control flow instruction target queue of the corresponding checker core. Each time the checker core fetches an instruction, it compares the program counter value of the item pointed to by the head pointer of the control flow instruction target queue with the program counter value of the fetch unit. If they are equal, the target address is given to the fetch unit as the branch prediction result, which is then used as the address for the next instruction fetch. The pointer of the control flow instruction target queue is then moved forward.

[0019] The present invention also proposes a storage medium for storing a program that executes any of the processor-based error detection methods based on the main core control flow information.

[0020] The present invention also proposes a data processing apparatus, including a storage medium, wherein when the processor of the data processing apparatus retrieves and executes computer-executable instructions in the computer-readable storage medium, the data processing apparatus performs heterogeneous parallel error detection sharing main core control flow information.

[0021] The present invention also proposes a client for running an error detection system based on any of the aforementioned processors with main core control flow information.

[0022] As can be seen from the above solutions, the advantages of the present invention are:

[0023] This invention proposes a method for using master core control flow information to guide checker core branch prediction, thereby accelerating the running performance of checker cores and reducing the number of checker cores required.

[0024] This invention sequentially stores the addresses of control flow instructions submitted by the main core and their target addresses in a control flow table. During the execution of the checking core, accessing the control flow table guides its branch prediction, resulting in 100% branch prediction accuracy. This eliminates the overhead of branch prediction failures, thereby improving the performance of the checking core and allowing for the use of fewer checking cores to match the throughput of the main core. Furthermore, by checking the predicted control flow instruction targets, the latency required for error detection is reduced. Attached Figure Description

[0025] Figure 1 This is a diagram of the error detection structure.

[0026] Figure 2 The kernel control flow information guides the inspection of the kernel branch prediction process diagram;

[0027] Figure 3 This is a flowchart of the heterogeneous parallel error detection method of the present invention;

[0028] Figure 4 This is a schematic diagram of the data processing device of the present invention. Detailed Implementation

[0029] In an out-of-order processor, each instruction can be executed out of order, but it is submitted according to a predetermined control flow order. Therefore, by simply saving the program counter (PC) (which represents the address of the instruction) and target of each branch and jump instruction according to the order in which the main core submits the instructions, the correct control flow information can be saved. For a program segment, the checker core only begins to check the program segment after the main core program segment has finished running. The control flow information of the program segment is known before the checker core begins its check. Therefore, this invention can save the control flow information of the program segment during the main core's execution, and use this control flow information to guide the checker core's branch prediction during the checker core's execution, thereby improving the checker core's running efficiency. For a given program segment, the main core and the checker core should have the same control flow. Therefore, using the main core's control flow information to guide the checker core's branch prediction has a 100% branch prediction accuracy, eliminating the overhead of branch prediction failures, thereby improving the checker core's performance.

[0030] To make the above features and effects of the present invention clearer and easier to understand, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings.

[0031] The overall structure of the proposed heterogeneous parallel error detection system is as follows: Figure 1 As shown, it mainly consists of a high-performance out-of-order main core, multiple low-performance sequential check cores, a load-forward unit, a load-store log, and a control flow table. The reorder buffer stores control information related to each instruction in sequence, including the instruction type, program counter (PC), jump destination address, and whether the instruction has been executed and written back.

[0032] The main core and the checker cores have the same instruction set architecture. The main core runs normal programs and divides them into multiple program segments, which are then passed to the checker cores for repeated execution and error detection. Each checker core has its own L0 instruction cache, as well as an L1 instruction cache shared with other checker cores. The L1 instruction cache is connected to the main core's L2 cache and retrieves the required instructions from the main core's L2 cache.

[0033] The load forwarding unit copies the data fetched by the main core's load instructions. When a load instruction is submitted, it compares it with the data in the load storage queue to prevent errors in the load instruction from being transmitted to the check core. Specifically, for a load instruction, normally, during execution, the instruction retrieves the corresponding data from the data cache and stores it in the load queue. This invention, however, simultaneously stores the data from the data cache in the load forwarding unit. When an instruction is submitted, the data for that instruction in the load queue is retrieved and compared with the data in the load forwarding unit. If the two sets of data match, the instruction is stored in the load storage log. This ensures the correctness of the data loaded in the load storage log. Therefore, the load forwarding unit first stores the data retrieved from the cache. When an instruction is submitted, it obtains the sequence number of the corresponding instruction, retrieves the stored data of the corresponding instruction based on the sequence number, and compares it with the data in the load queue, thus ensuring the correctness of the data loaded in the load storage log.

[0034] For load instructions, once issued, the load execution unit sends a read request to the data cache, which then returns the data at the corresponding address to the processor, storing it in the load-memory queue. For store instructions, once the data to be stored is ready, the store instruction is issued, and upon issuance, the required data is stored in the load-memory queue.

[0035] The load-store log is used to store the addresses and data corresponding to the load and store commands submitted by the main core. Each check core has its own independent partition, which can be accessed in parallel. During operation, the check core directly accesses the load-store log for load and store commands, and compares the data and addresses to achieve error detection.

[0036] The control flow table stores the address and target address of each control flow instruction submitted by the main core. Each checker core has its own independent partition to enable parallel access. During the execution of the checker core, the control flow information from the main core is used to guide the checker core's branch prediction. Control flow instructions include: jump instructions, branch instructions, call instructions, and return instructions.

[0037] The main core runs a normal program and divides it into multiple program segments, which are then repeatedly run by various check cores to perform error detection. Because the check cores have lower performance, multiple check cores run in parallel. Therefore, the throughput of the multiple check cores can match that of the main core. The process is as follows: Figure 2As shown, each program segment is assigned a checker. At the beginning of the program segment, the current state is copied to the checker so that the checker can start running with the same state. At the end of the program segment, the current state is also copied to the checker, which checks the state after the program segment finishes running, starts the current checker, and assigns a new checker to the new program segment.

[0038] When the main core is running, whenever a load or store instruction is submitted, the load / store address and data need to be saved to the load / store log partition corresponding to the current checker core. If the current load / store log partition is full, the current state is used as a checkpoint to divide the program segment. Whenever a control flow instruction is submitted, the program counter value and its target address of the instruction are saved to the control flow table. If the current control flow table partition is full, the current state is used as a checkpoint to divide the program segment. The size of the partition is manually set. Since each checker core has a separate partition, setting the partition too large will lead to excessive storage area overhead, so it needs to be determined based on the acceptable storage area overhead.

[0039] For each program segment, the checker core's operation is divided into three stages: 1) At the beginning of the program segment, the state of the main core's program counter, general-purpose registers, status registers, etc., is copied to the checker core, allowing the checker core to start running in the same state as the main core; 2) During the checker core's operation, for load instructions, it directly accesses the load memory log to obtain the required data and compares the addresses; differences indicate an error. For store instructions, it compares the data in the load memory log with the addresses; differences indicate an error. For branch prediction, the checker core directly accesses the control flow table to obtain the target addresses of each control flow instruction as the result of branch prediction, and verifies the branch prediction results during instruction execution; if a branch prediction fails, an error occurs; 3) When the program segment ends, the checker core's state is compared with the state of the copied program segment's end; differences indicate an error.

[0040] The program counter represents the address of the instruction currently being executed by the processor, allowing the processor to execute instructions one after another. Data registers primarily store operands and calculation results, saving time spent on bus and memory accesses when retrieving operands. Status registers store various status and control information related to instruction execution results. The processor's checkpoint state is composed of the contents of these registers.

[0041] During runtime, the main core performs branch prediction. It checks the program counter to determine if an instruction is a control flow instruction. If so, it predicts the target address of that instruction, and the next instruction fetch will be taken from that predicted address. The fetched instruction is placed in the reorder buffer. If branch prediction fails, the corresponding instruction is removed from the reorder buffer. Therefore, the main core always submits instructions in the correct order. Similarly, the check core also performs branch prediction during instruction fetching.

[0042] For the load instructions in the check kernel, they need to load the same data as the load instructions in the main kernel, so that the check kernel and the main kernel can run the same program segments. Therefore, retrieving data directly from the load memory log has less impact on the main kernel's performance compared to having the check kernel retrieve data from the cache. At the same time, this also speeds up the execution of program segments by the check kernel.

[0043] The following section uses examples to illustrate the process of using the master core control flow information to guide the check kernel in error detection.

[0044] The process of using master core control flow information to guide the inspection of kernel branch prediction is as follows: Figure 2 As shown, each entry in the control flow table consists of the program counter address (program counter value) of the control flow instruction and its target address. Whenever the main core submits a control flow instruction, its program counter and target address are added to the control flow instruction target queue of the corresponding checker core. For the checker core, its original branch prediction unit is deleted, and branch prediction is replaced by accessing the control flow table. Each time the checker core fetches an instruction, it compares the program counter value of the entry pointed to by the head pointer with the program counter value of the fetch unit. If they are equal, the target address is used as the result of the branch prediction and given to the fetch unit as the address for the next instruction fetch. The pointer of the control flow instruction target queue is then moved forward, and this process is repeated continuously. For each control flow instruction, whenever it is executed by the checker core, the calculated target address is compared with the predicted target address. If they are different, an error has occurred, thus achieving error detection for the control flow and reducing the latency of error detection.

[0045] When an error is detected, checkpointing can be used to restore the main core to the state of the previous checkpoint. Alternatively, the main core can be restarted to re-run the program. Interrupt handlers can also be used to handle errors.

[0046] Specifically, such as Figure 3 As shown, the heterogeneous parallel error detection method for sharing master core control flow information of the present invention specifically includes:

[0047] Step S1: Divide the program to be executed into multiple program segments, obtain the instructions to be executed for each program segment, and the control flow instructions that control the execution order of these instructions;

[0048] Step S2: The main core executes all program instructions in the order of control flow, obtains main core execution information, and generates control flow information;

[0049] Step S3: At the beginning of the program segment, the state of the main core program counter, general-purpose registers, status registers, etc., is copied to the check core, so that the check core can start running in the same state as the main core.

[0050] Step S4: The check kernel executes the program instructions of each program segment, obtains the check kernel execution information of each program segment, and compares it with the control flow information to perform error detection on the main kernel's running status in each program segment.

[0051] The following are system embodiments corresponding to the above method embodiments. This embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0052] This invention also proposes a processor operation error detection system based on main core control flow information, including:

[0053] The initial module is used to obtain a processing system with a main core and a check core, wherein the main core and the check core have the same instruction set architecture;

[0054] The control flow extraction module is used to extract the load memory log and control flow generated by the main core running program segment. The load memory log includes the load address and load data corresponding to the load instruction. The control flow table includes the target address and program counter value corresponding to the control flow instruction.

[0055] The detection module copies the state of the main core to the check core at the start of the program segment's execution, ensuring the check core starts running in the same state as the main core. During the check core's execution of the program segment, for load instructions, it directly accesses the load memory log to obtain the load data as the load result and checks if the address of the load result is the same as the load address in the load memory log; if they are different, an error has occurred. For branch prediction, the check core directly accesses the control flow table to obtain the target address of the current control flow instruction as the branch prediction result and checks if the branch prediction result is the same as the target address corresponding to the current control flow instruction in the control flow table; if they are different, an error has occurred. When the check core finishes running the program segment, it checks if its state at the time of termination is the same as the main core's state at the time of termination; if they are different, an error has occurred.

[0056] The processor operation error detection system based on main core control flow information includes a program segment generation process in the detection module as follows: when the main core runs the program to be executed, whenever a load instruction is submitted, the load address and load data are saved to the load memory log corresponding to the current check core. When the load memory log is full, the current state of the main core is used as a checkpoint to divide the program segment. Whenever a control flow instruction is submitted, the program counter value and target address of the control flow instruction are saved to the control flow table. When the control flow table is full, the current state of the main core is used as a checkpoint to divide the program segment.

[0057] The aforementioned processor operation error detection system based on main core control flow information, wherein the detection module is used for:

[0058] Whenever the main core submits a control flow instruction, it adds its program counter and target address value to the control flow instruction target queue of the corresponding checker core. Each time the checker core fetches an instruction, it compares the program counter value of the item pointed to by the head pointer of the control flow instruction target queue with the program counter value of the fetch unit. If they are equal, the target address is given to the fetch unit as the branch prediction result, which is used as the address for the next instruction fetch. The pointer of the control flow instruction target queue is then moved forward.

[0059] The present invention also proposes a storage medium for storing a program that executes any of the processor-based error detection methods based on the main core control flow information.

[0060] like Figure 4 As shown, the present invention also proposes a data processing apparatus, including a storage medium, wherein when the processor of the data processing apparatus retrieves and executes computer-executable instructions in the computer-readable storage medium, the data processing apparatus performs heterogeneous parallel error detection sharing main core control flow information.

[0061] The computer-readable storage medium of the present invention stores computer-executable instructions. When these computer-executable instructions are executed by a processor of a data processing device, the heterogeneous parallel error detection method sharing main core control flow information described above is implemented. Those skilled in the art will understand that all or part of the steps in the above method can be implemented by a program instructing related hardware (e.g., processor, FPGA, ASIC, etc.), and the program can be stored in a readable storage medium, such as a read-only memory, a disk, or an optical disk. All or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module in the above embodiments can be implemented in hardware, for example, by implementing its corresponding function through an integrated circuit, or it can be implemented as a software functional module, for example, by a processor executing a program / instruction stored in memory to implement its corresponding function. The embodiments of the present invention are not limited to any particular combination of hardware and software.

[0062] The present invention also proposes a client for running an error detection system based on any of the aforementioned processors with main core control flow information.

[0063] In summary, this invention proposes a method for using main core program flow information to guide checker core branch prediction, which can improve the performance of checker core error detection, reduce the number of checker cores required, and reduce error detection latency.

Claims

1. A processor operation error detection method based on main core control flow information, characterized in that, The method comprises the following steps: Step 1, obtaining a processing system with a main core and a check core, and the main core and the check core have the same instruction set architecture; Step 2, extracting a load and store log and a control flow generated by the main core running a program segment, the load and store log comprising a load address and load data corresponding to a load instruction, and saving a program counter value of the control flow and a target address thereof into a control flow table; Step 3, copying a state of the main core to the check core when the program segment starts running, so that the check core starts running in the same state as the main core, in the process of the check core running the program segment, for a load instruction, directly accessing the load and store log to obtain load data as a load result, and judging whether the address of the load result is the same as the load address in the load and store log, if not, indicating that an error occurs; For branch prediction, the check core directly accesses the control flow table to obtain a target address of a current control flow instruction as a branch prediction result, and judges whether the branch prediction result is the same as the target address corresponding to the current control flow instruction in the control flow table, if not, indicating that an error occurs; and judging whether a state of the check core when the program segment ends running is the same as a state of the main core when the program segment ends running, if not, indicating that an error occurs.

2. The method of claim 1, wherein the main core control flow information is based on a program counter value of the main core. The generating process of the program segment in step 3 comprises: when the main core runs a to-be-executed program, whenever a load instruction is submitted, saving a load address and load data into the load and store log corresponding to a current check core, and when the load and store log is full, taking a current state of the main core as a checkpoint to divide a program segment; and whenever a control flow instruction is submitted, saving a program counter value and a target address of the control flow instruction into the control flow table, and when the control flow table is full, taking a current state of the main core as a checkpoint to divide a program segment.

3. The method of claim 1, wherein the main core control flow information is based on a program counter value of the main core. Step 3 comprises: Whenever the main core submits a control flow instruction, adding a program counter and a target address thereof into a control flow instruction target queue of a corresponding check core; and the check core compares a program counter value of an item pointed by a head pointer of the control flow instruction target queue with a program counter value of a value taking unit every time the check core takes an instruction, and if the program counter values are equal, taking the target address as a branch prediction result for the value taking unit, as an address of next time taking an instruction by the value taking unit, and moving the pointer of the control flow instruction target queue.

4. A processor run error detection system based on master core control flow information, characterized by, The method comprises the following steps: An initial module is used for obtaining a processing system with a main core and a check core, and the main core and the check core have the same instruction set architecture; A control flow extraction module is used for extracting a load and store log and a control flow generated by the main core running a program segment, the load and store log comprising a load address and load data corresponding to a load instruction, and saving a program counter value of the control flow and a target address thereof into a control flow table; A detection module is used for copying a state of the main core to the check core when the program segment starts running, so that the check core starts running in the same state as the main core, in the process of the check core running the program segment, for a load instruction, directly accessing the load and store log to obtain load data as a load result, and judging whether the address of the load result is the same as the load address in the load and store log, if not, indicating that an error occurs; For branch prediction, the checking core directly accesses the control flow table, obtains the target address of the current control flow instruction as a branch prediction result, and judges whether the branch prediction result is the same as the target address corresponding to the current control flow instruction in the control flow table. If not, an error occurs. When the checking core ends running the program segment, it is judged whether the state of the checking core when it ends running the program segment is the same as the state of the main core when it ends running the program segment. If not, an error occurs.

5. The processor run error detection system based on master core control flow information of claim 4, wherein, The generation process of the program segment in the detection module includes: when the main core runs the to-be-executed program, whenever a load instruction is submitted, the load address and load data are saved to the load storage log corresponding to the current checking core; when the load storage log is full, the current state of the main core is taken as a checkpoint to divide the program segment; whenever a control flow instruction is submitted, the program counter value and target address of the control flow instruction are saved to the control flow table; and when the control flow table is full, the current state of the main core is taken as a checkpoint to divide the program segment.

6. The processor operation error detection system based on master core control flow information according to claim 4, wherein, The detection module is used for: Whenever the main core submits a control flow instruction, the program counter and target address thereof are added to the control flow instruction target queue of the corresponding checking core; the checking core compares the program counter value of the item pointed to by the head pointer of the control flow instruction target queue with the program counter value of the value taking unit every time it takes an instruction, and if they are equal, the value of the target address is taken as a branch prediction result for the instruction taking unit and as the address of the next instruction taking of the instruction taking unit, and the pointer of the control flow instruction target queue is moved backward.

7. A storage medium for storing a program for executing the processor running error detection method based on main core control flow information according to any one of claims 1 to 3.

8. A data processing apparatus comprising the storage medium according to claim 7, wherein when a processor of the data processing apparatus invokes and executes computer executable instructions in the storage medium, the data processing apparatus performs heterogeneous parallel error detection sharing main core control flow information.

9. A client for the processor running error detection system based on main core control flow information according to any one of claims 4 to 6.

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