A wide range soft-switching phase-shifted full-bridge circuit

Abstract

This invention discloses a phase-shifted full-bridge soft-switching circuit, which is a current injection control method based on the conduction time of the lagging branch. This method adjusts the injection time of the fifth switch Minj1 and the sixth switch Minj2 on the current injection side of the first transformer T1, as well as the size of the second capacitor Cinj1 and the third capacitor Cinj2, to regulate the current injected on the injection side of the first transformer T1, thereby increasing the current flowing through the primary side of the first transformer T1. At the same time, it charges (discharges) or discharges (charges) the parasitic capacitance Clag of the second MOS switch M2 and the fourth MOS switch M4 in the lagging branch. Before the second MOS switch M2 and the fourth MOS switch M4 are turned on, the parasitic capacitance Clag is discharged to zero, thus solving the soft-switching problem of the lagging branch.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a wide-range soft-switching phase-shifted full-bridge circuit. Background Technology

[0002] With the development of power electronics technology, DC-DC converters, as power conversion devices, are increasingly widely used. Isolated full-bridge converters, due to their high power and input-output electrical isolation advantages, have a wide range of applications. Phase-shift control enables full-bridge converters to achieve soft-switching operation with zero-voltage switching, further reducing converter conduction losses and improving transmission efficiency. They are widely used in aerospace, high-speed rail, and power systems where power quality requirements are stringent. Because of the high power and input-output electrical isolation advantages of the full-bridge circuit, it has been widely used in high-power power conversion devices. The phase-shift control full-bridge circuit uses four switching transistors that conduct alternately, reducing the conduction losses of the phase-shift full-bridge control converter. However, due to the inherent circuit structure of the lag branch, it cannot achieve zero-voltage switching. Therefore, other methods are needed to achieve soft switching of the lag branch to reduce losses. Furthermore, when the phase-shift full-bridge circuit is applied to high-voltage conversion, the inability of its lag branch to achieve soft switching results in large circuit losses, reduced efficiency, and severe heat generation. While increasing leakage inductance is generally the preferred method to solve the soft-switching problem, excessive leakage inductance can reduce circuit efficiency and is unsuitable for high-voltage circuits. Other solutions, such as modifying the load-side structure, are also too complex.

[0003] To address the above problems, there are several existing solutions: one is to increase the primary-side inductance, but this increases the primary-side circuit losses and also increases the duty cycle losses on the load side, leading to a drop in output voltage, which is uneconomical; the other is to change the switching frequency of the switching transistor to achieve soft switching, but this method can only achieve zero-voltage switching of the primary-side switch when the load power is low, which has significant limitations. Summary of the Invention

[0004] Technical problems to be solved

[0005] To address the shortcomings of existing technologies, this invention discloses a wide-range soft-switching phase-shifted full-bridge circuit to solve the problems mentioned in the background section.

[0006] Technical solution

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A wide-range soft-switching phase-shifted full-bridge circuit includes an input DC power supply Vin, a first MOS switch M1, a second MOS switch M2, a third MOS switch M3, a fourth MOS switch M4, a first rectifier diode D1, a second rectifier diode D2, a third rectifier diode D3, a fourth rectifier diode D4, a first output capacitor C1, a first output inductor L1, a first output resistor R, a first transformer T1, a fifth switch Minj1, a sixth switch Minj2, a second capacitor Cinj1, a third capacitor Cinj2, a fifth rectifier diode D5, and a sixth rectifier diode D4. Diode D6, the first MOS switch M1 and the third MOS switch M3 are connected in series and then in parallel with the input DC power supply Vin. The second MOS switch M2 and the fourth MOS switch M4 are connected in series and then in parallel with the input DC power supply Vin. The connection point between the first MOS switch M1 and the third MOS switch M3 is point A, and the connection point between the second MOS switch M2 and the fourth MOS switch M4 is point B. The first MOS switch M1 and the third MOS switch M3 have parasitic capacitance Clead, and the second MOS switch M2 and the fourth MOS switch M4 have... At the parasitic capacitance Clag, points A and B are connected to the primary side of the first transformer T1, respectively. There is a leakage inductance Lk1 between point A and the primary side of the first transformer T1. The first rectifier diode D1 and the third rectifier diode D3 are connected to point P, and the second rectifier diode D2 and the fourth rectifier diode D4 are connected to point Q. Points P and Q are connected to the load side of the first transformer T1, with a load side voltage of V1. The first output capacitor C1 and the first output resistor R are connected in parallel to one end of the first output inductor L1, and the other end of the first output inductor L1 is connected to the cathode of the second rectifier diode D2. The fifth switch Minj1, the sixth switch Minj2, the second capacitor Cinj1, the third capacitor Cinj2, the fifth rectifier diode D5, and the sixth rectifier diode D6 form the current injection side circuit topology of the first transformer T1. The fifth rectifier diode D5 and the second capacitor Cinj1 are connected in parallel and then in series with the fifth switch Minj1, and then in parallel with the current injection side V2 of the first transformer T1. The sixth rectifier diode D6 and the third capacitor Cinj2 are connected in series and then in parallel with the current injection side V3 of the first transformer T1. The current injection side voltages of the first transformer T1 are V2 and V3, respectively.

[0009] When the fifth switch Minj1 and the sixth switch Minj2 of this invention are turned off, the voltage of the first transformer T1 is switched to the current injection side. The voltage on the injection side is determined by the input DC power supply Vin and the turns ratio of the first transformer T1. The second capacitor Cinj1 and the third capacitor Cinj2 are charged through the diode D7 connected in parallel with the fifth switch Minj1 and the diode D8 connected in parallel with the sixth switch Minj2, respectively. When the fifth switch Minj1 and the sixth switch Minj2 are turned on, the second capacitor Cinj1 and the third capacitor Cinj2 are discharged through the fifth switch Minj1 and the sixth switch Minj2, respectively. Since the second capacitor Cinj1 and the third capacitor Cinj2 are connected in parallel with the fifth rectifier diode D5 and the sixth rectifier diode D6, respectively, the current on the current injection side will not flow in reverse.

[0010] The present invention determines the on / off time of the fifth switch Minj1 and the sixth switch Minj2, and the size of the second capacitor Cinj1 and the third capacitor Cinj2 as follows: the second MOS switch M2 and the fourth MOS switch M4 form a lag branch. Before the second MOS switch M2 and the fourth MOS switch M4 are turned on, the parasitic capacitance Clag of the second MOS switch M2 and the fourth MOS switch M4 in the lag branch is discharged to zero by the current injected on the current side. After the discharge is completed, the fifth switch Minj1 and the sixth switch Minj2 are turned off.

[0011] In this invention, the first MOS switch M1 and the third MOS switch M3 form a leading branch. There is a dead time between the first MOS switch M1 and the third MOS switch M3. The dead time between the second MOS switch M2 and the fourth MOS switch M4 is equal to that of the leading branch. The driving time of the fifth switch Minj1 and the sixth switch Minj2 is determined by the switching time of the lagging branch. Before the second MOS switch M2 and the fourth MOS switch M4 are turned on, the second capacitor Cinj1 and the third capacitor Cinj2 begin to discharge to discharge the parasitic capacitance Clag of the lagging branch. The current on the current injection side rises almost linearly. After the current drops to zero, it oscillates in a sinusoidal manner until it reaches zero and then stops flowing. The current flows to the primary side of the first transformer T1 and discharges the parasitic capacitance Clag of the lagging branch.

[0012] The phase-shifted full-bridge circuit of the present invention adds a current injection side circuit of a first transformer T1 compared with the conventional circuit, which can improve the defect of the conventional phase-shifted full-bridge control circuit that cannot achieve zero-voltage switching, and reduce conduction loss and improve the conduction performance of the circuit.

[0013] In this invention, when the conventional phase-shifted full-bridge control circuit reaches the end of mode 2, current is injected into the current injection side of the first transformer T1. At this time, the voltage at points A and B is 0. As soon as t2 passes, the fourth MOS switch M4 is turned off, and the current I on the leakage inductor Lk1... P Half of the current flows into the parasitic capacitance Clag of the second MOS switch M2, and half flows into the parasitic capacitance Clag of the fourth MOS switch M4. The current continues through the energy stored in the leakage inductor Lk1. When the energy stored in the leakage inductor Lk1 is insufficient to completely discharge the parasitic capacitance Clag of the second MOS switch M2, the energy stored in the leakage inductor Lk1 is:

[0014] (1)

[0015] Throughout mode 2, the voltage across the parasitic capacitance Clag of the second MOS switch M2 is equal to the voltage of the input DC power supply Vin, and the voltage across the parasitic capacitance Clag of the fourth MOS switch M4 is 0. Therefore, the energy stored in the second MOS switch M2 and the fourth MOS switch M4 is:

[0016] (2)

[0017] In the formula V in The voltage across the DC power supply Vin;

[0018] To achieve zero-voltage switching of the transistors on each bridge arm in phase-shifted full-bridge control, the parasitic capacitance of the transistors waiting to be turned on must be discharged, and at the same time, the parallel capacitance of the other transistor in the same bridge arm must be charged. Therefore, the energy relationship between them must satisfy the following:

[0019] (3)

[0020] In the formula, C lead This represents the parasitic capacitance Clead of the first MOS switch M1 and the third MOS switch M3. lag This indicates the capacitance value of the parasitic capacitance Clag of the second MOS switch M2 and the fourth MOS switch M4d, where...

[0021] In the formula V3 represents the capacitance value of the third capacitor Cinj2, V3 represents the voltage on the current injection side of the first transformer T1, and V3 represents the energy and leakage inductance on the current injection side. The energy inherent in the circuit is greater than that in the lagging branch, which is sufficient to charge and discharge the lagging branch, thus achieving zero-voltage switching of the lagging branch.

[0022] This invention discloses a wide-range soft-switching phase-shifted full-bridge circuit, which has the following beneficial effects:

[0023] This invention is a current injection control method based on the conduction time of the lagging branch. This method adjusts the injection time of the fifth switch (Minj1) and the sixth switch (Minj2) on the current injection side of the first transformer T1, as well as the values ​​of the second capacitor (Cinj1) and the third capacitor (Cinj2), to regulate the injected current. This increases the current flowing through the primary side of the first transformer T1. Simultaneously, it charges (discharges) or discharges (charges) the parasitic capacitance Clag of the second MOS switch M2 and the fourth MOS switch M4 in the lagging branch. Before the second MOS switch M2 and the fourth MOS switch M4 turn on, the parasitic capacitance Clag is discharged to zero, solving the soft-switching problem of the lagging branch. Compared with other solutions, this solution reduces conduction losses and can be used under a wide range of loads.

[0024] This invention addresses the problem that existing phase-shifted full-bridge circuits cannot achieve soft switching across the entire range of lag branches. It proposes a novel phase-shifted full-bridge control topology with auxiliary circuitry suitable for a wide load range, while reducing conduction losses and improving circuit conduction performance. Attached Figure Description

[0025] Figure 1 This is a topology diagram of a wide-range soft-switching phase-shifted full-bridge circuit according to the present invention.

[0026] Figure 2 This is a key waveform diagram showing the driving of each switching transistor after current is injected into the phase-shifted full-bridge circuit on the current injection side of the first transformer T1 of the present invention, which is a wide-range soft-switching phase-shifted full-bridge circuit.

[0027] Figure 3 This is a topology diagram of the conventional phase-shifted full-bridge circuit mode 2 in a wide-range soft-switching phase-shifted full-bridge circuit of the present invention;

[0028] Figure 4 The waveform diagram of the current injection branch current on the current injection side of the first transformer T1 of the wide-range soft-switching phase-shifted full-bridge circuit of the present invention is shown. Detailed Implementation

[0029] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0030] Please see Figures 1 to 4 The diagram shows a wide-range soft-switching phase-shifted full-bridge circuit according to the present invention.

[0031] like Figure 1As shown, a wide-range soft-switching phase-shifted full-bridge circuit includes an input DC power supply Vin, a first MOS switch M1, a second MOS switch M2, a third MOS switch M3, a fourth MOS switch M4, a first rectifier diode D1, a second rectifier diode D2, a third rectifier diode D3, a fourth rectifier diode D4, a first output capacitor C1, a first output inductor L1, a first output resistor R, a first transformer T1, a fifth switch Minj1, a sixth switch Minj2, a second capacitor Cinj1, a third capacitor Cinj2, a fifth rectifier diode D5, and a sixth rectifier diode D4. Rectifier diode D6, first MOSFET M1 and third MOSFET M3 are connected in series and then in parallel with the input DC power supply Vin, second MOSFET M2 and fourth MOSFET M4 are connected in series and then in parallel with the input DC power supply Vin, the connection point between first MOSFET M1 and third MOSFET M3 is point A, and the connection point between second MOSFET M2 and fourth MOSFET M4 is point B, first MOSFET M1 and third MOSFET M3 have parasitic capacitance Clead, second MOSFET M2 and fourth MOSFET M4 have parasitic capacitance Clead. A parasitic capacitance Clag exists. Points A and B are connected to the primary side of the first transformer T1, respectively. There is a leakage inductance Lk1 between point A and the primary side of the first transformer T1. The first rectifier diode D1 and the third rectifier diode D3 are connected to point P, and the second rectifier diode D2 and the fourth rectifier diode D4 are connected to point Q. Points P and Q are connected to the load side of the first transformer T1, and the load side voltage is V1. The first output capacitor C1 and the first output resistor R are connected in parallel to one end of the first output inductor L1, and the other end of the first output inductor L1 is connected to the cathode of the second rectifier diode D2. The circuit topology of the current injection side of the first transformer T1 consists of the fifth switch Minj1, the sixth switch Minj2, the second capacitor Cinj1, the third capacitor Cinj2, the fifth rectifier diode D5, and the sixth rectifier diode D6. The fifth rectifier diode D5 and the second capacitor Cinj1 are connected in parallel and then in series with the fifth switch Minj1, and then in parallel with the current injection side V2 of the first transformer T1. The sixth rectifier diode D6 and the third capacitor Cinj2 are connected in series and then in parallel with the current injection side V3 of the first transformer T1. The current injection side voltages of the first transformer T1 are V2 and V3, respectively.

[0032] When the fifth switch Minj1 and the sixth switch Minj2 are turned off, the voltage of the first transformer T1 is switched to the current injection side. The voltage on the injection side is determined by the input DC power supply Vin and the turns ratio of the first transformer T1. The second capacitor Cinj1 and the third capacitor Cinj2 are charged through the diode D7 connected in parallel with the fifth switch Minj1 and the diode D8 connected in parallel with the sixth switch Minj2, respectively. When the fifth switch Minj1 and the sixth switch Minj2 are turned on, the second capacitor Cinj1 and the third capacitor Cinj2 are discharged through the fifth switch Minj1 and the sixth switch Minj2, respectively. Since the second capacitor Cinj1 and the third capacitor Cinj2 are connected in parallel with the fifth rectifier diode D5 and the sixth rectifier diode D6, respectively, the current on the current injection side will not flow in reverse.

[0033] The present invention determines the on / off time of the fifth switch Minj1 and the sixth switch Minj2, and the size of the second capacitor Cinj1 and the third capacitor Cinj2 as follows: the second MOS switch M2 and the fourth MOS switch M4 form a lag branch. Before the second MOS switch M2 and the fourth MOS switch M4 are turned on, the parasitic capacitance Clag of the second MOS switch M2 and the fourth MOS switch M4 in the lag branch is discharged to zero by the current injected on the current side. After the discharge is completed, the fifth switch Minj1 and the sixth switch Minj2 are turned off.

[0034] like Figure 2 The diagram shows key waveforms of each switch driven after current is injected into the phase-shifted full-bridge circuit from the current injection side of the first transformer T1. The first MOS switch M1 and the third MOS switch M3 form a leading branch, with a dead time between them. The dead time between the second MOS switch M2 and the fourth MOS switch M4 is equal to that of the leading branch. The driving times of the fifth switch Minj1 and the sixth switch Minj2 are determined by the switching time of the lagging branch. Before the second MOS switch M2 and the fourth MOS switch M4 turn on, the second capacitor Cinj1 and the third capacitor Cinj2 begin to discharge to discharge the parasitic capacitance Clag of the lagging branch. Figure 3 It can be seen that the larger δ is, the larger the peak value of the injected current on the current injection side. The current on the current injection side rises almost linearly. After the current drops to zero, it oscillates in a sinusoidal form until it stops flowing. After the current flows to the primary side of the first transformer T1, it discharges the parasitic capacitance Clag of the lagging branch. The second capacitor Cinj1 and the third capacitor Cinj2 in the current injection side circuit are also related to the magnitude of the injected current.

[0035] The phase-shifted full-bridge circuit described above adds a current injection side circuit of the first transformer T1 compared to the traditional circuit. This can improve the defect of the traditional phase-shifted full-bridge control circuit that cannot achieve zero-voltage switching, and also reduce conduction losses and improve the conduction performance of the circuit.

[0036] like Figure 3 As shown, taking the injection of current at the end of mode 2 of the traditional phase-shifted full-bridge control circuit as an example, current is injected into the current injection side of the first transformer T1. At this time, the voltage at points A and B is 0. As soon as t2 passes, the fourth MOS switch M4 is turned off, and the current I on the leakage inductor Lk1... P Half of the current flows into the parasitic capacitance Clag of the second MOS switch M2, and half flows into the parasitic capacitance Clag of the fourth MOS switch M4. The current continues through the energy stored in the leakage inductor Lk1. When the energy stored in the leakage inductor Lk1 is insufficient to completely discharge the parasitic capacitance Clag of the second MOS switch M2, the energy stored in the leakage inductor Lk1 is:

[0037] (1)

[0038] Throughout mode 2, the voltage across the parasitic capacitance Clag of the second MOS switch M2 is equal to the voltage of the input DC power supply Vin, and the voltage across the parasitic capacitance Clag of the fourth MOS switch M4 is 0. Therefore, the energy stored in the second MOS switch M2 and the fourth MOS switch M4 is:

[0039] (2)

[0040] In the formula V in The voltage across the DC power supply Vin;

[0041] To achieve zero-voltage switching of the transistors on each bridge arm in phase-shifted full-bridge control, the parasitic capacitance of the transistors waiting to be turned on must be discharged, and at the same time, the parallel capacitance of the other transistor in the same bridge arm must be charged. Therefore, the energy relationship between them must satisfy the following:

[0042] (3)

[0043] In the formula, C lead This represents the parasitic capacitance Clead of the first MOS switch M1 and the third MOS switch M3. lag This indicates the capacitance value of the parasitic capacitance Clag of the second MOS switch M2 and the fourth MOS switch M4d, where...

[0044] In the formula V3 represents the capacitance value of the third capacitor Cinj2, V3 represents the voltage on the current injection side of the first transformer T1, and V3 represents the energy and leakage inductance on the current injection side. The energy inherent in the circuit is greater than the energy in the lagging branch, which is sufficient to charge and discharge the lagging branch, thus achieving zero-voltage switching of the lagging branch.

[0045] like Figure 4 The diagram shows the current waveform of the current injection branch on the current injection side of the first transformer T1 according to the present invention. When the fifth switch Minj1 and the sixth switch Minj2 on the current injection side are turned on, the second capacitor Cinj1 and the third capacitor Cinj2 begin to discharge, and the current rises rapidly. When the fifth switch Minj1 and the sixth switch Minj2 on the current injection side are turned off, the forward current becomes 0 because it can no longer flow. After the second capacitor Cinj1 and the third capacitor Cinj2 on the current injection side cannot discharge through the fifth switch Minj1 and the sixth switch Minj2, the freewheeling current and leakage inductance... To achieve resonance.

[0046] The working principle and process of this invention are as follows:

[0047] This invention is a current injection control method based on the conduction time of the lagging branch. This method adjusts the injection time of the fifth switch Minj1 and the sixth switch Minj2 on the current injection side of the first transformer T1, as well as the size of the second capacitor Cinj1 and the third capacitor Cinj2, to regulate the injected current on the injection side, thereby increasing the current flowing through the primary side of the first transformer T1. At the same time, it charges (discharges) or discharges (charges) the parasitic capacitance Clag of the second MOS switch M2 and the fourth MOS switch M4 in the lagging branch. Before the second MOS switch M2 and the fourth MOS switch M4 are turned on, the parasitic capacitance Clag is discharged to zero, thus solving the soft switching problem of the lagging branch.

Claims

1. A wide range soft-switching phase-shifted full-bridge circuit, characterized by: The input DC power Vin, the first MOS switch tube M1, the second MOS switch tube M2, the third MOS switch tube M3, the fourth MOS switch tube M4, the first rectifier diode D1, the second rectifier diode D2, the third rectifier diode D3, the fourth rectifier diode D4, the first output capacitor C1, the first output inductor L1, the first output resistor R, the first transformer T1, the fifth switch tube Minj1, the sixth switch tube Minj2, the second capacitor Cinj1, the third capacitor Cinj2, the fifth rectifier diode D5, and the sixth rectifier diode D6 are connected in parallel, the first MOS switch tube M1 and the third MOS switch tube M3 are connected in series and connected in parallel with the input DC power Vin, the second MOS switch tube M2 and the fourth MOS switch tube M4 are connected in series and connected in parallel with the input DC power Vin, the connection point between the first MOS switch tube M1 and the third MOS switch tube M3 is point A, the connection point between the second MOS switch tube M2 and the fourth MOS switch tube M4 is point B, the first MOS switch tube M1 and the third MOS switch tube M3 have a parasitic capacitor Clead, the second MOS switch tube M2 and the fourth MOS switch tube M4 have a parasitic capacitor Clag, point A and point B are connected to the primary side of the first transformer T1, there is a leakage inductance Lk1 between point A and the primary side of the first transformer T1, the first rectifier diode D1 and the third rectifier diode D3 are connected to point P, the second rectifier diode D2 and the fourth rectifier diode D4 are connected to point Q, point P and point Q are connected to the load side of the first transformer T1, the load side voltage is V1, the first output capacitor C1 and the first output resistor R are connected in parallel and connected to one end of the first output inductor L1, the other end of the first output inductor L1 is connected to the cathode of the second rectifier diode D2, the fifth switch tube Minj1, the sixth switch tube Minj2, the second capacitor Cinj1, the third capacitor Cinj2, the fifth rectifier diode D5, and the sixth rectifier diode D6 constitute the current injection side circuit topology of the first transformer T1, the fifth rectifier diode D5 and the second capacitor Cinj1 are connected in parallel and connected in series with the fifth switch tube Minj1, and then connected in parallel at the current injection side V2 of the first transformer T1, the sixth rectifier diode D6 and the third capacitor Cinj2 are connected in series, and then connected in parallel at the current injection side V3 of the first transformer T1, the current injection side voltages of the first transformer T1 are V2 and V3 respectively. When the fifth switch tube Minj1 and the sixth switch tube Minj2 are closed, the voltage of the first transformer T1 is converted to the current injection side, and the voltage of the current injection side is determined by the input DC power Vin and the transformation ratio of the first transformer T1. The diode D7 connected in parallel with the fifth switch tube Minj1 and the diode D8 connected in parallel with the sixth switch tube Minj2 respectively charge the second capacitor Cinj1 and the third capacitor Cinj2. When the fifth switch tube Minj1 and the sixth switch tube Minj2 are opened, the second capacitor Cinj1 and the third capacitor Cinj2 are discharged through the fifth switch tube Minj1 and the sixth switch tube Minj2 respectively. Since the second capacitor Cinj1 and the third capacitor Cinj2 are connected in parallel with the fifth rectifier diode D5 and the sixth rectifier diode D6 respectively, the current of the current injection side does not flow reversely.

2. The wide range soft-switching phase-shifted full-bridge circuit of claim 1, wherein, The opening and closing time of the fifth switch tube Minj1 and the sixth switch tube Minj2 and the size scheme of the second capacitor Cinj1 and the third capacitor Cinj2 are as follows: the second MOS switch tube M2 and the fourth MOS switch tube M4 form a lagging branch. Before the second MOS switch tube M2 and the fourth MOS switch tube M4 are opened, the parasitic capacitance Clag of the second MOS switch tube M2 and the fourth MOS switch tube M4 in the lagging branch is discharged to zero by using the current of the current injection side. After the discharge is completed, the fifth switch tube Minj1 and the sixth switch tube Minj2 are closed.

3. The wide range soft-switching phase-shifted full-bridge circuit of claim 2, wherein, The first MOS switch tube M1 and the third MOS switch tube M3 form a leading branch, and there is a dead time between the first MOS switch tube M1 and the third MOS switch tube M3. The dead time between the second MOS switch tube M2 and the fourth MOS switch tube M4 is equal to the dead time of the leading branch. The driving time of the fifth switch tube Minj1 and the sixth switch tube Minj2 is determined by the switching time of the lagging branch. Before the second MOS switch tube M2 and the fourth MOS switch tube M4 are opened, the second capacitor Cinj1 and the third capacitor Cinj2 start to discharge to discharge the parasitic capacitance Clag of the lagging branch. The current of the current injection side rises almost linearly. After the current drops to zero, it vibrates to zero current in a sinusoidal form and does not flow any more. After the current flows to the primary side of the first transformer T1, the parasitic capacitance Clag of the lagging branch is discharged.

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