A method for forming a BTO structure

Abstract

The present invention proposes a method for forming a BTO structure, which is applied to a groove with a smaller aspect ratio. In the method for forming a BTO structure provided by the present invention, the photoresist in the exposure opening area included in the pattern is exposed and developed by improving the BTOmaskCell mask area pattern, and the liquid inlet during wet etching is opened, and the photoresist is retained in other areas. The photoresists are connected into a network shape and are all connected to large blocks of glue blocks, which can maximize the support capacity of the photoresist and prevent the risk of floating glue. After that, a wet etching process is used to remove the thick oxide layer of a preset height on the inner wall of the groove through the liquid inlet during wet etching, and the process difficulty and process applicability caused by the need to accurately control the surface glue thickness and the exposure depth in the groove can also be avoided.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor device manufacturing, and in particular to a method for forming a BTO structure. Background Art

[0002] Trench insulated gate metal oxide semiconductor field effect transistor (MOSFET) has the advantages of high power density and low on-resistance due to its vertical conductive characteristics, which allows its cell size to be made smaller and eliminates the JFET (junction field effect transistor) region. It is widely used as a power switch in various power conversion and power protection circuits.

[0003] The performance of insulated gate field effect transistors (MOSFETs) depends on the thickness of the gate oxide layer. Reducing the thickness of the gate oxide layer enhances the current driving capability of MOS transistors and improves speed and power characteristics. Therefore, reducing the thickness of the gate oxide layer during process reduction can effectively improve the performance of MOS transistors. However, with the continuous miniaturization of manufacturing, various secondary effects become more and more obvious, causing the gate control capability to decrease. In order to improve the gate control capability, the gate capacitance must be increased. We know that the gate capacitance is inversely proportional to the thickness, so the physical thickness of the gate oxide layer must be very thin. However, if the physical thickness continues to be reduced to the limit, the quantum tunneling effect will occur, the gate leakage will increase, the current tunneling effect will be aggravated, and the reliability of the oxide layer will be reduced.

[0004] Therefore, for high gate controllability, a thinner gate oxide layer is generally required, but for high gate reliability and small Miller capacitance, a thick gate oxide layer is required. In order to compromise in this contradiction, we generally choose the bottom thick gate oxide (BTO) process at the bottom of the trench, so that the oxide layer is thinner in the channel to ensure high gate control, and thick gate oxide is used at the bottom and bottom corner where reliability problems are prone to occur to ensure high reliability of the device. However, this solution increases the process flow, which also leads to an increase in manufacturing costs. How to implement this structure at a low cost is very important. There are currently two mainstream implementation methods:

[0005] One method is to deposit a high-density plasma oxide layer (HDP Oxide), and then use chemical mechanical polishing (CMP) planarization and wet etching technology to etch the oxide layer to the required thickness. This method makes it difficult to control the uniformity of the oxide layer thickness at the bottom of the trench, and high-density plasma will also cause silicon etching at the bottom of the trench. Therefore, this method is complex and very costly.

[0006] Another method is to adjust the exposure amount by the thickness difference between the photoresist on the surface and inside the groove, ensure that the surface is fully exposed, the groove is underexposed, and retain the required thickness of photoresist after development to protect the thick gate oxide formed in advance. The thick gate oxide in other areas is removed by wet process, and the thin gate oxide in the channel area is realized by film formation again. Moreover, due to the coating characteristics of photoresist, for the trench structure with low aspect ratio, the photoresist filling morphology is not good, and it is difficult to achieve BTO using the photoresist solution. In addition, since the photoresist solution adopts maskless exposure (or no pattern exposure in the cell area), each photoresist in the trench is independent of each other and lacks support. After wet etching, its attachment base is etched, there is a risk of floating resin, and the difficulty of process control is also increased. Summary of the invention

[0007] The purpose of the present invention is to provide a method for forming a BTO structure to solve the problem that for a trench structure with a low aspect ratio, the photoresist filling morphology is poor, and it is difficult to realize BTO using a photoresist scheme. In addition, the current photoresist scheme adopts maskless exposure (or no pattern exposure in the Cell area), and each photoresist in the trench is independent of each other and lacks support. After wet etching, its attachment base is etched, there is a risk of floating resin, and the difficulty of process control is also increased.

[0008] In order to solve the above technical problems, the present invention provides a mask pattern, comprising:

[0009] A first mask pattern, wherein the first mask pattern includes a photoresist cross-linking area in a network shape;

[0010] A second mask pattern, wherein the second mask pattern includes a plurality of gate trench regions arranged at intervals along a first direction and having a rectangular shape;

[0011] A third mask pattern, wherein the third mask pattern comprises a plurality of exposure opening areas arranged along a first direction and spaced apart from the second mask pattern.

[0012] Furthermore, the third mask pattern is used to form a drug solution inlet during wet etching on the photoresist layer.

[0013] At the same time, in order to solve the above technical problems, the present invention also provides a method for forming a BTO structure based on the above mask pattern, including:

[0014] Providing a semiconductor substrate, wherein the upper surface of the semiconductor substrate is a first main surface, and the lower surface is a second main surface, and etching the first main surface to form a groove;

[0015] Forming a thick oxide layer and a photoresist layer, wherein the thick oxide layer covers the inner wall of the groove and the surface of the semiconductor substrate except the groove, and coating the surface of the thick oxide layer with photoresist, wherein the photoresist at least fills the groove;

[0016] Using the mask pattern, exposing and developing the exposure opening area in the third mask pattern and opening the inlet of the drug solution during wet etching;

[0017] Using a wet etching process to remove the thick oxide layer of a certain height on the surface of the semiconductor substrate except the groove and the inner wall of the groove;

[0018] The photoresist in the groove is removed by etching, and a gate oxide layer is grown on the inner wall of the groove and the surface of the semiconductor substrate except the groove to form a MOSFET device.

[0019] Furthermore, after a certain height of the thick oxide layer on the inner wall of the trench is removed by etching, the thickness of the remaining thick oxide layer at the bottom of the trench is 1.5 to 10 times the thickness of the gate oxide layer.

[0020] Furthermore, the etching amount of the thick oxide layer of a certain height on the inner wall of the groove is 10% to 90% of the groove depth.

[0021] Furthermore, forming a thick oxide layer on the inner wall of the trench and on the surface of the semiconductor substrate except the trench specifically includes:

[0022] A thick oxide layer is grown on the inner wall of the trench and on the surface of the semiconductor substrate except the trench by using a thermal oxidation process;

[0023] Alternatively, a composite oxide of thermal oxygen + deposited oxide layer is used to form a thick oxide layer.

[0024] Furthermore, the wet etching solution enters the desired wet etching area through the opened wet etching solution inlet to remove the thick oxide layer on the surface of the semiconductor substrate except the groove corresponding to the target height on the inner wall of the groove.

[0025] Furthermore, the wet etching solution for wet etching to remove the inner wall of the trench and the thick oxide layer on the surface of the semiconductor substrate except the trench is hydrofluoric acid or hot phosphoric acid.

[0026] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0027] The present invention proposes a method for forming a BTO structure. First, a groove is formed by etching on the first main surface of the semiconductor substrate, and a thick oxide layer and a photoresist layer are sequentially formed on the inner wall of the groove and the surface of the semiconductor substrate except the groove, and the photoresist at least fills the groove; then, the exposure opening area in the third mask pattern is exposed and developed by using the improved mask pattern, and the liquid inlet for wet etching is opened; then, a wet etching process is used to remove the thick oxide layer of a certain height on the surface of the semiconductor substrate except the groove and the inner wall of the groove; finally, the photoresist in the groove is etched away, and a gate oxide layer is grown on the inner wall of the groove and the surface of the semiconductor substrate except the groove to form a MOSFET device. The present invention improves the BTO mask Cell mask area pattern, and except for the specially set wet etching liquid inlet (Etch Gap), the photoresist is retained in other areas. The photoresists are connected in a network shape and are all connected to large photoresist blocks, which can maximize the support capacity of the photoresist and prevent the risk of floating photoresist. At the same time, the drug solution during wet etching enters the required wet etching area through the opened drug solution inlet during wet etching to remove the thick oxide layer on the surface of the semiconductor substrate except the groove corresponding to the target height on the inner wall of the groove, and can also avoid the need to accurately control the surface photoresist thickness and the exposure depth in the groove, which leads to a decrease in process difficulty and process applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of a process for forming a BTO structure in one embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a BTO structure mask pattern in one embodiment of the present invention;

[0030] Figure 3a-3e FIG. 1 is a schematic diagram of a forming process of a method for forming a BTO structure in one embodiment of the present invention;

[0031] Wherein, accompanying drawing 3 is marked as follows:

[0032] 100-semiconductor substrate; 110-trench;

[0033] 120-thick oxide layer; 130-photoresist layer;

[0034] 140 - gate oxide layer. DETAILED DESCRIPTION

[0035] As described in the background technology, the trench insulated gate metal oxide semiconductor field effect transistor (MOSFET) has the advantages of high power density and low on-resistance due to its vertical conductive characteristics, which allows its cell size to be made smaller and eliminates the JFET (junction field effect transistor) region. It is widely used as a power switch in various power conversion and power protection circuits.

[0036] The performance of insulated gate field effect transistors (MOSFETs) depends on the thickness of the gate oxide layer. Reducing the thickness of the gate oxide layer enhances the current driving capability of MOS transistors and improves speed and power characteristics. Therefore, reducing the thickness of the gate oxide layer during process reduction can effectively improve the performance of MOS transistors. However, with the continuous miniaturization of manufacturing, various secondary effects become more and more obvious, causing the gate control capability to decrease. In order to improve the gate control capability, the gate capacitance must be increased. We know that the gate capacitance is inversely proportional to the thickness, so the physical thickness of the gate oxide layer must be very thin. However, if the physical thickness continues to be reduced to the limit, the quantum tunneling effect will occur, the gate leakage will increase, the current tunneling effect will be aggravated, and the reliability of the oxide layer will be reduced.

[0037] Therefore, for high gate controllability, a thinner gate oxide layer is generally required, but for high gate reliability and small Miller capacitance, a thick gate oxide layer is required. In order to compromise in this contradiction, we generally choose the bottom thick gate oxide (BTO) process at the bottom of the trench, so that the oxide layer is thinner in the channel to ensure high gate control, and thick gate oxide is used at the bottom and bottom corners where reliability problems are prone to occur to ensure high reliability of the device. However, this solution increases the process flow, which also leads to an increase in manufacturing costs. How to implement this structure at a low cost is very important. There are currently two mainstream implementation methods: one is to deposit a high-density plasma oxygen shield (HDP Oxide) and then use chemical mechanical polishing (CMP) planarization and wet etching technology to etch the oxide layer to the required thickness. This method makes it difficult to control the uniformity of the oxide layer thickness at the bottom of the trench, and high-density plasma will also cause silicon etching at the bottom of the trench. Therefore, this method is complex and very costly.

[0038] Another method is to adjust the exposure amount by the thickness difference between the photoresist on the surface and inside the groove, ensure that the surface is fully exposed, the groove is underexposed, and retain the required thickness of photoresist after development to protect the thick gate oxide formed in advance. The thick gate oxide in other areas is removed by wet process, and the thin gate oxide in the channel area is realized by film formation again. Moreover, due to the coating characteristics of photoresist, for the trench structure with low aspect ratio, the photoresist filling morphology is not good, and it is difficult to achieve BTO using the photoresist solution. In addition, since the photoresist solution adopts maskless exposure (or no pattern exposure in the cell area), each photoresist in the trench is independent of each other and lacks support. After wet etching, its attachment base is etched, there is a risk of floating resin, and the difficulty of process control is also increased.

[0039] To this end, the purpose of the present invention is to provide a method for forming a BTO structure to solve the problem that for a trench structure with a low aspect ratio, the photoresist filling morphology is poor, and it is difficult to achieve BTO using a photoresist scheme. In addition, the current photoresist scheme adopts maskless exposure (or no pattern exposure in the Cell area), and each photoresist in the trench is independent of each other and lacks support. After wet etching, its attachment base is etched, there is a risk of floating resin, and the difficulty of process control is also increased.

[0040] For example, reference Figure 1 As shown, the method for forming a BTO structure includes the following steps:

[0041] Step S100, providing a semiconductor substrate, wherein the upper surface of the semiconductor substrate is a first main surface, and the lower surface is a second main surface, and the first main surface is etched to form a groove;

[0042] Step S200, forming a thick oxide layer and a photoresist layer, wherein the thick oxide layer covers the inner wall of the groove and the surface of the semiconductor substrate except the groove, and coating the surface of the thick oxide layer with photoresist, wherein the photoresist at least fills the groove;

[0043] Step S300, using the mask pattern, exposing and developing the exposure opening area in the third mask pattern and opening the inlet of the drug solution during wet etching;

[0044] Step S400, using a wet etching process to remove the thick oxide layer of a certain height on the surface of the semiconductor substrate except the trench and the inner wall of the trench;

[0045] Step S500, etching away the photoresist in the trench, and growing a gate oxide layer on the inner wall of the trench and on the surface of the semiconductor substrate except the trench, to form a MOSFET device.

[0046] That is, the present invention proposes a method for forming a BTO structure, first, etching is performed on the first main surface of the semiconductor substrate to form a groove, and a thick oxide layer and a photoresist layer are sequentially formed on the inner wall of the groove and the surface of the semiconductor substrate except the groove, and the photoresist at least fills the groove; then, the exposure opening area in the third mask pattern is exposed and developed using the improved mask pattern, and the liquid inlet for wet etching is opened; then, a wet etching process is used to remove the thick oxide layer of a certain height on the surface of the semiconductor substrate except the groove and the inner wall of the groove; finally, the photoresist in the groove is etched away, and a gate oxide layer is grown on the inner wall of the groove and the surface of the semiconductor substrate except the groove to form a MOSFET device. The present invention improves the BTO mask Cell mask area pattern, and except for the specially set wet etching liquid inlet (Etch Gap), the photoresist is retained in other areas. The photoresists are connected in a network shape and are all connected to large photoresist blocks, which can maximize the support capacity of the photoresist and prevent the risk of floating photoresist. At the same time, the drug solution during wet etching enters the required wet etching area through the opened drug solution inlet during wet etching to remove the thick oxide layer on the surface of the semiconductor substrate except the groove corresponding to the target height on the inner wall of the groove, and can also avoid the need to accurately control the surface photoresist thickness and the exposure depth in the groove, which leads to a decrease in process difficulty and process applicability.

[0047] The following is a further detailed description of a BTO structure formation method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, so the present invention is not limited to the specific embodiments disclosed below.

[0048] As shown in this application and the claims, unless the context clearly indicates an exception, the words "a", "an", "a kind" and / or "the" do not specifically refer to the singular, but may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may also include other steps or elements. When describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional spatial dimensions of length, width and depth should be included.

[0049] The following first describes in detail the BTO structure formation method provided by the present invention. Figure 2 -3, Figure 2 FIG. 1 is a schematic diagram of a BTO structure mask pattern in one embodiment of the present invention. Figure 3a-3e A schematic diagram of a forming process of a BTO structure forming method in an embodiment of the present invention; wherein the BTO structure forming method may include the following steps:

[0050] In step S100, refer to Figure 3a As shown, a semiconductor substrate 100 is provided, and the semiconductor substrate 100 is used to provide an operating platform for the subsequent process to generate a MOSFET device with a BTO structure. The material of the semiconductor substrate 100 is selected from single crystal silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate 100 can also be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors; the semiconductor substrate 100 can also be a ceramic substrate such as aluminum oxide, a quartz or glass substrate or other semiconductor materials. Exemplarily, in an embodiment of the present invention, the semiconductor substrate 100 is a silicon substrate. The upper surface of the semiconductor substrate 100 is a first main surface, and the lower surface is a second main surface. A groove 110 is formed on the first main surface of the semiconductor substrate 100 by photolithography and etching processes;

[0051] In step S200, refer to Figure 3b As shown, a thick oxide layer is formed on the inner wall of the formed trench 110 and the surface of the semiconductor substrate 100 except the trench 110. Exemplarily, in this embodiment, a thick oxide layer 120 is grown on the inner wall of the trench 110 and the surface of the semiconductor substrate 100 except the trench 110 by a thermal oxidation process, or a composite oxygen of thermal oxidation + deposited oxide layer can be used to form the thick oxide layer 120; then, a photoresist is coated on the surface of the thick oxide layer 120 to form a photoresist layer 130, and the photoresist at least fills the trench 110.

[0052] In step S300, refer to Figure 3c As shown, and combined with reference Figure 2As shown, the mask pattern is used to expose and develop the exposure opening area (Etch Gap) in the mask pattern to remove the photoresist layer corresponding to the exposure opening area, and form and open the liquid inlet during wet etching. Exemplarily, in this embodiment, the mask pattern forms three mask pattern areas along the X-axis direction, namely the first mask pattern, the second mask pattern and the third mask pattern; wherein the first mask pattern includes a photoresist cross-linking area in a network shape; the second mask pattern includes a plurality of gate groove areas arranged at intervals along the X-axis direction and in a rectangular shape; the third mask pattern includes a plurality of exposure opening areas arranged at intervals along the X-axis direction and arranged with the second mask pattern. In this embodiment, by exposing and developing the plurality of exposure opening areas arranged at intervals in the third mask pattern to remove the photoresist layer corresponding to the exposure opening area, the liquid inlet during wet etching is formed and opened, and the remaining photoresist layers are connected in a network shape and are all connected to the large block of glue, which can maximize the support capacity of the photoresist and prevent glue floating.

[0053] In step S400, refer to Figure 3d As shown, a wet etching process is used to remove the semiconductor substrate surface 100 except the groove 110 and the thick oxide layer 120 of a certain height on the inner wall of the groove. Exemplarily, in this embodiment, a wet etching solution such as hydrofluoric acid or hot phosphoric acid is used to enter the desired wet etching area through the opened wet etching solution inlet, and the concentration of the wet etching solution and the etching time are controlled to remove the thick oxide layer 120 on the surface of the semiconductor substrate 100 except the groove 110 corresponding to the target height on the inner wall of the groove. In this embodiment, due to Figure 2 The improvement of the mask pattern shown allows the thick oxide layer on the surface of the semiconductor substrate 100 to be laterally etched. Due to the isotropy of wet etching, the thick oxygen on the inner wall of the trench is etched along the depth direction of the trench. In addition, the longitudinal etching amount of the thick oxygen on the inner wall of the trench can be controlled by controlling the concentration of the solution and the etching time during wet etching, thereby retaining the thick oxygen at the bottom of the trench from being etched.

[0054] In step S500, refer to Figure 3e As shown, the photoresist layer 120 in the groove 110 and on the surface of the semiconductor substrate is removed by etching, and a gate oxide layer 140 is grown on the inner wall of the groove and on the surface of the semiconductor substrate 100 except the groove, so as to form a MOSFET device. Exemplarily, in this embodiment, the photoresist layer 120 in the groove 110 and on the surface of the semiconductor substrate is etched, and on this basis, a gate oxide layer 140 is grown by a thermal oxidation process. During the formation of the gate oxide layer, the thick oxide layer at the bottom of the groove remains unchanged, and finally a MOSFET device with a thin gate oxide layer and a thick oxide layer at the bottom of the groove is formed.

[0055] In summary, the present invention proposes a method for forming a BTO structure. First, a groove is formed by etching on the first main surface of the semiconductor substrate, and a thick oxide layer and a photoresist layer are sequentially formed on the inner wall of the groove and the surface of the semiconductor substrate except the groove, and the photoresist at least fills the groove; then, the exposure opening area in the third mask pattern is exposed and developed by using the improved mask pattern, and the liquid inlet for wet etching is opened; then, a wet etching process is used to remove the thick oxide layer of a certain height on the surface of the semiconductor substrate except the groove and the inner wall of the groove; finally, the photoresist in the groove is etched away, and a gate oxide layer is grown on the inner wall of the groove and the surface of the semiconductor substrate except the groove to form a MOSFET device. The present invention improves the BTO mask Cell mask area pattern, and the photoresist is retained in other areas except for the specially set wet etching liquid inlet (Etch Gap). The photoresists are connected in a network shape and are all connected to large photoresist blocks, which can maximize the support capacity of the photoresist and prevent the risk of floating photoresist. At the same time, the drug solution during wet etching enters the required wet etching area through the opened drug solution inlet during wet etching to remove the thick oxide layer on the surface of the semiconductor substrate except the groove corresponding to the target height on the inner wall of the groove, and can also avoid the need to accurately control the surface photoresist thickness and the exposure depth in the groove, which leads to a decrease in process difficulty and process applicability.

[0056] It should be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

[0057] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0058] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A method for forming a BTO structure, characterized in that: include: Providing a semiconductor substrate, wherein the upper surface of the semiconductor substrate is a first main surface, and the lower surface is a second main surface, and etching the first main surface to form a groove; Forming a thick oxide layer and a photoresist layer, wherein the thick oxide layer covers the inner wall of the groove and the surface of the semiconductor substrate except the groove, and coating the surface of the thick oxide layer with photoresist, wherein the photoresist at least fills the groove; Providing a mask pattern, the mask pattern comprising a first mask pattern, a second mask pattern, and a third mask pattern, the first mask pattern comprising a photoresist cross-linking area in a network shape, the second mask pattern comprising a plurality of gate trench areas arranged at intervals along a first direction and in a rectangular shape, and the third mask pattern comprising a plurality of exposure opening areas arranged at intervals along the first direction and in a relationship with the second mask pattern; Exposing and developing the exposure opening area in the third mask pattern and opening the inlet of the drug solution for wet etching; Using a wet etching process to remove the thick oxide layer of a certain height on the surface of the semiconductor substrate except the groove and the inner wall of the groove; The photoresist in the groove is removed by etching, and a gate oxide layer is grown on the inner wall of the groove and the surface of the semiconductor substrate except the groove to form a MOSFET device.

2. The method for forming a BTO structure according to claim 1, wherein: The third mask pattern is used to form a drug solution inlet during wet etching on the photoresist layer.

3. The method for forming a BTO structure according to claim 2, characterized in that: After a certain height of the thick oxide layer on the inner wall of the trench is removed by etching, the thickness of the remaining thick oxide layer at the bottom of the trench is 1.5 to 10 times the thickness of the gate oxide layer.

4. The method for forming a BTO structure according to claim 2, wherein: The etching amount of the thick oxide layer of a certain height on the inner wall of the groove is 10% to 90% of the groove depth.

5. The method for forming a BTO structure according to claim 2, wherein: Forming a thick oxide layer on the inner wall of the trench and the surface of the semiconductor substrate except the trench, specifically comprising: growing a thick oxide layer on the inner wall of the trench and the surface of the semiconductor substrate except the trench by a thermal oxidation process; Alternatively, a composite oxide of thermal oxygen + deposited oxide layer is used to form a thick oxide layer.

6. The method for forming a BTO structure according to claim 2, wherein: The wet etching solution enters the desired wet etching area through the opened wet etching solution inlet to remove the thick oxide layer on the surface of the semiconductor substrate except the groove corresponding to the target height on the inner wall of the groove.

7. The method for forming a BTO structure according to claim 2, wherein: The wet etching solution for wet etching to remove the inner wall of the trench and the thick oxide layer on the surface of the semiconductor substrate except the trench is hydrofluoric acid or hot phosphoric acid.

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