Processor start-up system and method

Abstract

The embodiment of the present application provides a processor starting system and method, wherein the system comprises a programmable logic device, a processor, a first flash chip and a second flash chip, the second flash chip is in a state of prohibiting write operation, the programmable logic device is used for resetting the processor and controlling the second flash chip to be connected with the processor when the processor fails to start through the first flash chip; the processor is used for starting through the second flash chip, and repairing the first flash chip according to a boot program in the second flash chip after starting; after the first flash chip is repaired, the programmable logic device is used for controlling the first flash chip to be connected with the processor and resetting the processor. The present application can ensure the normal start of the processor based on original data without change, and realizes the priority selection of the first flash chip to ensure the normal start of the processor.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a processor boot system and method. Background Technology

[0002] In embedded device hardware design, the processor reset address typically points to the Flash chip. This allows the processor to automatically jump to the Flash chip to execute and load system files to boot the device during power-on or reset. The Flash chip usually stores critical data such as the U-Boot (Universal Boot Loader) bootloader, Linux kernel, root file system, and user programs. Errors in reading or writing data to the Flash chip, abnormal Flash data upgrade processes, or incorrect files being upgraded can all prevent the embedded device from booting properly.

[0003] The existing technology is to implement a dual-Flash chip automatic switching design for the Serial Peripheral Interface (SPI). This design allows the device to boot based on either the primary Flash chip or the backup Flash chip. If booting based on the primary Flash chip fails, the backup Flash chip will be used for booting.

[0004] During the above process, if the data on the backup Flash chip is also corrupted, the normal startup of the device cannot be guaranteed. Since updating the content on the Flash chip will upgrade the data on both chips at the same time, if the upgraded content itself is incorrect, it will cause both Flash chips to fail to start normally, thus causing the device to fail to start through the Flash chip.

[0005] Therefore, it can be seen that in the existing technology, when a device is started using a Flash chip, if the data on the backup Flash chip is also corrupted or the upgraded content is incorrect, the device will fail to start. Summary of the Invention

[0006] This application provides a processor boot system and method to solve the problem in the prior art where the device cannot boot if the data on the backup Flash chip is corrupted or the upgraded content is incorrect when booting the device via the Flash chip.

[0007] In a first aspect, embodiments of this application provide a processor boot system, comprising: a programmable logic device, a processor, a first Flash chip, and a second Flash chip; a first terminal of the programmable logic device is connected to the first Flash chip or the second Flash chip via a first chip select signal line, and a second terminal of the programmable logic device is connected to the processor via a second chip select signal line; the second Flash chip is in a write-disabled state, and the programmable logic device is used for:

[0008] When the processor fails to boot from the first Flash chip, the processor is reset, and the second Flash chip is connected to the processor via the first chip select signal line.

[0009] The processor is used to boot from the second Flash chip and, after booting, repair the first Flash chip according to the boot program in the second Flash chip;

[0010] After the first Flash chip is repaired, the programmable logic device controls the first Flash chip to connect to the processor via the first chip select signal line and resets the processor.

[0011] Secondly, embodiments of this application provide a processor startup method applied to a programmable logic device. A first terminal of the programmable logic device is connected to a first Flash chip or a second Flash chip via a first chip select signal line, and a second terminal of the programmable logic device is connected to a processor via a second chip select signal line. The second Flash chip is in a write-prohibited state. The method includes:

[0012] If the processor fails to boot from the first Flash chip, the processor is reset.

[0013] The second Flash chip is controlled to connect to the processor via the first chip select signal line, so that the processor can be started through the second Flash chip;

[0014] After the first Flash chip is repaired according to the boot program in the second Flash chip, the first Flash chip is controlled to connect to the processor through the first chip select signal line, and the processor is reset.

[0015] In this embodiment, by setting the second Flash chip to a write-prohibited state, data corruption or unavailability on the second Flash chip due to any abnormal situation can be avoided. When the processor fails to boot through the first Flash chip, the programmable logic device resets the processor and controls the processor to boot through the second Flash chip. This ensures the normal boot of the processor based on the original, unaltered data. After the processor repairs the first Flash chip using the second Flash chip, the programmable logic device controls the first Flash chip to connect to the processor and resets the processor, enabling the processor to boot through the first Flash chip. This prioritizes the use of the first Flash chip to ensure the normal boot of the processor. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram illustrating the existing technology for automatic switching design of dual Flash chips for SPI;

[0018] Figure 2 This is a schematic diagram of one of the processor boot systems provided in an embodiment of this application;

[0019] Figure 3 This is a second schematic diagram illustrating the processor boot system provided in an embodiment of this application.

[0020] Figure 4 This is the third schematic diagram illustrating the processor boot system provided in this application embodiment;

[0021] Figure 5 A schematic diagram illustrating the processor startup method provided in an embodiment of this application;

[0022] Figure 6 This is an overall flowchart illustrating the processor boot method provided in an embodiment of this application;

[0023] Figure 7 This diagram illustrates the upgraded bootloader provided in this application embodiment and the process of starting the processor based on the upgraded bootloader. Detailed Implementation

[0024] In the embodiments of this application, the term "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0025] In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0027] See Figure 1The diagram illustrates a dual-Flash chip auto-flip design for SPI. The two Flash chips share the serial clock SCK line, Master Input / Slave Output (MISO) data line, and Master Output / Slave Input (MOSI) data line, and are connected to the processor's SPI Flash controller. The processor's CS line (chip select signal line) is connected to the two Flash chips via a Field Proframmable Gate Array (FPGA) to switch the chip select signal, allowing the FPGA to determine which Flash chip the processor boots from. The FPGA can be replaced with an Erasable Programmable Logic Device (EPLD). Both the U-boot programs on Flash0 and Flash1 chips are in normal working order; the U-boot program on Flash0 is used as the primary boot program, and the U-boot program on Flash1 is used as the backup boot program. When the embedded device powers on or resets, the FPGA starts first, preferentially switching the chip select signal to the Flash0 chip and starting a timer. The processor then executes and loads the bootloader from the Flash0 chip. If, for some reason, the bootloader on the Flash0 chip malfunctions, the timer expires, the FPGA resets the embedded device, switches the chip select signal to the Flash1 chip, and the processor executes and loads the bootloader from the Flash1 chip. When the content on the Flash chips needs to be updated, the data on both the Flash0 and Flash1 chips is updated simultaneously to synchronize the version data of the two Flash chips.

[0028] Therefore, in existing technologies, when booting a device via a Flash chip, there is a problem where the device cannot boot if the data on the backup Flash chip is corrupted or the updated content is incorrect. To address this problem, this application provides a processor boot system and method. By storing a bootable file on a backup Flash chip, and preventing the processor from performing write operations on the backup Flash chip, the availability of the backup Flash chip is guaranteed, thus ensuring the normal boot of the processor.

[0029] The processor boot system provided in the embodiments of this application is described below. See also... Figures 2 to 4This application provides a processor boot system, including: a programmable logic device 11, a processor 12, a first Flash chip 13, and a second Flash chip 14. A first terminal of the programmable logic device 11 is connected to either the first Flash chip 13 or the second Flash chip 14 via a first chip select signal line, and a second terminal of the programmable logic device 11 is connected to the processor 12 via a second chip select signal line. The second Flash chip 14 is in a write-disabled state. The programmable logic device 11 is used for:

[0030] When the processor 12 fails to boot through the first Flash chip 13, the processor 12 is reset and the second Flash chip 14 is controlled to connect to the processor 12 through the first chip select signal line.

[0031] The processor 12 is used to boot through the second Flash chip 14 and repair the first Flash chip 13 according to the boot program in the second Flash chip 14 after booting;

[0032] After the first Flash chip 13 is repaired, the programmable logic device 11 controls the first Flash chip 13 to connect to the processor 12 through the first chip select signal line and resets the processor 12.

[0033] The processor boot system provided in this application includes: a programmable logic device 11, a processor 12, a first Flash chip 13, and a second Flash chip 14. The second end of the programmable logic device 11 is connected to the processor 12 through a second chip select signal line, and the first end of the programmable logic device 11 is connected to the first Flash chip 13 or the second Flash chip 14. Specifically, the programmable logic device 11 can control the first chip select signal line to connect to the first Flash chip 13 or the second Flash chip 14.

[0034] The processor 12 can boot by connecting to the programmable logic device 11, or by connecting the programmable logic device 11 to the first Flash chip 13 or the second Flash chip 14, and executing and loading a boot program from the first Flash chip 13 or the second Flash chip 14. Here, the first Flash chip 13 can be understood as the primary Flash chip, and the second Flash chip 14 as the backup Flash chip. When the first terminal of the programmable logic device 11 is connected to the first Flash chip 13 via the first chip select signal line, the processor 12 can be connected to the first Flash chip 13. If the processor 12 fails to execute and load the boot program from the first Flash chip 13, it is determined that the processor 12 has failed to boot from the first Flash chip 13, and at this time, the programmable logic device 11 can control the processor 12 to reset. The programmable logic device 11 can be an FPGA or an EPLD.

[0035] After the programmable logic device 11 controls the processor 12 to reset, it can control the second Flash chip 14 to connect to the processor 12. Specifically, the first terminal of the programmable logic device 11 is connected to the second Flash chip 14 via a first chip select signal line, and the connection between the processor 12 and the second Flash chip 14 is achieved based on the connection between the second terminal of the programmable logic device 11 and the processor 12 via a second chip select signal line. By controlling the connection of the second Flash chip 14 to the processor 12, the processor 12 can execute and load the boot program from the second Flash chip 14, thus enabling the processor 12 to boot. The second Flash chip 14 stores a file that can be booted normally, and it is in a write-prohibited state to ensure its continued availability and prevent data corruption.

[0036] After the processor 12 successfully boots through the second Flash chip 14, the processor 12 can repair the first Flash chip 13 according to the boot program in the second Flash chip 14. This repair involves copying the boot program from the second Flash chip 14 to the first Flash chip 13, thus updating the boot program within the Flash chip. After the repair is complete, the programmable logic device 11 can control the connection between the first Flash chip 13 and the processor 12. After establishing the connection, the programmable logic device 11 resets the processor 12, enabling the processor 12 to boot through the first Flash chip 13. This also prepares for potential future upgrades to the content on the Flash chip, updating the content on the first Flash chip 13 and ensuring that the second Flash chip 14 remains unaffected.

[0037] In the above embodiments of this application, by setting the second Flash chip to a write-prohibited state, it is possible to avoid any abnormal situation causing the data on the second Flash chip to be damaged or unusable. When the processor fails to start through the first Flash chip, the programmable logic device resets the processor and controls the processor to start through the second Flash chip. This can ensure the normal startup of the processor based on the original data that has not been modified. After the processor repairs the first Flash chip according to the second Flash chip, the programmable logic device controls the first Flash chip to connect to the processor and resets the processor, so that the processor starts through the first Flash chip, thereby achieving the priority selection of the first Flash chip to ensure the normal startup of the processor.

[0038] In an optional embodiment of this application, see [link to application]. Figures 2 to 4 As shown, when the processor 12 fails to boot via the first Flash chip 13 and the programmable logic device 11 resets the processor 12, the programmable logic device 11 is further used for:

[0039] When the processor 12 is powered on or reset, the first chip select signal line is connected to the first Flash chip 13 and a timer is started so that the processor 12 can start by executing and loading the boot program in the first Flash chip 13;

[0040] If no shutdown command for the timer is received within the preset time period, it is determined that the processor 12 has failed to start through the first Flash chip 13, and the processor 12 is reset.

[0041] After the processor 12 is powered on or reset, the programmable logic device 11 starts first, preferentially switching the first chip select signal line to the first Flash chip 13, thus establishing a connection between the first Flash chip 13 and the processor 12. When the programmable logic device 11 switches the first chip select signal line to the first Flash chip 13, it starts a timer, at which point the processor 12 can be started through the first Flash chip 13.

[0042] After the processor 12 boots normally based on the first Flash chip 13, it can send a shutdown command to the programmable logic device 11. The programmable logic device 11 then shuts down a timer based on the shutdown command. This timer is an internal timer of the programmable logic device 11, and the programmable logic device 11 receives the shutdown command within a preset duration after the timer starts. At this time, the programmable logic device 11 maintains its connection with the first Flash chip 13 to prepare for potential future upgrades to the bootloader, ensuring that the first Flash chip 13 is the chip for which version upgrades are performed.

[0043] If the programmable logic device 11 does not receive a shutdown command for the timer within a preset time period, it indicates that the boot program on the first Flash chip 13 is corrupted or unusable (version unavailable), and the processor 12 fails to boot through the first Flash chip. At this time, the programmable logic device 11 resets the processor 12. The start time of the preset time period is the time when the timer is started. For example, if the programmable logic device 11 does not receive a shutdown command within 5 seconds after the timer is started, it is determined that the processor 12 has failed to boot.

[0044] In the above embodiments of this application, a timer is started when the programmable logic device is connected to the first Flash chip. If a shutdown command is received within a preset time period, it is determined that the processor has started normally. If no shutdown command is received within the preset time period, it is determined that the processor has failed to start. This realizes the determination of whether the processor has started normally based on the reception of shutdown commands within a preset time period.

[0045] In an optional embodiment of this application, see [link to application]. Figures 2 to 4 As shown, when the processor 12 fails to boot through the first Flash chip 13, the programmable logic device 11 is used to record the first information of the processor 12 failing to boot through the first Flash chip 13;

[0046] When the second Flash chip 14 is connected to the processor 12 via the first chip select signal line, the programmable logic device 11 is used to control the first chip select signal line to connect to the second Flash chip 14 according to the first information, and start the timer;

[0047] Processor 12 is used to execute and load the boot program within the second Flash chip 14 via connection to the second Flash chip 14 for booting;

[0048] After the processor 12 successfully executes and loads the boot program in the second Flash chip 14, the programmable logic device 11 is used to turn off the timer according to the received shutdown instruction.

[0049] When processor 12 fails to boot via the first Flash chip 13, programmable logic device 11 can record first information. When programmable logic device 11 controls the second Flash chip 14 to connect to processor 12 via the first chip select signal line, it can determine based on the first information that processor 12 failed to boot via the first Flash chip 13. Therefore, it can control the first chip select signal line to connect to the second Flash chip 14, controlling the connection between processor 12 and the second Flash chip 14. When controlling the connection of the first chip select signal line to the second Flash chip 14, a timer is started. Since the data on the second Flash chip 14 cannot be modified, processor 12 can boot normally by executing and loading the boot program within the second Flash chip 14.

[0050] When the processor 12 starts up normally through the second Flash chip 14, the processor 12 sends a shutdown command to the programmable logic device 11. After receiving the shutdown command, the programmable logic device 11 can shut down the timer based on the received shutdown command.

[0051] Since the second Flash chip 14 serves as a backup Flash chip, after the processor 12 boots normally via the backup Flash chip, it can repair the first Flash chip 13 (the primary Flash chip) based on the backup Flash chip, thereby ensuring the availability of the first Flash chip 13.

[0052] In the above embodiments of this application, when the processor fails to boot through the first Flash chip, the programmable logic device records first information and controls the first chip select signal line to connect to the second Flash chip according to the recorded first information. This enables the processor to boot by executing and loading the boot program in the second Flash chip, thereby ensuring that the processor boots normally based on the original data.

[0053] In an optional embodiment of this application, see [link to application]. Figures 2 to 4 As shown, when controlling the first Flash chip 13 to connect to the processor 12 via the first chip select signal line and resetting the processor 12, the programmable logic device 11 is used to control the first chip select signal line to connect to the first Flash chip 13; the first Flash chip 13 is used to connect to the processor 12 via the first chip select signal line; after the first Flash chip 13 is connected to the processor 12, the programmable logic device 11 is used to reset the processor 12; the processor 12 is used to execute and load the boot program in the first Flash chip 13 for startup.

[0054] When the programmable logic device 11 controls the connection of the first Flash chip 13 to the processor 12, it can control the first chip select signal line to connect to the first Flash chip 13. Based on the connection between the second terminal of the programmable logic device 11 and the processor 12 via the second chip select signal line, the connection between the processor 12 and the first Flash chip 13 is achieved. After the first Flash chip 13 is connected to the processor 12, the programmable logic device 11 can reset the processor 12, allowing the processor 12 to boot through the first Flash chip 13. This prioritizes the booting of the processor 12 through the first Flash chip 13 and prepares for potential future upgrades to the content on the Flash chip, updating the content on the first Flash chip 13 and ensuring that the second Flash chip 14 is unaffected.

[0055] In the above embodiments of this application, after the processor repairs the first Flash chip based on the second Flash chip, the programmable logic device controls the first Flash chip to connect to the processor, and the processor starts up based on the first Flash chip, which can realize the priority selection of the main Flash chip to ensure the normal startup of the processor.

[0056] In an optional embodiment of this application, see [link to application]. Figures 2 to 4 As shown, when the boot program in the first Flash chip 13 and the second Flash chip 14 is inconsistent with the latest version of the boot program in the server, the processor 12 is used to write the latest version of the boot program in the server into the first Flash chip 13; the programmable logic device 11 is used to reset the processor 12; the processor 12 is used to execute and load the latest version of the boot program in the first Flash chip 13 for startup; wherein, the server is the application server corresponding to the target application running on the processor 12.

[0057] When it is necessary to upgrade the boot program on the Flash chip, since the second Flash chip 14 is write-prohibited, only the boot program on the first Flash chip 13 can be upgraded. By setting the second Flash chip 14 to a write-prohibited state, the problem of the processor 12 failing to start due to write operation errors or errors in the content to be upgraded can be avoided.

[0058] When the bootloader on the first Flash chip 13 is inconsistent with the latest version of the bootloader in the server, the processor 12 writes the latest version of the bootloader from the server into the first Flash chip 13, thus upgrading the bootloader within the first Flash chip 13. After the upgrade is complete (i.e., after the processor 12 completes the write operation), the programmable logic device 11 resets the processor 12, and the processor 12 can then boot by executing and loading the latest version of the bootloader in the first Flash chip 13. Here, the server is an application server, and the target application corresponding to the application server runs on the processor 12.

[0059] In the embodiments described above, the processor updates the boot program in the first Flash chip based on the latest version of the boot program in the server, and the programmable logic device resets the processor after the update is completed, so that the processor can start based on the latest version of the boot program.

[0060] In an optional embodiment of this application, such as Figure 3 As shown, the processor 12 includes a serial peripheral interface (SPI) Flash controller 121;

[0061] The first Flash chip 13 is connected to the SPI Flash controller 121 via the serial clock SCK line, the master input / slave output MISO data line, and the master output / slave input MOSI data line; the second Flash chip 14 is connected to the SPI Flash controller 121 via the serial SCK line and the MISO data line.

[0062] The SPI Flash controller 121 is connected to the second terminal of the programmable logic device 11 via the second chip select signal line.

[0063] In this embodiment, the first Flash chip 13 and the second Flash chip 14 share the serial SCK line and the MISO data line, and are connected to the SPI Flash controller 121. The SPI Flash controller 121 is connected to the programmable logic device 11 via the second chip select signal line. The programmable logic device 11 can be an FPGA or an EPLD. The programmable logic device 11 is connected to either the first Flash chip 13 or the second Flash chip 14 via the first chip select signal line, so that the programmable logic device 11 can determine which Flash chip the processor 12 will boot from. The first Flash chip 13 is connected to the SPI Flash controller 121 via the MOSI data line, while the second Flash chip 14 is not connected to the MOSI data line, thus ensuring that write operations are disabled on the second Flash chip 14 and preventing data corruption.

[0064] Regarding the second Flash chip 14, after a bootable program is programmed using a programmer, it is then mounted onto the device board. Because the improved hardware design does not connect the MOSI data line, software cannot perform write operations on it, thus preventing data corruption or version unavailability under various abnormal conditions. Through the above design of this embodiment, the constant availability of the second Flash chip 14 can be guaranteed.

[0065] In an optional embodiment of this application, such as Figure 4 As shown, the processor 12 includes a parallel Flash interface 122;

[0066] The first Flash chip 13 and the second Flash chip 14 are connected to the parallel Flash interface 122 through the data bus and the address bus. The first Flash chip 13 is connected to the parallel Flash interface 122 through the write enable signal line.

[0067] The parallel Flash interface 122 is connected to the second terminal of the programmable logic device 11 via the second chip select signal line.

[0068] The first Flash chip 13 and the second Flash chip 14 share the data bus [0…8 / 16] and the address bus [0~19], and are connected to the parallel Flash interface 122 of the processor 12. The parallel Flash interface 122 is connected to the programmable logic device 11 through the second chip select signal line. The programmable logic device 11 is connected to either the first Flash chip 13 or the second Flash chip 14 to determine which Flash chip the processor 12 will boot from. The WE (write enable signal line) is only connected to the first Flash chip 13 and not to the second Flash chip 14, meaning that write operations are disabled on the backup Flash chip to prevent data corruption.

[0069] Regarding the second Flash chip 14, after a bootable program is programmed using a programmer, it is then mounted onto the device board. Because the improved hardware design does not connect to the WE (Web Application Wave), software cannot perform write operations on it, preventing data corruption or version unavailability under various abnormal conditions. Through the above design of this embodiment, the constant availability of the second Flash chip 14 is guaranteed, and protection is provided for the primary and backup Flash chip design of the parallel interface.

[0070] The above describes the processor boot system provided in this application embodiment. By setting the second Flash chip to a write-prohibited state, any abnormal situation can prevent the data on the second Flash chip from being damaged or unusable. When the processor fails to boot through the first Flash chip, the programmable logic device resets the processor and controls the processor to boot through the second Flash chip. This ensures the normal boot of the processor based on the original, unaltered data. After repairing the first Flash chip using the second Flash chip, the programmable logic device resets the processor, and the processor boots through the first Flash chip. This prioritizes the use of the first Flash chip to ensure the normal boot of the processor and can prepare for potential upgrades to the boot program within the Flash chip.

[0071] Furthermore, it is possible to determine whether the processor has started normally by observing the reception of shutdown commands within a preset time period; by recording first information when the processor fails to start through the first Flash chip, and controlling the processor to start through the second Flash chip based on the recorded first information, it is possible to ensure that the processor starts normally based on the original data; by controlling the boot program in the first Flash chip to upgrade by the processor, it is possible to ensure that the processor starts based on the latest boot program after the processor is reset.

[0072] The processor boot method provided in this application embodiment is described below. This processor boot method is applied to a programmable logic device. The first terminal of the programmable logic device is connected to a first Flash chip or a second Flash chip via a first chip select signal line. The second terminal of the programmable logic device is connected to the processor via a second chip select signal line. The second Flash chip is in a write-disabled state. Figure 5 As shown, the method includes:

[0073] Step 501: If the processor fails to boot through the first Flash chip, reset the processor.

[0074] The processor can execute and load a boot program from either the first Flash chip or the second Flash chip to boot. The first Flash chip can be understood as the primary Flash chip, and the second Flash chip as the backup Flash chip. When the first terminal of the programmable logic device (PLD) is connected to the first Flash chip via the first chip select signal line, the connection between the processor and the first Flash chip can be achieved through the connection of the second terminal of the PLD to the processor via the second chip select signal line. If the processor fails to execute and load the boot program from the first Flash chip, it is determined that the processor has failed to boot from the first Flash chip. At this point, the PLD can control the processor to reset. The PLD can be a programmable gate array (FPGA) or an erasable programmable logic device (EPLD).

[0075] Step 502: Control the second Flash chip to connect to the processor through the first chip select signal line so that the processor can start through the second Flash chip.

[0076] After the programmable logic device (PLD) controls the processor to reset, it can control the second Flash chip to connect to the processor via the first chip select signal line. That is, the first terminal of the PLD connects to the second Flash chip via the first chip select signal line, and the second terminal of the PLD connects to the processor via the second chip select signal line, thus establishing a connection between the processor and the second Flash chip. By controlling the connection between the second Flash chip and the processor, the processor can execute and load the boot program from the second Flash chip, enabling the processor to start up. The second Flash chip stores a bootable file and is in a write-disabled state to ensure its continued availability and prevent data corruption.

[0077] Step 503: After the first Flash chip is repaired according to the boot program in the second Flash chip, the first Flash chip is controlled to connect to the processor through the first chip select signal line, and the processor is reset.

[0078] After the processor successfully boots through the second Flash chip, it can repair the first Flash chip using the bootloader within the second Flash chip. This repair involves copying the bootloader from the second Flash chip to the first Flash chip, thus updating the bootloader within the first Flash chip. After repairing the first Flash chip, the programmable logic device (PLD) can control the connection between the first Flash chip and the processor. Specifically, the first terminal of the PLD is connected to the first Flash chip via a first chip select signal line, and the second terminal of the PLD is connected to the processor via a second chip select signal line, thus establishing the connection between the processor and the first Flash chip. After establishing the connection between the first Flash chip and the processor, resetting the processor allows it to boot from the first Flash chip and prepares for potential future upgrades to the content on the first Flash chip, updating the content on the first Flash chip and ensuring the second Flash chip remains unaffected.

[0079] In the above-described implementation process of this application, by setting the second Flash chip to a write-prohibited state, it is possible to avoid any abnormal situation causing the data on the second Flash chip to be damaged or unusable. When the processor fails to boot through the first Flash chip, the programmable logic device resets the processor and controls the processor to boot through the second Flash chip. This can ensure the normal boot of the processor based on the original data that has not been altered. After the processor repairs the first Flash chip according to the second Flash chip, the programmable logic device controls the first Flash chip to connect to the processor and resets the processor, so that the processor boots through the first Flash chip, thereby prioritizing the use of the first Flash chip to ensure the normal boot of the processor.

[0080] In an optional embodiment of this application, when the processor fails to boot through the first Flash chip, resetting the processor includes:

[0081] When the processor is powered on or reset, the first chip select signal line is connected to the first Flash chip, and a timer is started so that the processor can start by executing and loading the boot program in the first Flash chip.

[0082] If no shutdown command is received within the preset time, it is determined that the processor has failed to boot through the first Flash chip, and the processor is reset.

[0083] After the processor is powered on or reset, the programmable logic device (PLD) starts first. After startup, the PLD prioritizes switching the first chip select signal line to the first Flash chip, establishing a connection between the PLD and the first Flash chip. During this connection process, a timer is started, enabling the processor to boot by executing and loading the boot program within the first Flash chip.

[0084] After the processor boots normally based on the first Flash chip, it can send a shutdown command to the programmable logic device (PLD). The PLD shuts down its internal timer according to the shutdown command, and receives the shutdown command within a preset time after the timer starts. At this time, the PLD maintains its connection with the first Flash chip to prepare for potential future bootloader upgrades, ensuring that the first Flash chip is the chip that will be upgraded.

[0085] If the programmable logic device does not receive a shutdown command for the timer within a preset time period, it indicates that the boot program on the first Flash chip is corrupted or unusable (version unavailable), and the processor fails to boot through the first Flash chip. In this case, the processor needs to be reset. The start time of the preset time period is the time when the timer is started. For example, if no shutdown command is received within 5 seconds after the timer is started, it is determined that the processor boot has failed.

[0086] In the above implementation process of this application, a timer is started when the programmable logic device is connected to the first Flash chip. If a shutdown command is received within a preset time period, it is determined that the processor has started normally. If no shutdown command is received within the preset time period, it is determined that the processor has failed to start. This realizes the determination of whether the processor has started normally based on the reception of shutdown commands within a preset time period.

[0087] In an optional embodiment of this application, when the processor fails to boot via the first Flash chip, the method further includes:

[0088] Record the first message indicating that the processor failed to boot from the first Flash chip;

[0089] Controlling the second Flash chip to connect to the processor via the first chip select signal line includes:

[0090] Based on the first information, the first chip select signal line is connected to the second Flash chip, and a timer is started so that the processor can start by executing and loading the boot program in the second Flash chip;

[0091] After the processor successfully executes and loads the boot program in the second Flash chip, it shuts down the timer according to the received shutdown command.

[0092] When the processor fails to boot from the first Flash chip, the programmable logic device (PLD) can record the first piece of information indicating the failure. When controlling the connection between the second Flash chip and the processor via the first chip select signal line, the recorded information can be used to determine if the processor failed to boot from the first Flash chip. Therefore, the first chip select signal line can be controlled to connect to the second Flash chip, establishing the connection between the processor and the second Flash chip. Simultaneously, a timer is started when the first chip select signal line is connected to the second Flash chip. Since the data on the second Flash chip is immutable, the processor can boot normally by executing and loading the boot program within the second Flash chip.

[0093] After the processor successfully executes and loads the boot program in the second Flash chip, the processor can start normally. At this time, the processor sends a shutdown command to the programmable logic device. After receiving the shutdown command, the programmable logic device can shut down the timer based on the received shutdown command.

[0094] Since the second Flash chip serves as a backup Flash chip, after the processor boots normally through the backup Flash chip, it can repair the first Flash chip (the primary Flash chip) based on the backup Flash chip to ensure the availability of the first Flash chip.

[0095] In the above implementation process of this application, when the processor fails to boot through the first Flash chip, the programmable logic device records the first information and controls the first chip select signal line to connect to the second Flash chip according to the recorded first information. This enables the processor to boot by executing and loading the boot program in the second Flash chip, thereby ensuring that the processor boots normally based on the original data.

[0096] In an optional embodiment of this application, controlling the first Flash chip to connect to the processor via the first chip select signal line and resetting the processor includes:

[0097] The first chip select signal line is connected to the first Flash chip, so that the first Flash chip is connected to the processor;

[0098] After the first Flash chip is connected to the processor, the processor is reset so that it can start by executing and loading the boot program within the first Flash chip.

[0099] When controlling the connection of the first Flash chip to the processor, the first chip select signal line can be connected to the first Flash chip, and the connection between the processor and the first Flash chip can be achieved through the connection of the second terminal of the programmable logic device to the processor via the second chip select signal line. After the first Flash chip is connected to the processor, the processor can be reset to boot the processor based on the first Flash chip. This ensures that the first Flash chip is prioritized to guarantee the normal startup of the processor, and it can also prepare for subsequent version upgrades of the content on the Flash chip, updating the content on the first Flash chip and ensuring that the second Flash chip is not affected.

[0100] In the above implementation process of this application, after the processor repairs the first Flash chip based on the second Flash chip, the programmable logic device controls the first Flash chip to connect to the processor, and the processor starts up based on the first Flash chip, which can realize the priority selection of the main Flash chip to ensure the normal startup of the processor.

[0101] The following describes the boot method for the aforementioned processor through an overall implementation process. (See attached document.) Figure 6 As shown, the steps include the following.

[0102] Step 601: After the processor is powered on or reset, the programmable logic device starts, controls the first chip select signal line to connect to the first Flash chip, and starts the timer, enabling the processor to boot through the first Flash chip. If booting is successful, proceed to step 602; otherwise, proceed to step 603.

[0103] Step 602: The processor sends a shutdown command to the programmable logic device (PLD). The PLD shuts down the timer according to the shutdown command, while maintaining its connection with the first Flash chip, preparing for subsequent boot program upgrades of the first Flash chip. This concludes the process.

[0104] Step 603: The programmable logic device records the first information of the processor's failure to boot based on the first Flash chip and resets the processor.

[0105] Step 604: The programmable logic device starts up. Based on the first information, it is determined that the processor failed to start up based on the first Flash chip. The first chip select signal line is connected to the second Flash chip, and the timer is started.

[0106] Step 605: The processor starts normally through the second Flash chip and sends a shutdown command to the programmable logic device. The programmable logic device shuts down the timer based on the shutdown command.

[0107] Step 606: The processor repairs the boot program of the first Flash chip according to the boot program of the second Flash chip.

[0108] Step 607: After the processor completes the repair of the first Flash chip, the programmable logic device controls the first Flash chip to connect with the processor and resets the processor.

[0109] In the above implementation process, the programmable logic device first controls the first Flash chip to connect to the processor. When the processor fails to boot through the first Flash chip, the programmable logic device controls the second Flash chip to connect to the processor. After the processor successfully boots through the second Flash chip and the first Flash chip is repaired, the programmable logic device controls the first Flash chip to connect to the processor, so that the processor preferentially selects the first Flash chip to boot.

[0110] In an optional embodiment of this application, when the bootloader in the first Flash chip and the second Flash chip is inconsistent with the latest version of the bootloader in the server, the method further includes:

[0111] After the processor writes the latest version of the bootloader from the server into the first Flash chip, the processor is reset so that it can start by executing and loading the latest version of the bootloader from the first Flash chip.

[0112] The server is the application server corresponding to the target application running on the processor.

[0113] When it is necessary to upgrade the boot program on the Flash chip, since the second Flash chip is write-prohibited, only the boot program on the first Flash chip can be upgraded. By setting the second Flash chip to a write-prohibited state, the problem of the processor failing to start due to write operation errors or errors in the content to be upgraded can be avoided.

[0114] When the bootloader on the first Flash chip is inconsistent with the latest version of the bootloader in the server, the processor writes the latest version of the bootloader from the server into the first Flash chip, thus upgrading the bootloader within the first Flash chip. After the upgrade is complete (i.e., after the processor completes the write operation), the processor is reset, and the processor can then boot by executing and loading the latest version of the bootloader in the first Flash chip. Here, the server is an application server, and the target application corresponding to the application server runs on the processor.

[0115] The following example illustrates the process by which the upgraded bootloader boots the processor based on the upgraded bootloader. (See [link to documentation]). Figure 7As shown, the steps may include the following.

[0116] Step 701: The processor starts normally based on the first Flash chip.

[0117] Step 702: When the boot program in the first Flash chip is inconsistent with the latest version of the boot program in the server, the processor writes the latest version of the boot program in the server into the first Flash chip.

[0118] Step 703: Reset the programmable logic device processor.

[0119] Step 704: The processor starts by executing and loading the latest version of the bootloader in the first Flash chip.

[0120] It should be noted that, in the event that the processor fails to boot from the first Flash chip, the processor can first boot from the second Flash chip. After successful boot, the processor repairs the first Flash chip using the second Flash chip. Once the first Flash chip is repaired, it boots normally using the first Flash chip. If the bootloader in the first Flash chip is inconsistent with the latest version of the bootloader in the server, the processor writes the latest version of the bootloader from the server into the first Flash chip, upgrading the bootloader in the first Flash chip. Then, the programmable logic device resets the processor, and the processor boots from the latest version of the bootloader in the first Flash chip.

[0121] In the above implementation process of this application, the processor updates the boot program in the first Flash chip based on the latest version of the boot program in the server, and resets the processor after the update is completed, so that the processor can start based on the latest version of the boot program.

[0122] The above is the overall implementation flow of the processor boot method provided in this application embodiment. By setting the second Flash chip to a write-prohibited state, the data on the second Flash chip can be prevented from being damaged or unusable due to any abnormal situation. When the processor fails to boot through the first Flash chip, the programmable logic device resets the processor and controls the processor to boot through the second Flash chip. This can ensure the normal boot of the processor based on the original data that has not been changed. After the processor repairs the first Flash chip according to the second Flash chip, the programmable logic device resets the processor, and the processor boots through the first Flash chip. This can ensure the normal boot of the processor by prioritizing the use of the first Flash chip and can also prepare for the possible upgrade of the boot program in the Flash chip in the future.

[0123] Furthermore, it is possible to determine whether the processor has started normally by observing the reception of shutdown commands within a preset time period; by recording first information when the processor fails to start through the first Flash chip, and controlling the processor to start through the second Flash chip based on the recorded first information, it is possible to ensure that the processor starts normally based on the original data; by controlling the boot program in the first Flash chip to upgrade by the processor, it is possible to ensure that the processor starts based on the latest boot program after resetting the processor.

[0124] Based on the above description, the core idea of ​​this application is that a backup Flash chip stores a file that can boot normally, while the processor cannot write data to the backup Flash chip. This ensures that the backup Flash chip is always available and its data content will not be corrupted. When the data on the primary Flash chip is corrupted, the timer times out, and the programmable logic device controls the processor to restart. Then, the processor and backup Flash chip are connected, allowing the processor to boot through the backup Flash chip. Furthermore, after the processor boots through the backup Flash chip, the timer is turned off, and the programmable logic device connects the processor and primary Flash chip. Thus, when the content on the Flash chip needs to be upgraded, only the content on the primary Flash chip is updated; the backup Flash chip remains unaffected. This solves the problems of the processor failing to boot normally due to incorrect upgrade content causing simultaneous upgrades of both primary and backup Flash chips, and the problem of the processor failing to boot if the data on the backup Flash chip is corrupted.

[0125] The processor boot system and method provided in this application disable write operations on a backup Flash chip in the hardware design, ensuring that the backup Flash chip can be used normally under any circumstances. Simultaneously, the software design optimizes processor boot, primary Flash chip fault repair, and primary Flash chip bootloader upgrades, guaranteeing that the processor can boot normally under any circumstances. This solves the problems in existing technologies where write errors to the backup Flash chip, data corruption, and bugs in the bootloader to be upgraded prevent the processor from booting. Furthermore, while providing primary / backup protection for the SPI Flash controller, it also addresses the primary / backup Flash issues of the parallel interface.

[0126] Those skilled in the art will understand that embodiments of this application can be provided as systems and methods. This application may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects.

[0127] The processor boot system and method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A processor boot system, comprising: A programmable logic device, a processor, a first Flash chip, and a second Flash chip, wherein a first terminal of the programmable logic device is connected to the first Flash chip or the second Flash chip via a first chip select signal line, and a second terminal of the programmable logic device is connected to the processor via a second chip select signal line; The write enable signal line is connected only to the first Flash chip and not to the second Flash chip; characterized in that the second Flash chip is in a write-disabled state, and the programmable logic device is used for: When the processor fails to boot through the first Flash chip, the processor is reset, and the programmable logic device is used to record the first information of the processor failing to boot through the first Flash chip; When controlling the second Flash chip to connect to the processor via the first chip select signal line, the programmable logic device is used to control the first chip select signal line to connect to the second Flash chip according to the first information, and start a timer; The processor is used to execute and load the boot program within the second Flash chip for startup via a connection with the second Flash chip; After the processor successfully executes and loads the boot program in the second Flash chip, the programmable logic device is used to turn off the timer according to the received shutdown instruction; The processor is used to boot from the second Flash chip and, after booting, repair the first Flash chip according to the boot program in the second Flash chip; After the first Flash chip is repaired, the programmable logic device controls the first Flash chip to connect to the processor via the first chip select signal line and resets the processor.

2. The processor boot system according to claim 1, characterized in that, When the processor fails to boot from the first Flash chip and the programmable logic device resets the processor, the programmable logic device is further configured to: When the processor is powered on or reset, the first chip select signal line is connected to the first Flash chip, and a timer is started so that the processor can start by executing and loading the boot program in the first Flash chip; If no shutdown command to shut down the timer is received within a preset time period, it is determined that the processor has failed to boot through the first Flash chip, and the processor is reset.

3. The processor boot system according to claim 1, characterized in that, When controlling the first Flash chip to connect to the processor via the first chip select signal line and resetting the processor, the programmable logic device is used to control the first chip select signal line to connect to the first Flash chip; The first Flash chip is used to connect to the processor via the first chip select signal line; After the first Flash chip is connected to the processor, the programmable logic device is used to reset the processor; The processor is used to execute and load the boot program within the first Flash chip for startup.

4. The processor boot system according to claim 1, characterized in that, When the boot program in the first Flash chip and the second Flash chip is inconsistent with the latest version of the boot program in the server, the processor is used to write the latest version of the boot program in the server into the first Flash chip; The programmable logic device is used to reset the processor; The processor is used to execute and load the latest version of the boot program in the first Flash chip for startup; The server is the application server corresponding to the target application running on the processor.

5. The processor boot system according to any one of claims 1 to 4, characterized in that, The processor includes a serial peripheral interface (SPI) Flash controller. The first Flash chip is connected to the SPI Flash controller via a serial clock SCK line, a master input / slave output MISO data line, and a master output / slave input MOSI data line; the second Flash chip is connected to the SPI Flash controller via the serial SCK line and the MISO data line. The SPI Flash controller is connected to the second terminal of the programmable logic device via the second chip select signal line.

6. The processor boot system according to any one of claims 1 to 4, characterized in that, The processor includes a parallel Flash interface; The first Flash chip and the second Flash chip are connected to the parallel Flash interface through a data bus and an address bus. The first Flash chip is connected to the parallel Flash interface through a write enable signal line. The parallel Flash interface is connected to the second terminal of the programmable logic device via the second chip select signal line.

7. A processor startup method, applied to a programmable logic device, wherein a first terminal of the programmable logic device is connected to a first Flash chip or a second Flash chip via a first chip select signal line, a second terminal of the programmable logic device is connected to a processor via a second chip select signal line, and a write enable signal line is connected only to the first Flash chip and not to the second Flash chip; characterized in that, The second Flash chip is in a write-prohibited state, and the method includes: If the processor fails to boot from the first Flash chip, the processor is reset. Record the first information indicating that the processor failed to boot through the first Flash chip; Controlling the second Flash chip to connect to the processor via the first chip select signal line includes: Based on the first information, the first chip select signal line is connected to the second Flash chip, and a timer is started so that the processor can start by executing and loading the boot program in the second Flash chip; Wherein, after the processor successfully executes and loads the boot program in the second Flash chip, the timer is turned off according to the received shutdown instruction; The second Flash chip is controlled to connect to the processor via the first chip select signal line, so that the processor can be started through the second Flash chip; After the first Flash chip is repaired according to the boot program in the second Flash chip, the first Flash chip is controlled to connect to the processor through the first chip select signal line, and the processor is reset.

8. The processor boot method according to claim 7, characterized in that, The step of resetting the processor when the processor fails to boot through the first Flash chip includes: When the processor is powered on or reset, the first chip select signal line is connected to the first Flash chip, and a timer is started so that the processor can start by executing and loading the boot program in the first Flash chip; If no shutdown command to shut down the timer is received within a preset time period, it is determined that the processor has failed to boot through the first Flash chip, and the processor is reset.

9. The processor boot method according to claim 7, characterized in that, The step of controlling the first Flash chip to connect to the processor via the first chip select signal line and resetting the processor includes: Control the first chip select signal line to connect to the first Flash chip, so that the first Flash chip is connected to the processor; After the processor is connected to the first Flash chip, the processor is reset so that it can start by executing and loading the boot program in the first Flash chip.

10. The processor boot method according to claim 7, characterized in that, When the bootloader in the first Flash chip and the second Flash chip is inconsistent with the latest version of the bootloader in the server, the method further includes: After the processor writes the latest version of the bootloader from the server into the first Flash chip, the processor is reset so that it can start by executing and loading the latest version of the bootloader in the first Flash chip. The server is the application server corresponding to the target application running on the processor.

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