An image processing method, apparatus, reference monitor, and medium

Abstract

The present application provides an image processing method, apparatus, reference monitor and medium. Since in the embodiments of the present application, the correspondence between the first number of the first VBO signal line and the column is pre-stored in the FPGA, for each first transmission group, the FPGA determines the first target column where each column of RGB data in the first transmission group is located according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group and the pre-stored correspondence, avoiding problems such as pixel misalignment in the received image and improving the accuracy of image transmission.

Description

Technical Field

[0001] This application relates to the field of image processing technologies, and in particular, to an image processing method, apparatus, reference monitor, and medium. Background Art

[0002] In the prior art, when a system-on-chip (SOC) transmits images to a field-programmable gate array (FPGA), the transmission is mainly carried out through HS(VBO) signal lines.

[0003] Specifically, the SOC and the corresponding pins of the FPGA are connected through VBO signal lines. The SOC groups the pixel points in the image by column, and the number of pixel points in each group is the same as the number of VBO signal lines. The SOC sequentially sends the RGB data of each column in each group to the FPGA according to the order of the pins. After receiving the RGB data, the FPGA uses the pin order as the order of the VBO signal lines to combine and splice the received RGB data to obtain a complete image.

[0004] However, when designing and manufacturing each chip circuit board, in order to meet the requirements of the circuit board size or equal length and equal spacing of the VBO signal lines, the connection order of the pins of the SOC and the FPGA will be adjusted during the manufacturing process, which results in the pins of the SOC and the FPGA not being correspondingly connected. For example, pin 1 of the SOC should be connected to pin 1 of the FPGA, but during the manufacturing process, pin 1 of the SOC is connected to pin 3 of the FPGA. This further leads to the image spliced by the FPGA being inconsistent with the original image, reducing the accuracy rate of image transmission. Summary of the Invention

[0005] This application provides an image processing method, apparatus, reference monitor, and medium to solve the problem in the prior art that due to the influence of circuit board design, the pins of the SOC and the FPGA are not correspondingly connected, which further leads to the image spliced by the FPGA being inconsistent with the original image and the low accuracy rate of image transmission.

[0006] In a first aspect, an embodiment of this application provides an image processing method applied to a field-programmable gate array (FPGA). The method includes:

[0007] Receiving the RGB data of each column sent by a system-on-chip (SOC) through a first preset number of first VBO signal lines, and determining the RGB data of each column included in each first transmission group;

[0008] For each first transmission group, according to the first VBO signal lines corresponding to each column of RGB data included in the first transmission group, and the correspondence between the first numbers of the first VBO signal lines and the columns pre-stored, determine the first target column where each column of RGB data in the first transmission group is located; wherein, each first transmission group includes the first preset number of columns of RGB data;

[0009] Determine a target image according to the first target column where each column of RGB data in each first transmission group is located and the order of the first transmission groups.

[0010] In a second aspect, an embodiment of the present application further provides an image processing device, which is applied to a field programmable gate array (FPGA). The device includes:

[0011] A receiving module, configured to receive each column of RGB data sent by a system on a chip (SOC) through the first preset number of first VBO signal lines, and determine each column of RGB data included in each first transmission group;

[0012] A determining module, configured to, for each first transmission group, according to the first VBO signal lines corresponding to each column of RGB data included in the first transmission group, and the correspondence between the first numbers of the first VBO signal lines and the columns pre-stored, determine the first target column where each column of RGB data in the first transmission group is located; wherein, each first transmission group includes the first preset number of columns of RGB data; and determine a target image according to the first target column where each column of RGB data in each first transmission group is located and the order of the first transmission groups.

[0013] In a third aspect, an embodiment of the present application further provides a reference monitor, which includes an FPGA, and the FPGA is configured to execute the steps of the image processing method as described above.

[0014] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the steps of the image processing method as described above are implemented.

[0015] In an embodiment of the present application, the FPGA receives the RGB data of each column sent by the SOC through the first preset number of first VBO signal lines, and determines the RGB data of each column included in each first transmission group; for each first transmission group, according to the first VBO signal line corresponding to the RGB data of each column included in the first transmission group, and the corresponding relationship between the first number of the first VBO signal line and the column saved in advance, determine the first target column where the RGB data of each column in the first transmission group is located; wherein, each first transmission group includes the first preset number of columns; according to the target column where the RGB data of each column in each first transmission group is located and the order of the first transmission group, determine the target image. Since in the embodiment of the present application, the corresponding relationship between the first number of the first VBO signal line and the column is saved in advance in the FPGA, for each first transmission group, the FPGA determines the first target column where the RGB data of each column in the first transmission group is located according to the first VBO signal line corresponding to the RGB data of each column included in the first transmission group and the saved corresponding relationship, avoiding problems such as pixel misalignment in the received image and improving the accuracy of image transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 Schematic diagram of the structure of a reference monitor in a related art provided by an embodiment of the present application;

[0018] Figure 2 Schematic diagram of an image processing process provided by an embodiment of the present application;

[0019] Figure 3 Schematic diagram of the structure of the reference monitor provided by an embodiment of the present application;

[0020] Figure 4 Schematic diagram of the first test image and the first predicted image provided by an embodiment of the present application;

[0021] Figure 5 Schematic diagram of the determination process of the corresponding relationship between the first number of the first VBO signal line and the column provided by an embodiment of the present application;

[0022] Figure 6 Schematic diagram of the internal structure of the FPGA provided by an embodiment of the present application;

[0023] Figure 7Schematic diagram of the internal structure of the data detection and comparison module of the FPGA provided by the embodiment of the present application;

[0024] Figure 8 Schematic diagram of the second test images of two second transmission groups provided by the embodiment of the present application;

[0025] Figure 9 Schematic diagram of the predicted images corresponding to the second test images of two second transmission groups provided by the embodiment of the present application;

[0026] Figure 10 Schematic diagram of the determination process of the correspondence between the second number and the column of the second VBO signal line provided by the embodiment of the present application;

[0027] Figure 11 Schematic diagram of the structure of an image processing device provided by the embodiment of the present application;

[0028] Figure 12 Schematic diagram of the structure of an electronic device provided by the embodiment of the present application. Detailed implementation manners

[0029] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are only a part rather than all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art shall fall within the protection scope of the present application.

[0030] In the related art, the reference monitor includes a SOC, an FPGA, and a timer control register (TCON). Figure 1 Schematic diagram of a reference monitor in the related art. As Figure 1 shown, the pins of the SOC are connected to the pins on the FPGA side through the VBO signal line, and the pins on the other side of the FPGA are connected to the TCON. Among them, the RGB data of the image is transmitted from the SOC to the FPGA chip through the VBO signal line. After the FPGA chip processes the RGB data, it is transmitted to the backend TCON through the VBO signal line for final display.

[0031] Among them, the SOC, FPGA, and FPGA and TCON are usually connected by 8 VBO signal lines. Each VBO signal line is used to transmit the RGB data of a specific column in the image. Moreover, the 8 VBO signal lines independently transmit the RGB data. The order between each line of the VBO signal lines does not affect the quality of data transmission, but it will affect the arrangement order of the RGB data. Based on this, if the back-end chip does not recombine the image data in the order transmitted by the front-end chip, the image displayed on the back-end will have pixel misalignment and display errors.

[0032] Therefore, to solve the above problems, the embodiments of the present application provide an image processing method. This method is applied to an FPGA. The FPGA receives the RGB data of each column sent by the SOC through a first preset number of first VBO signal lines, and determines the RGB data of each column included in each first transmission group; for each first transmission group, according to the first VBO signal line corresponding to the RGB data of each column included in this first transmission group, and the corresponding relationship between the first number of the first VBO signal line and the column saved in advance, determine the first target column where the RGB data of each column in this first transmission group is located; where each first transmission group includes a first preset number of columns; according to the first target column where the RGB data of each column in each first transmission group is located and the order of the first transmission group, determine the target image.

[0033] Figure 2 It is a schematic diagram of an image processing process provided by the embodiments of the present application. This process includes:

[0034] S201: Receive the RGB data of each column sent by the SOC through a first preset number of first VBO signal lines, and determine the RGB data of each column included in each first transmission group.

[0035] An image processing method provided by the embodiments of the present application is applied to an FPGA, and the FPGA is deployed on a reference monitor.

[0036] Figure 3 It is a schematic diagram of the structure of the reference monitor provided by the embodiments of the present application. As shown in this Figure 3As shown, the reference monitor includes: a microcontroller unit (MCU), a system on a chip (SOC), a personal computer (PC), a host computer, and a timing controller (TCON). Among them, in the embodiments of the present application, the MCU can configure the parameters of the field-programmable gate array (FPGA) after the FPGA is powered on; the SOC is the core device of the reference monitor and has rich input and output interfaces, such as a high-definition multimedia interface (HDMI) and a vertical blanking output (VBO), etc. At the same time, the SOC also has digital signal processing functions; the host computer software is installed in the PC, and technicians can read and write the content stored in the FPGA in real time through the host computer software installed in the PC; the TCON is used to drive the liquid crystal display to display images; the FPGA is used to receive the images sent by the SOC, perform image processing on the images, such as enhancing the image quality effect, etc., and send the processed images to the TOCN.

[0037] In the embodiments of the present application, the FPGA is connected to the SOC through a first preset number of first VBO signal lines, and the SOC transmits the RGB data of each column of the image to the FPGA through the first preset number of first VBO signal lines. Among them, in the embodiments of the present application, when transmitting the RGB data of the image, the SOC divides the image into at least one first transmission group, and each first VBO signal line is used to transmit the RGB data of a specific column in each first transmission group. Each first transmission group contains the first preset number of columns of RGB data.

[0038] Based on this, in the embodiments of the present application, the FPGA receives the RGB data of each column sent by the SOC through the first preset number of first VBO signal lines, and determines the RGB data of each column included in each first transmission group according to the transmission order of the RGB data of each column in the corresponding first VBO signal line. Specifically, the RGB data of each column with the same transmission order is located in a first transmission group. For example, in the embodiments of the present application, the first column of RGB data transmitted by each first VBO signal line is determined as a first transmission group, and the second column of RGB data transmitted by each first VBO signal line is determined as a first transmission group, etc.

[0039] S202: For each first transmission group, determine the first target column where the RGB data of each column in the first transmission group is located according to the first VBO signal line corresponding to the RGB data of each column included in the first transmission group and the corresponding relationship between the first number of the first VBO signal line and the column saved in advance; where each first transmission group contains the first preset number of columns of RGB data.

[0040] Due to the design of the circuit board, the pins with the same serial number on the FPGA and the SOC may not be correspondingly connected. To avoid the FGPA directly arranging each column of RGB data received according to the pin order, resulting in pixel misalignment in the obtained image, in the embodiment of the present application, the FPGA stores the correspondence between the first number of the first VBO signal line and the column, so that after the FPGA receives each column of RGB data, for each first transmission group, it can determine the first target column corresponding to each column of RGB data included in the first transmission group according to this correspondence.

[0041] Among them, in the embodiment of the present application, the columns in this correspondence are the columns in the first transmission group, and the first number of each first VBO signal line is generally the serial number of the pin of the FPGA corresponding to the first VBO signal line.

[0042] Specifically, in the embodiment of the present application, after the FPGA determines the RGB data included in each first transmission group, the FPGA determines the first VBO signal line for transmitting each column of RGB data and obtains the first number corresponding to each of the first VBO signal lines saved. The FPGA determines the first target column where each column of RGB data is located according to the correspondence between the first number of the saved first VBO signal line and the column. Among them, in the embodiment of the present application, the first target column corresponding to each column of RGB data is the column where the column of RGB data is located in the first transmission group. The FPGA will finally generate an image consistent with the image sent by the SOC according to the order of each first transmission group where each column of RGB data is located and the first target column of each column of RGB data in the first transmission group where it is located.

[0043] Among them, it should be noted that each first transmission group includes a first preset number of columns.

[0044] In addition, in the embodiment of the present application, a VBO signal line order adjustment module for the receiving end can be added inside the FGPA, and the correspondence between the first number of the first VBO signal line and the column is saved in this adjustment module.

[0045] In the embodiment of the present application, the correspondence between the first number of the first VBO signal line and the column can be saved in the MCU. When the FPGA is powered on, the MCU will write this correspondence into the FPGA, so that the FPGA can combine each column of RGB data received according to this correspondence and generate an image, where the image generated by the FPGA is consistent with the image sent by the SOC.

[0046] S203: Determine the target image according to the first target column where each column of RGB data in each first transmission group is located and the order of the first transmission group.

[0047] In an embodiment of the present application, after the FPGA determines the first target column where each column of RGB data in each first transmission group is located, the FPGA determines the target image according to the first target column where each column of RGB data in each first transmission group is located and the order of the first transmission groups.

[0048] Specifically, for each first transmission group, the FPGA determines the sub-target image corresponding to the first transmission group according to the first target column where each column of RGB data in the first transmission group is located. After the FPGA determines each sub-target image corresponding to each first transmission group, the FPGA splices each sub-target image according to the order of the first transmission groups to obtain the target image.

[0049] Since in an embodiment of the present application, the correspondence between the first number of the first VBO signal line and the column is pre-stored in the FPGA, for each first transmission group, the FPGA determines the first target column where each column of RGB data in the first transmission group is located according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group and the pre-stored correspondence, avoiding problems such as pixel misalignment in the received image and improving the accuracy of image transmission.

[0050] In order to avoid problems such as pixel misalignment in the image obtained after image recombination based on the received RGB data, on the basis of the above embodiment, in an embodiment of the present application, determining the first target column where each column of RGB data in the first transmission group is located according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group and the pre-stored correspondence between the first number of the first VBO signal line and the column includes:

[0051] For each column of RGB data in the first transmission group, determine the target first VBO signal line corresponding to the column of RGB data; according to the correspondence, determine the column corresponding to the target first number of the target first VBO signal line, and determine the column as the first target column where the column of RGB data is located.

[0052] In an embodiment of the present application, when the FPGA determines the first target column where each column of RGB data in the first transmission group is located, for each column of RGB data in the first transmission group, the FPGA determines the target first VBO signal line for transmitting the column of RGB data, and according to the saved correspondence, determines the column corresponding to the target first number of the target first VBO signal line, and determines the column as the first target column where the column of RGB data is located.

[0053] For example, in the embodiments of the present application, the first transmission group sent by the SOC to the FPGA through four first VBO signal lines includes four columns of RGB data. Among them, the numbers of the four first VBO signal lines are 1, 2, 3, and 4 respectively. The four columns of RGB data are RGB data A, RGB data B, RGB data C, and RGB data D respectively. The first VBO signal line numbered 1 transmits RGB data A, the first VBO signal line numbered 2 transmits RGB data B, the first VBO signal line numbered 3 transmits RGB data C, and the first VBO signal line numbered 4 transmits RGB data D. And, the corresponding relationship stored in the FPGA is that number 1 corresponds to the first column, number 2 corresponds to the fourth column, number 3 corresponds to the second column, and number 4 corresponds to the third column. Based on this, the FPGA determines that the first target column where RGB data A is located is the first column, the first target column where RGB data B is located is the fourth column, the first target column where RGB data C is located is the second column, and the first target column where RGB data D is located is the third column.

[0054] In order to improve the accuracy of image transmission, on the basis of the above embodiments, in the embodiments of the present application, the determination process of each first transmission group includes:

[0055] Determine the transmission order of each RGB data in the corresponding first VBO signal line;

[0056] Determine the RGB data with the same transmission order as a first transmission group.

[0057] In the embodiments of the present application, when the FPGA determines each first transmission group, the FPGA determines the transmission order of each RGB data in the corresponding first VBO signal line, and determines the RGB data with the same transmission order as a first transmission group. For example, the FPGA determines the first column RGB data transmitted by each first VBO signal line as a transmission group, etc.

[0058] In order to enable the FPGA to store the corresponding relationship between the first number of the first VBO signal line and the column, and thus improve the accuracy of image transmission, on the basis of the above embodiments, in the embodiments of the present application, the determination process of the corresponding relationship between the first number of the first VBO signal line and the column includes:

[0059] Send the generated first test image to the SOC through the host computer, where each column of the first test RGB data in the first test image is different, and the first test image includes a first preset number of columns;

[0060] Send a sending instruction carrying each column of RGB data to the SOC, and receive each column of second test RGB data sent by the SOC through the first preset number of first VBO signal lines;

[0061] For the second test RGB data of each column, determine the second target column corresponding to the second test RGB data of this column in the first test image, and correspondingly save the second target column and the first number of the first VBO signal line transmitting the second test RGB data of this column.

[0062] In the embodiment of the present application, the FPGA generates a first test image and sends the first test image to the SOC. Among them, since the correspondence between the first number of the first VBO signal line and the column is applicable to all first transmission groups, therefore, in order to save transmission resources, in the embodiment of the present application, the first test image can be composed of one first transmission group, that is, the number of columns included in the first test image is the same as the number of first VBO signal lines.

[0063] Among them, in order to enable the SOC to accurately receive the first test image generated by the FPGA, in the embodiment of the present application, the FPGA sends the generated first test image to the SOC through the host computer.

[0064] In the embodiment of the present application, after the FPGA sends the first test image to the SOC through the host computer, the FPGA sends a sending instruction to the SOC, so that after receiving the sending instruction, the SOC sends the first test RGB data of each column of the first test image to the FPGA through the first preset number of first VBO signal lines. And, since the RGB data received by a certain serial number pin of the FPGA may not be the same column as the RGB data sent by the same serial number pin of the SOC. For example, the pin with serial number 1 of the SOC is responsible for sending the RGB data of the first column of the first test image, but the RGB data received by the pin with serial number 1 of the FPGA is the third column of the first test image. Therefore, in the embodiment of the present application, the RGB data received by the FPGA is called the second test RGB data.

[0065] In the embodiment of the present application, after the FPGA receives the second test RGB data, for the second test RGB data of each column, the FPGA determines the second target column corresponding to the second test data of this column in the first test image, and correspondingly saves the second target column and the first number of the first VBO signal line transmitting the second test RGB data of this column.

[0066] Specifically, in the embodiment of the present application, when the FPGA determines the second target column corresponding to the second test RGB data of each column, it can be determined by one or more of the following methods:

[0067] Method 1: For the second test RGB data of each column, according to the first test RGB data corresponding to each column of pixel points in the first test image, search for the second target column corresponding to the second test RGB data in the first test image.

[0068] Since the first test RGB data of each column in the first test image is different, for each column of the second test RGB data, the FPGA can search in the first test image for the target first test RGB data with the same value as the second test RGB data, and determine the column where the target first test RGB data is located as the second target column corresponding to the second test RGB data.

[0069] For example, there are 4 columns of first test RGB data in the first test image. For a certain second test RGB data, if the FPGA determines that the value of the second test RGB data is the same as the value of the first test RGB data in the third column of the first test image, then the FPGA determines that the third column is the second target column corresponding to the second test RGB data.

[0070] Method 2: The FPGA sorts the first numbers of each first VBO signal line pre - saved, and splices the second test RGB data transmitted by each first VBO signal line according to the sorting result to obtain a first predicted image. The FPGA compares the first predicted image with the first test image, and adjusts the order of the second test RGB data in the first predicted image according to the order of the first test RGB data in the first test image, so that the first predicted image is consistent with the first test image. For each second test RGB data, the FPGA determines the column where the second test RGB data is located in the adjusted first predicted image, and determines this column as the second target column corresponding to the second test RGB data.

[0071] Figure 4 is a schematic diagram of the first test image and the first predicted image provided by the embodiment of the present application. As shown in Figure 4 the figure, the first test RGB data of each column in the first test image is different, and the second and third columns of the first predicted image are different from those of the first test image.

[0072] In addition, in the embodiment of the present application, after the FPGA determines the correspondence between the first number of the first VBO signal line and the column, the FPGA saves this correspondence in a register and sends this correspondence to the MCU, so that the MCU writes this correspondence into the program of the power - on configuration parameters. When the FPGA is powered on again, the MCU can send this power - on configuration parameter to the FPGA, so that the FPGA saves this correspondence.

[0073] Figure 5 is a schematic diagram of the determination process of the correspondence between the first number of the first VBO signal line and the column provided by the embodiment of the present application. As shown in Figure 5 the figure, this process includes:

[0074] S501: Power on the reference monitor.

[0075] S502: The MCU configures the parameters of the FPGA so that the reference monitor can work properly.

[0076] S503: The technician controls the FPGA to enter the VBO signal line detection mode through the host computer.

[0077] In the embodiment of the present application, the technician can send an instruction to the FPGA to enter the VBO signal line detection mode through the host computer, so that the FPGA enters the VBO signal line detection mode and determines the correspondence between the first number of the first VBO signal line and the column.

[0078] S504: The FPGA generates a first test image.

[0079] S505: The host computer obtains the first test image generated by the FPGA and sends the first test image to the SOC.

[0080] S506: The FPGA sends a transmission instruction carrying the RGB data of each column to the SOC and receives the second test RGB data of each column sent by the SOC through the first preset number of first VBO signal lines.

[0081] S507: The FPGA sorts the first numbers of each first VBO signal line saved in advance and splices the second test RGB data transmitted by each first VBO signal line according to the sorting result to obtain a first predicted image.

[0082] S508: The FPGA compares the first predicted image with the first test image.

[0083] S509: Adjust the order of the second test RGB data in the first predicted image according to the order of the first test RGB data in the first test image so that the first predicted image is consistent with the first test image.

[0084] S510: For each second test RGB data, the FPGA determines the column where the second test RGB data is located in the adjusted first predicted image and determines the column as the second target column corresponding to the second test RGB data.

[0085] S511: Corresponding save the second target column and the first number of the first VBO signal line transmitting the second test RGB data of the column into the register.

[0086] S512: The host computer reads the correspondence saved in the register.

[0087] S513: The display screen displays the first test image and the first predicted image, and the technician verifies whether the corresponding relationship is correct according to the display.

[0088] S514: The technician writes the corresponding relationship into the program of the power-on configuration parameters of the MCU and powers on the FPGA again.

[0089] In order to enable the image to be correctly displayed on the display screen of the reference monitor, based on the above embodiments, in the embodiments of the present application, the method further includes:

[0090] Obtain the second preset number of the second VBO signal lines connecting the FPGA and the timing controller TCON that is saved, and group each column of RGB data in the target image according to the second preset number to determine each second transmission group;

[0091] Determine the second VBO signal line with the second number corresponding to each column of each second transmission group in the target image according to the corresponding relationship between the second number of the second VBO signal line and the column that is saved in advance;

[0092] Use the second VBO signal line with the second number corresponding to each column of RGB data in each second transmission group to send each column of RGB data in the target image to the TCON.

[0093] In the embodiments of the present application, the FPGA is also connected to the TCON and sends RGB data to the TCON, so that the TCON controls the display to display the image.

[0094] Specifically, in the embodiments of the present application, the FPGA obtains the second preset number of the second VBO signal lines connecting the FPGA and the TCON that is saved, and groups each column of RGB data in the received target image according to the second preset number to determine each second transmission group. Wherein, in the embodiments of the present application, the second preset number may be the same as or different from the first preset number.

[0095] Due to the design of the circuit board, the pin connection order between the FPGA and the TCON will be adjusted during the manufacturing process of the circuit board, which results in non-corresponding connections between the pins of the TCON and the FPGA. For example, pin 1 of the TCON should be connected to pin 1 of the FPGA, but during the manufacturing process, pin 1 of the TCON is connected to pin 3 of the FPGA. This further leads to the inconsistency between the image spliced by the TCON and the target image, reducing the accuracy of image transmission. Based on this, in the embodiments of the present application, the FPGA also stores the correspondence between the second number of the second VBO signal line and the column. According to this correspondence, the FPGA determines the second number corresponding to each column of each second transmission group in the target image, and uses the second VBO signal line corresponding to the second number of each column of RGB data in each second transmission group to send each column of RGB data in the target image to the TCON, so that the TCON can control the display screen to display the correct target image.

[0096] Figure 6 Schematic diagram of the internal structure of the FPGA provided by the embodiments of the present application. As shown in Figure 6 the figure, the FPGA includes a serial-to-parallel conversion and decoding module, a parallel-to-serial conversion and encoding module, a received data recombination module, a transmitted data recombination module, a data detection and comparison module, and a data reading and writing module. Among them, the serial-to-parallel conversion and decoding module is used to perform serial-to-parallel conversion of each column of RGB data, converting the serial signal of each column of RGB data sent by the SOC into a parallel digital signal; the parallel-to-serial conversion and encoding module is used to perform parallel-to-serial conversion of data, converting each column of RGB data from a parallel digital signal into a serial signal and sending it to the TCON for display; the received data recombination module is used to rearrange and combine each column of RGB data sent by the SOC to form a target image; the transmitted data recombination module is used to re-split the target image and send each split column of RGB data to the TCON; the image processing module is used to perform image processing on the image to achieve effects such as enhanced image quality; the data detection and comparison module is used to generate a test image and determine the correspondence between the number of the VBO signal line and the column; the data reading and writing module is used to receive the parameters configured by the MCU after power-on, perform parameter configuration, and receive the reading and writing of the internal data of the FPGA through the host computer.

[0097] In order to enable the FPGA to store the correspondence between the second number of the second VBO signal line and the column, thereby improving the accuracy of image transmission. On the basis of the above embodiments, in the embodiments of the present application, the process of determining the correspondence between the second number of the second VBO signal line and the column includes:

[0098] Send the third test RGB data of the generated second test image to the TCON, so that the TCON sorts according to the received third test RGB data to obtain a predicted image, and sends the predicted image to the SOC; wherein each column of the third test RGB data in the second test image is different, and the second test image contains a second preset number of columns.

[0099] Receive the fourth test RGB data of each column of pixel points of the predicted image sent by the SOC through the first VBO signal line.

[0100] For each column of the fourth test RGB data, determine the corresponding third target column of the fourth test RGB data in the second test image, and save the third target column corresponding to the second number of the second VBO signal line that transmits the fourth test RGB data of this column.

[0101] In the embodiment of the present application, the FPGA generates a second test image and sends each column of the third test RGB data of the second test image to the TCON. Among them, since the correspondence between the second number of the second VBO signal line and the column is applicable to all second transmission groups, in order to save transmission resources, in the embodiment of the present application, the second test image can be composed of one second transmission group, that is, the number of columns included in the second test image is the same as the number of second VBO signal lines.

[0102] Among them, since the RGB data sent by a certain pin number of the FPGA may not be the same column as the RGB data received by the same pin number of the TCON. For example, the pin numbered 1 of the FPGA is responsible for sending the first column RGB data of the second test image, but the RGB data received by the pin numbered 1 of the TCON is the third column of the second test image. Therefore, in the embodiment of the present application, each column of RGB data received by the TCON is called the fourth test RGB data. After the TCON receives each column of the third test RGB data, it will sort each column of the third test RGB data according to the order of the pins connected by each second VBO signal line to obtain a predicted image.

[0103] In order to enable the FPGA to determine whether pixel disorder occurs in the predicted image determined by the TCON, in the embodiment of the present application, the FPGA sends the second predicted image to the TCON, and after the TCON determines the predicted image, the TCON will also forward the predicted image to the FPGA. Among them, in order to make the predicted image received by the FPGA consistent with the predicted image determined by the TCON, in the embodiment of the present application, the TCON sends the predicted image to the SOC through the upper computer, and then the SOC sends it to the FPGA.

[0104] In an embodiment of the present application, after the FPGA receives the fourth test RGB data of each column through the host computer and the SOC, for the fourth test RGB data of each column, the FPGA determines the third target column corresponding to the fourth test data of this column in the predicted image, and stores the third target column corresponding to the second number of the second VBO signal line transmitting the fourth test RGB data of this column.

[0105] Specifically, in an embodiment of the present application, when the FPGA determines the third target column corresponding to the fourth test RGB data of each column, it can be determined in one or more of the following ways:

[0106] Method 1: For the fourth test RGB data of each column, according to the third test RGB data corresponding to each column of pixel points in the second test image, search for the third target column corresponding to the fourth test RGB data in the second test image.

[0107] Since the third test RGB data of each column in the second test image is different, for the fourth test RGB data of each column, the FPGA can search for the target third test RGB data with the same value as the fourth test RGB data in the second test image, and determine the column where the target third test RGB data is located as the third target column corresponding to the fourth test RGB data.

[0108] For example, there are 4 columns of third test RGB data in the second test image. For a certain column of fourth test RGB data, if the FPGA determines that the value of this column of fourth test RGB data is the same as the value of the third test RGB data in the third column of the second test image, then the FPGA determines that the third column is the third target column corresponding to the fourth test RGB data.

[0109] Method 2: The FPGA splices the fourth test RGB data transmitted by each second VBO signal line according to the corresponding relationship between the first number of the first VBO signal line and the column stored in advance, so that the FPGA restores the predicted image determined by the TCON. The FPGA compares the predicted image with the second test image, and adjusts the order of the fourth test RGB data in the predicted image according to the order of the third test RGB data in the second test image, so that the predicted image is consistent with the second test image. For the fourth test RGB data of each column, the FPGA determines the column where the fourth test RGB data is located in the adjusted predicted image, and determines this column as the third target column corresponding to the fourth test RGB data.

[0110] In addition, in the embodiments of the present application, after the TCON determines the predicted image, the TCON can also control the display screen to display the predicted image. A technician can obtain the second test image generated by the FPGA from the FPGA through an upper computer, and determine the correspondence between the second number of the second VBO signal line and the column according to the second test image and the predicted image. The technician writes the correspondence into the FPGA through the MCU.

[0111] In addition, when the FPGA generates the second test image, the second test image can also include two second transmission groups or multiple second transmission groups. Among them, in the embodiments of the present application, when the FPGA generates the second test image of two second transmission groups, it can first generate two sub-test images, namely the first sub-test image and the second sub-test image. The FPGA splices the first sub-test image and the second sub-test image to obtain the second test image. Among them, in order to improve the display effect of the image, the sub-test RGB data of one second transmission group in the first sub-test image is the RGB data corresponding to white pixel points, and the sub-test RGB data of the other second transmission group in the second sub-test image is the RGB data corresponding to black pixel points; the sub-test RGB data of the two second transmission groups in the second sub-test image is the same, but the sub-RGB data of different columns in the same second transmission group is different.

[0112] Figure 7 It is a schematic diagram of the internal structure of the data detection and comparison module of the FPGA provided by the embodiments of the present application. As shown in Figure 7 the figure, the internal data detection and comparison module includes a VBO RX test card generation module, a VBO RX test card extraction module, a VBO RX data comparison module, a VBO TX reference card generation module, a VBO TX detection card generation module, and a card splicing and combination module. Among them, the VBO RX test card generation module is used to generate the first test image, read the first test image to the PC through the upper computer, and send it to the SCO chip; the VBO RX test card extraction module is used to parse the received second test RGB data sent by the SOC and extract image recognition information; the VBO RX data comparison module is used to compare the second test RGB data and the first test RGB data generated by the VBO RX test card generation module, automatically identify the correspondence between the first number of the second VBO signal line of the FPGA and the column, and write the correspondence into the received data recombination module in the form of a register; the VBO TX reference card generation module is used to generate the first sub-test image; the VBO TX detection card generation module is used to generate the second sub-test image; the card splicing and combination module is used to splice the first sub-test image and the second sub-test image to obtain the second test image.

[0113] Figure 8 Schematic diagram of the second test images of two second transmission groups provided by an embodiment of the present application. As shown in the Figure 8 figure, the second test image is composed of two sub-test images, namely the first sub-test image and the second sub-test image. Among them, the sub-test RGB data of one second transmission group in the first sub-test image is the RGB data corresponding to white pixel points, and the sub-test RGB data of the other second transmission group in the second sub-test image is the RGB data corresponding to black pixel points; the sub-test RGB data of the two second transmission groups in the second sub-test image is the same, but the sub-RGB data of different columns of the same second transmission group is different.

[0114] Based on Figure 8 this, Figure 9 Schematic diagram of the predicted image corresponding to the second test image of two second transmission groups provided by an embodiment of the present application. As shown in the Figure 9 figure, each second transmission group of the predicted image is different from the second and third columns of each second transmission group of the first test image.

[0115] Figure 10 Schematic diagram of the determination process of the correspondence between the second number of the second VBO signal line and the column provided by an embodiment of the present application. As shown in the Figure 10 figure, this process includes:

[0116] S1001: The host computer sends a VBO TX signal line sequence debugging command to the FPGA.

[0117] S1002: The VBO TX reference card generation module of the FPGA generates the first sub-test image.

[0118] S1003: The VBO TX detection card generation module of the FPGA generates the second sub-test image.

[0119] S1004: The card splicing and combination module stitches the first sub-test image and the second sub-test image together to obtain the second test image.

[0120] S1005: The receiving SOC receives the fourth test RGB data of each column of pixels of the predicted image sent through the first VBO signal line.

[0121] S1006: For each column of the fourth test RGB data, determine the third target column corresponding to the fourth test RGB data of this column in the second test image, and save the correspondence between the third target column and the second number of the second VBO signal line transmitting the fourth test RGB data of this column.

[0122] In order to send RGB data to the TCON, based on the above embodiments, in the embodiments of the present application, sending each column of RGB data in the target image to the TCON through the second VBO signal lines corresponding to the second numbers of each column of RGB data in each second transmission group includes:

[0123] Sort each second transmission group according to the column of RGB data with the smallest sequence number included in each second transmission group; where the sequence number is the sorting of each column of RGB data in the target image;

[0124] According to the sorting result, for each second transmission group in turn, send each column of RGB data in the second transmission group to the TCON through the second VBO signal lines corresponding to the second numbers of each column of RGB data in the second transmission group.

[0125] In the embodiments of the present application, when the FPGA sends each column of RGB data in the target image to the TCON through the second VBO signal lines corresponding to the second numbers of each column of RGB data in each second transmission group, the FPGA sorts each second transmission group according to the column of RGB data with the smallest sequence number included in each second transmission group, so that the FPGA determines the sorting result as the transmission order of each column of RGB data in the corresponding second VBO signal lines in each second transmission group.

[0126] Specifically, according to the sorting result, for each second transmission group in turn, send each column of RGB data in the second transmission group to the TCON through the second VBO signal lines corresponding to the second numbers of each column of RGB data in the second transmission group.

[0127] Figure 11 The figure is a schematic structural diagram of an image processing device provided by an embodiment of the present application. The device includes:

[0128] A receiving module 1101, configured to receive each column of RGB data sent by a system-on-chip (SOC) through a first preset number of first VBO signal lines, and determine each column of RGB data included in each first transmission group;

[0129] A determining module 1102, configured to, for each first transmission group, determine the first target column where each column of RGB data in the first transmission group is located according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group and the pre-saved correspondence between the first number of the first VBO signal line and the column; where each first transmission group includes the first preset number of columns of RGB data; determine the target image according to the first target column where each column of RGB data in each first transmission group is located and the order of the first transmission group.

[0130] In a possible implementation manner, the determining module 1102 is specifically configured to, for each column of RGB data in the first transmission group, determine a target first VBO signal line corresponding to the column of RGB data; according to the corresponding relationship, determine the column corresponding to the target first number of the target first VBO signal line, and determine the column as the first target column where the column of RGB data is located.

[0131] In a possible implementation manner, the determining module 1102 is further configured to send the generated first test image to the SOC through the host computer, where each column of first test RGB data in the first test image is different, and the first test image includes a first preset number of columns; send a sending instruction for sending each column of RGB data to the SOC, and receive each column of second test RGB data sent by the SOC through the first preset number of first VBO signal lines; for each column of second test RGB data, determine a second target column corresponding to the column of second test RGB data in the first test image, and correspondingly save the second target column and the first number of the first VBO signal line that transmits the column of second test RGB data.

[0132] In a possible implementation manner, the determining module 1102 is further configured to determine the transmission order of each RGB data in the corresponding first VBO signal line; determine RGB data with the same transmission order as a first transmission group.

[0133] In a possible implementation manner, the determining module 1102 is further configured to obtain a second preset number of second VBO signal lines for connecting the FPGA to the timing controller TCON that are saved, and according to the second preset number, group each column of RGB data in the target image to determine each second transmission group; according to the corresponding relationship between the second number of the second VBO signal line and the column that is pre-saved, determine the second VBO signal line corresponding to the second number of each column in each second transmission group in the target image;

[0134] The device further includes:

[0135] A sending module 1103, configured to use the second VBO signal line corresponding to the second number of each column of RGB data in each second transmission group to send each column of RGB data in the target image to the TCON.

[0136] In a possible implementation manner, the determining module 1102 is further configured to send the third test RGB data of the generated second test image to the TCON, so that the TCON sorts the received third test RGB data to obtain a predicted image, and sends the predicted image to the SOC; wherein each column of the third test RGB data in the second test image is different, and the second test image includes a second preset number of columns; receive the fourth test RGB data of each column of pixel points of the predicted image sent by the SOC through the first VBO signal line; for each column of the fourth test RGB data, determine the third target column corresponding to the column of the fourth test RGB data in the second test image, and save the third target column in correspondence with the second number of the second VBO signal line transmitting the column of the fourth test RGB data.

[0137] In a possible implementation manner, the sending module 1103 is specifically configured to sort each second transmission group according to the column of RGB data with the smallest serial number included in each second transmission group; wherein the serial number is the sorting of each column of RGB data in the target image; according to the sorting result, for each second transmission group in sequence, send each column of RGB data in the second transmission group to the TCON according to the second VBO signal line corresponding to the second number of each column of RGB data in the second transmission group.

[0138] In an embodiment of the present application, the data transmission device is deployed in the FPGA of the reference monitor.

[0139] On the basis of the above embodiments, an embodiment of the present application further provides an electronic device. Figure 12 The following is a schematic structural diagram of an electronic device provided by an embodiment of the present application, as Figure 12 shown, including: a processor 1201, a communication interface 1202, a memory 1203, and a communication bus 1204, wherein the processor 1201, the communication interface 1202, and the memory 1203 complete mutual communication through the communication bus 1204;

[0140] The memory 1203 stores a computer program, and when the program is executed by the processor 1201, the processor 1201 is caused to execute the following steps:

[0141] Receive the RGB data of each column sent by the system-on-chip SOC through a first preset number of first VBO signal lines, and determine the RGB data of each column included in each first transmission group;

[0142] For each first transmission group, according to the first VBO signal lines corresponding to each column of RGB data included in the first transmission group and the correspondence between the first numbers of the first VBO signal lines and the columns pre - saved, determine the first target columns where each column of RGB data in the first transmission group is located; wherein, each first transmission group includes the first preset number of columns of RGB data.

[0143] According to the first target columns where each column of RGB data in each first transmission group is located and the order of the first transmission groups, determine the target image.

[0144] In a possible implementation manner, the processor is further configured to:

[0145] For each column of RGB data in the first transmission group, determine the target first VBO signal line corresponding to the column of RGB data; according to the correspondence, determine the column corresponding to the target first number of the target first VBO signal line, and determine the column as the first target column where the column of RGB data is located.

[0146] In a possible implementation manner, the processor is further configured to:

[0147] Send the generated first test image to the SOC through the host computer, where each column of first test RGB data in the first test image is different, and the first test image includes the first preset number of columns.

[0148] Send a sending instruction carrying each column of RGB data to the SOC, and receive each column of second test RGB data sent by the SOC through the first preset number of first VBO signal lines.

[0149] For each column of second test RGB data, determine the second target column corresponding to the column of second test RGB data in the first test image, and correspondingly save the second target column and the first number of the first VBO signal line transmitting the column of second test RGB data.

[0150] In a possible implementation manner, the processor is further configured to:

[0151] Determine the transmission order of each RGB data in the corresponding first VBO signal line.

[0152] Determine the RGB data with the same transmission order as a first transmission group.

[0153] In a possible implementation manner, the processor is further configured to:

[0154] Obtain the second preset quantity of the second VBO signal lines connecting the FPGA and the timing controller TCON that are saved, and group each column of RGB data in the target image according to the second preset quantity to determine each second transmission group;

[0155] Determine the second VBO signal line with the second number corresponding to each column in each second transmission group in the target image according to the corresponding relationship between the second number of the second VBO signal line and the column that is saved in advance;

[0156] Use the second VBO signal line with the second number corresponding to each column of RGB data in each second transmission group to send each column of RGB data in the target image to the TCON.

[0157] In a possible implementation manner, the processor is further configured to:

[0158] Send the third test RGB data of the generated second test image to the TCON, so that the TCON sorts according to the received third test RGB data to obtain a predicted image, and send the predicted image to the SOC; wherein each column of the third test RGB data in the second test image is different, and the second test image contains a second preset number of columns;

[0159] Receive the fourth test RGB data of each column of pixel points of the predicted image sent by the SOC through the first VBO signal line;

[0160] For each column of the fourth test RGB data, determine the third target column corresponding to the column of the fourth test RGB data in the second test image, and correspondingly save the third target column and the second number of the second VBO signal line that transmits the column of the fourth test RGB data.

[0161] In a possible implementation manner, the processor is further configured to:

[0162] Sort each second transmission group according to the column of RGB data with the smallest serial number included in each second transmission group; wherein, the serial number is the sorting of each column of RGB data in the target image;

[0163] According to the sorting result, for each second transmission group in turn, send each column of RGB data in the second transmission group to the TCON according to the second VBO signal line with the second number corresponding to each column of RGB data in the second transmission group.

[0164] Since the principle of the above electronic device for solving problems is similar to that of the image processing method, the implementation of the above electronic device can refer to the embodiments of the method, and the repeated parts will not be described again.

[0165] The communication bus mentioned in the above electronic device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. The communication interface 1202 is used for communication between the above electronic device and other devices. The memory may include a Random Access Memory (RAM), and may also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located far from the aforementioned processor.

[0166] The above-mentioned processor may be a general-purpose processor, including a central processing unit, a Network Processor (NP), etc.; it may also be a Digital Signal Processing (DSP), an application-specific integrated circuit, a field programmable gate array, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0167] Based on the above embodiments, the embodiment of the present invention further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program executable by a processor. When the program runs on the processor, the processor is caused to execute the following steps when executed:

[0168] Receive each column of RGB data sent by the system-on-chip (SOC) through the first preset number of first VBO signal lines, and determine each column of RGB data included in each first transmission group;

[0169] For each first transmission group, according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group, and the correspondence between the first number of the first VBO signal line and the column saved in advance, determine the first target column where each column of RGB data in the first transmission group is located; wherein, each first transmission group includes the first preset number of columns of RGB data;

[0170] Determine the target image according to the first target column where each column of RGB data in each first transmission group is located and the order of the first transmission group.

[0171] In a possible implementation manner, determining the first target column where each column of RGB data in the first transmission group is located according to the first VBO signal lines corresponding to each column of RGB data included in the first transmission group, and the corresponding relationship between the first numbers of the first VBO signal lines and columns saved in advance includes:

[0172] For each column of RGB data in the first transmission group, determine the target first VBO signal line corresponding to this column of RGB data; according to the corresponding relationship, determine the column corresponding to the target first number of the target first VBO signal line, and determine this column as the first target column where this column of RGB data is located.

[0173] In a possible implementation manner, the process of determining the corresponding relationship between the first numbers of the first VBO signal lines and columns includes:

[0174] Send the generated first test image to the SOC through the host computer, where each column of first test RGB data in the first test image is different, and the first test image contains a first preset number of columns;

[0175] Send a sending instruction for sending each column of RGB data to the SOC, and receive each column of second test RGB data sent by the SOC through the first preset number of first VBO signal lines;

[0176] For each column of second test RGB data, determine the second target column corresponding to this column of second test RGB data in the first test image, and correspondingly save the second target column and the first number of the first VBO signal line transmitting this column of second test RGB data.

[0177] In a possible implementation manner, the process of determining each first transmission group includes:

[0178] Determine the transmission order of each RGB data in the corresponding first VBO signal line;

[0179] Determine the RGB data with the same transmission order as a first transmission group.

[0180] In a possible implementation manner, the method further includes:

[0181] Obtain the second preset number of second VBO signal lines for connecting the FPGA and the timing controller TCON saved, and according to the second preset number, group each column of RGB data in the target image to determine each second transmission group;

[0182] Determine the second VBO signal lines corresponding to the second numbers of each column in each second transmission group in the target image according to the pre - saved correspondence between the second numbers of the second VBO signal lines and the columns;

[0183] Use the second VBO signal lines corresponding to the second numbers of each column of RGB data in each second transmission group to send each column of RGB data in the target image to the TCON.

[0184] In a possible implementation manner, the process of determining the correspondence between the second numbers of the second VBO signal lines and the columns includes:

[0185] Send the third test RGB data of the generated second test image to the TCON, so that the TCON sorts according to the received third test RGB data to obtain a predicted image, and sends the predicted image to the SOC; where each column of the third test RGB data in the second test image is different, and the second test image contains a second preset number of columns;

[0186] Receive the fourth test RGB data of each column of pixel points of the predicted image sent by the SOC through the first VBO signal line;

[0187] For each column of the fourth test RGB data, determine the third target column corresponding to this column of the fourth test RGB data in the second test image, and correspondingly save the third target column and the second number of the second VBO signal line transmitting this column of the fourth test RGB data.

[0188] In a possible implementation manner, the step of using the second VBO signal lines corresponding to the second numbers of each column of RGB data in each second transmission group to send each column of RGB data in the target image to the TCON includes:

[0189] Sort each second transmission group according to the column of RGB data with the smallest serial number included in each second transmission group; where the serial number is the sorting of each column of RGB data in the target image;

[0190] According to the sorting result, for each second transmission group in turn, send each column of RGB data in this second transmission group to the TCON according to the second VBO signal line corresponding to the second number of each column of RGB data in this second transmission group.

[0191] Since the principle of the above - mentioned computer - readable storage medium for solving problems is similar to that of the image - processing method, the implementation of the above - mentioned computer - readable storage medium can refer to the embodiments of the method, and the repeated parts will not be elaborated.

[0192] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0193] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for realizing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0194] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that realize the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0195] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for realizing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0196] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. An image processing method, applied to a field programmable gate array (FPGA), characterized in that The method includes: Receiving each column of RGB data sent by a system-on-chip (SOC) through a first preset number of first VBO signal lines, and determining each column of RGB data included in each first transmission group; For each first transmission group, according to the first VBO signal lines corresponding to each column of RGB data included in the first transmission group, and the pre-saved correspondence between the first numbers of the first VBO signal lines and columns, determining the first target column where each column of RGB data in the first transmission group is located; wherein, each first transmission group includes the first preset number of columns of RGB data; Determining a target image according to the first target column where each column of RGB data in each first transmission group is located and the order of the first transmission groups.

2. The method according to claim 1, wherein The determining the first target column where each column of RGB data in the first transmission group is located according to the first VBO signal lines corresponding to each column of RGB data included in the first transmission group, and the pre-saved correspondence between the first numbers of the first VBO signal lines and columns includes: For each column of RGB data in the first transmission group, determining the target first VBO signal line corresponding to the column of RGB data; according to the correspondence, determining the column corresponding to the target first number of the target first VBO signal line, and determining the column as the first target column where the column of RGB data is located.

3. The method according to claim 1, wherein The process of determining the correspondence between the first numbers of the first VBO signal lines and columns includes: Sending the generated first test image to the SOC through a host computer, where each column of first test RGB data in the first test image is different, and the first test image includes a first preset number of columns; Sending a transmission instruction for sending each column of RGB data to the SOC, and receiving each column of second test RGB data sent by the SOC through the first preset number of first VBO signal lines; For each column of second test RGB data, determining the second target column corresponding to the column of second test RGB data in the first test image, and correspondingly saving the second target column and the first number of the first VBO signal line transmitting the column of second test RGB data.

4. The method according to claim 1, wherein The process of determining each first transmission group includes: Determining the transmission order of each RGB data in the corresponding first VBO signal line; Determining the RGB data with the same transmission order as a first transmission group.

5. The method according to claim 1, characterized in that, The method further includes: Obtaining a second preset number of second VBO signal lines for connecting the field-programmable gate array (FPGA) to a timing controller (TCON) that is saved, and according to the second preset number, grouping each column of RGB data in the target image to determine each second transmission group; According to the pre-saved correspondence between the second numbers of the second VBO signal lines and columns, determining the second VBO signal lines with the second numbers corresponding to each column in each second transmission group in the target image; Using the second VBO signal lines with the second numbers corresponding to each column of RGB data in each second transmission group to send each column of RGB data in the target image to the TCON.

6. The method according to claim 5, characterized in that, The process of determining the correspondence between the second numbers of the second VBO signal lines and columns includes: Send the third test RGB data of the generated second test image to the TCON, so that the TCON sorts the received third test RGB data to obtain a predicted image and sends the predicted image to the SOC; wherein each column of the third test RGB data in the second test image is different, and the second test image contains a second preset number of columns. Receive the fourth test RGB data of each pixel point of the predicted image sent by the SOC through the first VBO signal line. For each column of the fourth test RGB data, determine the third target column corresponding to the column of the fourth test RGB data in the second test image, and store the third target column corresponding to the second number of the second VBO signal line that transmits the column of the fourth test RGB data.

7. The method according to claim 5, wherein Sending each column of RGB data in the target image to the TCON according to the second VBO signal line corresponding to the second number of each column of RGB data in each second transmission group includes: Sort each second transmission group according to the column of RGB data with the smallest serial number included in each second transmission group; wherein the serial number is the sorting of each column of RGB data in the target image. According to the sorting result, for each second transmission group in turn, send each column of RGB data in the second transmission group to the TCON according to the second VBO signal line corresponding to the second number of each column of RGB data in the second transmission group.

8. An image processing device is applied to a field programmable gate array (FPGA), and is characterized in that The device includes: A receiving module, configured to receive each column of RGB data sent by a system-on-chip (SOC) through a first preset number of first VBO signal lines, and determine each column of RGB data included in each first transmission group. A determining module, configured to, for each first transmission group, determine the first target column where each column of RGB data in the first transmission group is located according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group and the pre-stored correspondence between the first number of the first VBO signal line and the column; wherein each first transmission group includes the first preset number of columns of RGB data; determine the target image according to the first target column where each column of RGB data in each first transmission group is located and the order of the first transmission groups.

9. A reference monitor, characterized in that, The reference monitor includes an FPGA, and the FPGA is configured to execute the steps of the image processing method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, It stores a computer program, and when the computer program is executed by a processor, it implements the steps of the image processing method according to any one of claims 1-7.

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