A method for identifying a latch structure

Abstract

An embodiment of the present invention discloses a method for identifying a latch structure. The method includes: in a chip layout, finding a first N-type heavily doped region that is connected to a first input / output pad and is located in a P-type substrate; finding a first P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located in an N-well, and a second P-type heavily doped region that is located in the P-type substrate; finding a second N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located in the N-well; wherein the N-well is located on the P-type substrate; the region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well, and the P-type substrate is the identified latch structure.

Description

Technical Field

[0001] The present invention relates to a method for an ESD protection circuit of a semiconductor integrated circuit, and more particularly to a method for identifying a latch-up structure. Background Art

[0002] Reliability has become increasingly important for semiconductor products. Latch-up is a very important item in the reliability of semiconductor products. In a designed integrated circuit product, various latch-up paths may exist. Especially in the circuit connected to the input / output pad (IO PAD), it becomes very important to effectively detect these possible latch-up paths and check whether they are safe using existing design rules. Summary of the Invention

[0003] In view of this, an embodiment of the present invention provides a method for identifying a latch-up structure.

[0004] According to a first aspect of an embodiment of the present invention, a method for identifying a latch-up structure is provided. The method includes:

[0005] In a chip layout, find a first N-type heavily doped region that is connected to a first input / output pad and is located in a P-type substrate;

[0006] Find a first P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located in an N-well and a second P-type heavily doped region that is located in the P-type substrate;

[0007] Find a second N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located in the N-well; wherein the N-well is located on the P-type substrate;

[0008] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well, and the P-type substrate is the identified latch-up structure; or,

[0009] In a chip layout, find a first P-type heavily doped region that is connected to a first input / output pad and is located in an N-well;

[0010] Find a first N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located in the P-type substrate and a second N-type heavily doped region that is located in the N-well;

[0011] Find a second P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located in the P-type substrate; wherein the N-well is located on the P-type substrate;

[0012] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N well, and the P-type substrate is the identified latch structure.

[0013] In some embodiments, finding the first P-type heavily doped region adjacent to the first N-type heavily doped region and located in the N well and the second P-type heavily doped region located in the P-type substrate includes:

[0014] Taking the first N-type heavily doped region as the center and a preset distance as the radius, identifying the first P-type heavily doped region and the second P-type heavily doped region whose distances to the first N-type heavily doped region are less than the preset distance;

[0015] Finding the first N-type heavily doped region adjacent to the first P-type heavily doped region and located in the P-type substrate and the second N-type heavily doped region located in the N well includes:

[0016] Taking the first P-type heavily doped region as the center and a preset distance as the radius, identifying the first N-type heavily doped region and the second N-type heavily doped region whose distances to the first P-type heavily doped region are less than the preset distance.

[0017] In some embodiments, finding the first N-type heavily doped region connected to the first input / output pad and located in the P-type substrate includes:

[0018] Finding the first N-type heavily doped region directly or indirectly connected to the first input / output pad and located in the P-type substrate;

[0019] Finding the first P-type heavily doped region connected to the first input / output pad and located in the N well includes:

[0020] Finding the first P-type heavily doped region directly or indirectly connected to the first input / output pad and located in the N well.

[0021] According to the second aspect of the embodiments of the present invention, a method for identifying a latch structure is provided, characterized in that the method includes:

[0022] In the chip layout, finding the first N-type heavily doped region connected to the first input / output pad and located in the first N well;

[0023] Finding the first P-type heavily doped region adjacent to the first N-type heavily doped region and located in the second N well and the second P-type heavily doped region located in the P-type substrate;

[0024] Finding the second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the second N well; wherein the first N well and the second N well are both located on the P-type substrate;

[0025] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the first N well, the second N well, and the P-type substrate is the identified latch structure; or,

[0026] In the chip layout, find the first P-type heavily doped region that is connected to the first input / output pad and is located in the second N well;

[0027] Find the first N-type heavily doped region adjacent to the first P-type heavily doped region and located in the first N well, and the second N-type heavily doped region located in the second N well;

[0028] Find the second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the P-type substrate; wherein, both the first N well and the second N well are located on the P-type substrate;

[0029] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the first N well, the second N well, and the P-type substrate is the identified latch structure.

[0030] In some embodiments, finding the first P-type heavily doped region adjacent to the first N-type heavily doped region and located in the second N well and the second P-type heavily doped region located in the P-type substrate includes:

[0031] Taking the first N-type heavily doped region as the center and a preset distance as the radius, identify the first P-type heavily doped region and the second P-type heavily doped region whose distances to the first N-type heavily doped region are less than the preset distance;

[0032] Finding the first N-type heavily doped region adjacent to the first P-type heavily doped region and located in the first N well and the second N-type heavily doped region located in the second N well includes:

[0033] Taking the first P-type heavily doped region as the center and a preset distance as the radius, identify the first N-type heavily doped region and the second N-type heavily doped region whose distances to the first P-type heavily doped region are less than the preset distance.

[0034] In some embodiments, finding the first N-type heavily doped region that is connected to the first input / output pad and is located in the first N well includes:

[0035] Find the first N-type heavily doped region that is directly or indirectly connected to the first input / output pad and is located in the first N well;

[0036] Finding a first P-type heavily doped region that is connected to the first input / output pad and is located in the second N-well; including:

[0037] Finding a first P-type heavily doped region that is directly or indirectly connected to the first input / output pad and is located in the second N-well.

[0038] According to a third aspect of an embodiment of the present invention, a method for identifying a latch structure is provided, characterized in that the method includes:

[0039] In the chip layout, finding a first N-type heavily doped region that is connected to the first input / output pad and is located in the deep N-well;

[0040] Finding a first P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located in the second N-well, and a second P-type heavily doped region that is located in the P-type substrate;

[0041] Finding a second N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located in the second N-well; wherein the deep N-well is located in the first N-well, and the first N-well and the second N-well are both located on the P-type substrate;

[0042] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure; or,

[0043] In the chip layout, finding a first P-type heavily doped region that is connected to the first input / output pad and is located in the second N-well;

[0044] Finding a first N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located in the deep N-well, and a second N-type heavily doped region that is located in the second N-well;

[0045] Finding a second P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located in the P-type substrate; wherein the deep N-well is located in the first N-well, and the first N-well and the second N-well are both located on the P-type substrate;

[0046] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure.

[0047] In some embodiments, the finding a first P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located in the second N-well, and a second P-type heavily doped region that is located in the P-type substrate; includes:

[0048] Centered on the first N-type heavily doped region and with a preset distance as the radius, identify a first P-type heavily doped region and a second P-type heavily doped region whose distances to the first N-type heavily doped region are less than the preset distance;

[0049] The finding of a first N-type heavily doped region adjacent to the first P-type heavily doped region and located in the deep N-well and a second N-type heavily doped region located in the second N-well; includes:

[0050] Centered on the first P-type heavily doped region and with a preset distance as the radius, identify a first N-type heavily doped region and a second N-type heavily doped region whose distances to the first P-type heavily doped region are less than the preset distance.

[0051] In some embodiments, the finding of a first N-type heavily doped region connected to the first input / output pad and located in the deep N-well; includes:

[0052] Find a first N-type heavily doped region directly or indirectly connected to the first input / output pad and located in the deep N-well;

[0053] The finding of a first P-type heavily doped region connected to the first input / output pad and located in the second N-well;

[0054] Find a first P-type heavily doped region directly or indirectly connected to the first input / output pad and located in the second N-well.

[0055] According to the fourth aspect of the embodiments of the present invention, there is provided a method for identifying a latch structure, characterized in that the method includes:

[0056] In the chip layout, find a first P-type heavily doped region connected to the first input / output pad and located in the deep N-well;

[0057] Find a first N-type heavily doped region adjacent to the first P-type heavily doped region and located in the P-well and a second N-type heavily doped region located in the deep N-well;

[0058] Find a second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the P-well; wherein the P-well is located in the deep N-well, the deep N-well is located in the N-well, and the N-well is located on the P-type substrate;

[0059] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the N-well, and the P-type substrate is the identified latch structure; or,

[0060] In the chip layout, find the first N-type heavily doped region that is connected to the first input / output pad and is located within the P-well;

[0061] Find the first P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located within the deep N-well, and the second P-type heavily doped region that is located within the P-well;

[0062] Find the second N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located within the deep N-well; wherein, the P-well is located within the deep N-well, the deep N-well is located within the N-well, and the N-well is located on the P-type substrate;

[0063] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the N-well, and the P-type substrate is the identified latch structure.

[0064] In some embodiments, the finding of the first N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located within the P-well and the second N-type heavily doped region that is located within the deep N-well; includes:

[0065] Centering on the first P-type heavily doped region and with a preset distance as the radius, identify the first N-type heavily doped region and the second N-type heavily doped region whose distances to the first P-type heavily doped region are less than the preset distance;

[0066] The finding of the first P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located within the deep N-well and the second P-type heavily doped region that is located within the P-well; includes:

[0067] Centering on the first N-type heavily doped region and with a preset distance as the radius, identify the first P-type heavily doped region and the second P-type heavily doped region whose distances to the first N-type heavily doped region are less than the preset distance.

[0068] In some embodiments,

[0069] The finding of the first P-type heavily doped region that is connected to the first input / output pad and is located within the deep N-well; includes:

[0070] Find the first P-type heavily doped region that is directly or indirectly connected to the first input / output pad and is located within the deep N-well;

[0071] The finding of the first N-type heavily doped region that is connected to the first input / output pad and is located within the P-well; includes:

[0072] Find the first N-type heavily doped region that is directly or indirectly connected to the first input / output pad and is located within the P-well.

[0073] According to a fifth aspect of an embodiment of the present invention, there is provided a method for identifying a latch structure, characterized in that the method includes:

[0074] In the chip layout, find a first P-type heavily doped region that is connected to the first input / output pad and is located in the P-well.

[0075] Find a first N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located in the P-type substrate, and a second N-type heavily doped region that is located in the N-well.

[0076] Find a second P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located in the P-type substrate; wherein, the P-well is located in the deep N-well, the deep N-well is located in the N-well, and the N-well is located on the P-type substrate.

[0077] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the N-well, and the P-type substrate is the identified latch structure; or,

[0078] In the chip layout, find a first N-type heavily doped region that is connected to the first input / output pad and is located in the P-type substrate.

[0079] Find a first P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located in the P-well, and a second P-type heavily doped region that is located in the P-type substrate.

[0080] Find a second N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located in the N-well; wherein, the P-well is located in the deep N-well, the deep N-well is located in the N-well, and the N-well is located on the P-type substrate.

[0081] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the N-well, and the P-type substrate is the identified latch structure.

[0082] In some embodiments, the step of finding a first N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located in the P-type substrate, and a second N-type heavily doped region that is located in the N-well includes:

[0083] Taking the first P-type heavily doped region as the center and a preset distance as the radius, identify a first N-type heavily doped region and a second N-type heavily doped region whose distances to the first P-type heavily doped region are less than the preset distance.

[0084] Finding a first P-type heavily doped region adjacent to the first N-type heavily doped region and located within the P-well, and a second P-type heavily doped region located within the P-type substrate; including:

[0085] Centering on the first N-type heavily doped region and with a preset distance as the radius, identifying a first P-type heavily doped region and a second P-type heavily doped region whose distances to the first N-type heavily doped region are less than the preset distance.

[0086] In some embodiments, finding a first P-type heavily doped region connected to the first input / output pad and located within the P-well; including:

[0087] Finding a first P-type heavily doped region directly or indirectly connected to the first input / output pad and located within the P-well;

[0088] Finding a first N-type heavily doped region connected to the first input / output pad and located within the P-type substrate; including:

[0089] Finding a first N-type heavily doped region directly or indirectly connected to the first input / output pad and located within the P-type substrate.

[0090] According to a sixth aspect of an embodiment of the present invention, there is provided a method for identifying a latch structure, characterized in that the method includes:

[0091] In the chip layout, finding a first P-type heavily doped region connected to the first input / output pad and located within the P-well;

[0092] Finding a first N-type heavily doped region adjacent to the first P-type heavily doped region and located within the second N-well, and a second N-type heavily doped region located within the first N-well;

[0093] Finding a second P-type heavily doped region adjacent to the first N-type heavily doped region and located within the P-type substrate; wherein the P-well is located within the deep N-well, the deep N-well is located within the first N-well, and both the first N-well and the second N-well are located on the P-type substrate;

[0094] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure; or,

[0095] In the chip layout, finding a first N-type heavily doped region connected to the first input / output pad and located within the second N-well;

[0096] Find a first P-type heavily doped region adjacent to the first N-type heavily doped region and located within the P-well, and a second P-type heavily doped region located within the P-type substrate;

[0097] Find a second N-type heavily doped region adjacent to the first P-type heavily doped region and located within the first N-well; wherein, the P-well is located within the deep N-well, the deep N-well is located within the first N-well, and both the first N-well and the second N-well are located on the P-type substrate;

[0098] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure.

[0099] In some embodiments, the finding of a first N-type heavily doped region adjacent to the first P-type heavily doped region and located within the second N-well and a second N-type heavily doped region located within the first N-well includes:

[0100] Centering on the first P-type heavily doped region and with a preset distance as the radius, identify a first N-type heavily doped region and a second N-type heavily doped region whose distances to the first P-type heavily doped region are less than the preset distance;

[0101] The finding of a first P-type heavily doped region adjacent to the first N-type heavily doped region and located within the P-well and a second P-type heavily doped region located within the P-type substrate includes:

[0102] Centering on the first N-type heavily doped region and with a preset distance as the radius, identify a first P-type heavily doped region and a second P-type heavily doped region whose distances to the first N-type heavily doped region are less than the preset distance.

[0103] In some embodiments, the finding of a first P-type heavily doped region connected to the first input / output pad and located within the P-well includes:

[0104] Find a first P-type heavily doped region directly or indirectly connected to the first input / output pad and located within the P-well;

[0105] The finding of a first N-type heavily doped region connected to the first input / output pad and located within the second N-well includes:

[0106] Find a first N-type heavily doped region directly or indirectly connected to the first input / output pad and located within the second N-well.

[0107] According to a seventh aspect of the embodiments of the present invention, there is provided a method for identifying a latch structure, characterized in that the method includes:

[0108] In the chip layout, find the first P-type heavily doped region that is connected to the first input / output pad and is located within the P-well;

[0109] Find the first N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located within the second deep N-well, and the second N-type heavily doped region that is located within the first N-well;

[0110] Find the second P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located within the P-type substrate; wherein, the P-well is located within the first deep N-well, the first deep N-well is located within the first N-well, the second deep N-well is located within the second N-well, and both the first N-well and the second N-well are located on the P-type substrate;

[0111] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the first deep N-well, the second deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure; or,

[0112] In the chip layout, find the first N-type heavily doped region that is connected to the first input / output pad and is located within the second deep N-well;

[0113] Find the first P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located within the P-well, and the second P-type heavily doped region that is located within the P-type substrate;

[0114] Find the second N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located within the first N-well; wherein, the P-well is located within the first deep N-well, the first deep N-well is located within the first N-well, the second deep N-well is located within the second N-well, and both the first N-well and the second N-well are located on the P-type substrate;

[0115] The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the first deep N-well, the second deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure.

[0116] In some embodiments, the step of finding the first N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located within the second deep N-well, and the second N-type heavily doped region that is located within the first N-well; includes:

[0117] Taking the first P-type heavily doped region as the center and a preset distance as the radius, identify the first N-type heavily doped region and the second N-type heavily doped region whose distances to the first P-type heavily doped region are less than the preset distance;

[0118] Finding a first P-type heavily doped region adjacent to the first N-type heavily doped region and located in the P-well, and a second P-type heavily doped region located in the P-type substrate; including:

[0119] Centering on the first N-type heavily doped region and with a preset distance as the radius, identifying a first P-type heavily doped region and a second P-type heavily doped region whose distances to the first N-type heavily doped region are less than the preset distance.

[0120] In some embodiments, finding a first P-type heavily doped region connected to the first input / output pad and located in the P-well; including:

[0121] Finding a first P-type heavily doped region directly or indirectly connected to the first input / output pad and located in the P-well;

[0122] Finding a first N-type heavily doped region connected to the first input / output pad and located in the second N-well; including:

[0123] Finding a first N-type heavily doped region directly or indirectly connected to the first input / output pad and located in the second N-well.

[0124] In the embodiments of the present invention, by finding a first N-type heavily doped region or a first P-type heavily doped region connected to the first input / output pad, and respectively finding other P-type or N-type heavily doped regions through the first N-type heavily doped region or the first P-type heavily doped region, thus, the latch structure connected to the first input / output pad is identified, and accordingly, the corresponding design rules can be used to check whether it is safe to ensure the reliability of the device. Brief Description of the Drawings

[0125] Figure 1a It is a schematic flowchart of the method for identifying the latch structure provided by the embodiment of the present invention;

[0126] Figure 1b It is a schematic flowchart of the method for identifying the latch structure provided by another embodiment of the present invention;

[0127] Figure 1c It is a top view of a latch structure provided by the embodiment of the present invention;

[0128] Figure 1d It is a cross-sectional view of a latch structure provided by the embodiment of the present invention;

[0129] Figure 1e It is a cross-sectional view of a latch structure provided by another embodiment of the present invention;

[0130] Figure 2a It is a schematic flowchart of the method for identifying the latch structure provided by the embodiment of the present invention;

[0131] Figure 2b Schematic flow chart of the latch structure identification method provided by another embodiment of the present invention;

[0132] Figure 2c Top view of a latch structure provided by an embodiment of the present invention;

[0133] Figure 2d Cross-sectional view of a latch structure provided by an embodiment of the present invention;

[0134] Figure 2e Cross-sectional view of a latch structure provided by another embodiment of the present invention;

[0135] Figure 3a Schematic flow chart of the latch structure identification method provided by an embodiment of the present invention;

[0136] Figure 3b Schematic flow chart of the latch structure identification method provided by another embodiment of the present invention;

[0137] Figure 3c Top view of a latch structure provided by an embodiment of the present invention;

[0138] Figure 3d Cross-sectional view of a latch structure provided by an embodiment of the present invention;

[0139] Figure 3e Cross-sectional view of a latch structure provided by another embodiment of the present invention;

[0140] Figure 4a Schematic flow chart of the latch structure identification method provided by an embodiment of the present invention;

[0141] Figure 4b Schematic flow chart of the latch structure identification method provided by another embodiment of the present invention;

[0142] Figure 4c Top view of a latch structure provided by an embodiment of the present invention;

[0143] Figure 4d Cross-sectional view of a latch structure provided by an embodiment of the present invention;

[0144] Figure 4e Cross-sectional view of a latch structure provided by another embodiment of the present invention;

[0145] Figure 5a Schematic flow chart of the latch structure identification method provided by an embodiment of the present invention;

[0146] Figure 5b Schematic flow chart of the latch structure identification method provided by another embodiment of the present invention;

[0147] Figure 5c Top view of a latch structure provided by an embodiment of the present invention;

[0148] Figure 5d Cross-sectional view of a latch structure provided by an embodiment of the present invention;

[0149] Figure 5e Cross-sectional view of a latch structure provided by another embodiment of the present invention;

[0150] Figure 6a Schematic flowchart of a method for identifying a latch structure provided by an embodiment of the present invention;

[0151] Figure 6b Schematic flowchart of a method for identifying a latch structure provided by another embodiment of the present invention;

[0152] Figure 6c Top view of a latch structure provided by an embodiment of the present invention;

[0153] Figure 6d Cross-sectional view of a latch structure provided by an embodiment of the present invention;

[0154] Figure 6e Cross-sectional view of a latch structure provided by another embodiment of the present invention;

[0155] Figure 7a Schematic flowchart of a method for identifying a latch structure provided by an embodiment of the present invention;

[0156] Figure 7b Schematic flowchart of a method for identifying a latch structure provided by another embodiment of the present invention;

[0157] Figure 7c Top view of a latch structure provided by an embodiment of the present invention;

[0158] Figure 7d Cross-sectional view of a latch structure provided by an embodiment of the present invention;

[0159] Figure 7e Cross-sectional view of a latch structure provided by another embodiment of the present invention.

[0160] Explanation of reference numerals:

[0161] 11, 21, 31, 42, 52, 62, 72 - First N-type heavily doped region;

[0162] 12, 22, 32, 41, 51, 61, 71 - First P-type heavily doped region;

[0163] 13, 23, 33, 44, 54, 64, 74 - Second P-type heavily doped region;

[0164] 14, 24, 34, 43, 53, 63, 73 - Second N-type heavily doped region;

[0165] 15, 25, 35, 45, 55, 65, 75 - P-type substrate;

[0166] 16, 48, 58 - N-well;

[0167] 46, 56, 66, 76 - P-well;

[0168] 36, 47, 57, 67 - Deep N-well;

[0169] 77 - First deep N-well;

[0170] 78 - Second deep N-well;

[0171] 26, 37, 68, 79 - First N-well;

[0172] 27, 38, 69, 80 - Second N-well. Detailed implementation manners

[0173] The exemplary embodiments disclosed in the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present invention disclosed can be completely conveyed to those skilled in the art.

[0174] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some well-known technical features are not described in order to avoid confusion with the present invention; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0175] In the drawings, for clarity, the dimensions of layers, regions, elements and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0176] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer or portion discussed below may be denoted as the second element, component, region, layer or portion. And when discussing the second element, component, region, layer or portion, it does not imply that a first element, component, region, layer or portion necessarily exists in the present invention.

[0177] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0178] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0179] To thoroughly understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution of the present invention. The preferred embodiments of the present invention are described in detail below. However, in addition to these detailed descriptions, the present invention may have other implementation manners.

[0180] In current integrated circuits, the identification and inspection of parasitic latch-up paths can ensure that the integrated circuit products do not fail due to latch-up, thereby ensuring the reliability of the products. However, there is often no reliable, effective, and comprehensive method for identifying and inspecting parasitic latch-up paths, which poses a major challenge to the prevention of latch-up.

[0181] The following will specifically illustrate the method for identifying the latch-up structure provided by the present invention through specific embodiments. Figures 1a - 7e A total of 7 methods for identifying the latch-up structure are shown. For different latch-up structures, the positions of the first N-type heavily doped region, the first P-type heavily doped region, the second N-type heavily doped region, and the second P-type heavily doped region are different. It should be noted that Figures 1a - 7e the P-type heavily doped region is abbreviated as P+, the N-type heavily doped region is abbreviated as N+, the first input / output pad is abbreviated as IO, the ground pad is abbreviated as VSS, and the power supply pad is abbreviated as VDD.

[0182] Figure 1a The flowchart of the method for identifying the latch-up structure provided by the embodiments of the present invention is shown as follows. As shown in the figure, the method includes the following steps:

[0183] Step 101a: In the chip layout, find the first N-type heavily doped region that is connected to the first input / output pad and is located in the P-type substrate.

[0184] Step 102a: Find the first P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located in the N-well, and the second P-type heavily doped region that is located in the P-type substrate.

[0185] Step 103a: Find the second N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located in the N-well; wherein, the N-well is located on the P-type substrate; the region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well, and the P-type substrate is the identified latch-up structure.

[0186] The following will further illustrate in detail the method for identifying the latch-up structure provided by the embodiments of the present invention in combination with specific embodiments.

[0187] Figure 1c The top view of a latch-up structure provided by the embodiments of the present invention. Figure 1d The cross-sectional view of a latch-up structure provided by the embodiments of the present invention.

[0188] Before performing step 101a, first find the first input / output pad, which includes pads such as data signal pads (DQ PAD) or address pads (CA PAD).

[0189] Next, as Figure 1d shown, perform step 101a. In the chip layout, find the first N-type heavily doped region 11 that is connected to the first input / output pad and is located within the P-type substrate 15.

[0190] In one embodiment, finding the first N-type heavily doped region 11 that is connected to the first input / output pad and is located within the P-type substrate 15 includes:

[0191] finding the first N-type heavily doped region 11 that is directly or indirectly connected to the first input / output pad and is located within the P-type substrate 15.

[0192] Here, finding the first N-type heavily doped region 11 that is directly connected to the first input / output pad means that there is a direct connection between the first input / output pad and the first N-type heavily doped region 11 without passing through other devices.

[0193] Finding the first N-type heavily doped region 11 that is indirectly connected to the first input / output pad means that the first input / output pad is connected to the first N-type heavily doped region 11 through a high current conducting path. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first N-type heavily doped region 11 through a reverse diode.

[0194] Next, perform step 102a to find the first P-type heavily doped region 12 that is adjacent to the first N-type heavily doped region 11 and is located within the N-well 16, and the second P-type heavily doped region 13 that is located within the P-type substrate 15.

[0195] In this embodiment, the first P-type heavily doped region 12 is connected to the power supply pad, and the second P-type heavily doped region 13 is connected to the ground pad.

[0196] The first P-type heavily doped region 12 can be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a high current conducting path. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0197] The second P-type heavily doped region 13 can be directly or indirectly connected to the ground pad. The indirect connection includes being connected through a high current conducting path. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0198] In one embodiment, finding the first P-type heavily doped region 12 adjacent to the first N-type heavily doped region 11 and located in the N well 16, and the second P-type heavily doped region 13 located in the P-type substrate 15; includes: taking the first N-type heavily doped region 11 as the center and a preset distance as the radius, identifying the first P-type heavily doped region 12 and the second P-type heavily doped region 13 whose distances to the first N-type heavily doped region 11 are less than the preset distance. Here, the preset distance can be obtained according to the design rules of the chip layout.

[0199] Next, perform step 103a to find the second N-type heavily doped region 14 adjacent to the first P-type heavily doped region 12 and located in the N well 16; wherein, the N well 16 is located on the P-type substrate 15; the region formed by the first P-type heavily doped region 12, the first N-type heavily doped region 11, the second P-type heavily doped region 13, the second N-type heavily doped region 14, the N well 16, and the P-type substrate 15 is the identified latch structure.

[0200] In this embodiment, the second N-type heavily doped region 14 is connected to the power supply pad.

[0201] The second N-type heavily doped region 14 is directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0202] Finding the second N-type heavily doped region 14 adjacent to the first P-type heavily doped region 12 and located in the N well 16 includes: taking the first P-type heavily doped region 12 as the center and a preset distance as the radius, identifying the second N-type heavily doped region 14 whose distance to the first P-type heavily doped region 12 is less than the preset distance.

[0203] In one embodiment, as Figure 1c shown, there is a first distance L1 between the second P-type heavily doped region 13 and the first N-type heavily doped region 11, a second distance L2 between the first N-type heavily doped region 11 and the first P-type heavily doped region 12, and a third distance L3 between the first P-type heavily doped region 12 and the second N-type heavily doped region 14.

[0204] Taking the first N-type heavily doped region 11 as the center and a preset distance as the radius, identifying the first P-type heavily doped region 12 and the second P-type heavily doped region 13 whose distances to the first N-type heavily doped region 11 are less than the preset distance; specifically includes: both the second distance and the first distance are less than the preset distance.

[0205] Figure 1bSchematic flowchart of the latch structure identification method provided by another embodiment of the present invention. As shown in the figure, the method includes the following steps:

[0206] Step 101b: In the chip layout, find the first P-type heavily doped region that is connected to the first input / output pad and is located in the N-well;

[0207] Step 102b: Find the first N-type heavily doped region located in the P-type substrate and the second N-type heavily doped region located in the N-well that are adjacent to the first P-type heavily doped region;

[0208] Step 103b: Find the second P-type heavily doped region located in the P-type substrate that is adjacent to the first N-type heavily doped region; wherein, the N-well is located on the P-type substrate; the region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well, and the P-type substrate is the identified latch structure.

[0209] The following further elaborates on the latch structure identification method provided by the embodiments of the present invention in combination with specific embodiments.

[0210] Figure 1e Cross-sectional view of a latch structure provided by another embodiment of the present invention.

[0211] Before performing step 101b, first find the first input / output pad, and the first input / output pad includes pads such as data signal pads (DQ PAD) or address pads (CA PAD).

[0212] Next, as Figure 1e shown, perform step 101b. In the chip layout, find the first P-type heavily doped region 12 that is connected to the first input / output pad and is located in the N-well 16.

[0213] In one embodiment, the finding of the first P-type heavily doped region 12 that is connected to the first input / output pad and is located in the N-well 16 includes:

[0214] Find the first P-type heavily doped region 12 that is directly or indirectly connected to the first input / output pad and is located in the N-well 16.

[0215] Here, finding the first P-type heavily doped region 12 that is directly connected to the first input / output pad means that there is a direct connection between the first input / output pad and the first P-type heavily doped region 12 without passing through other devices.

[0216] Find the first P-type heavily doped region 12 that is indirectly connected to the first input / output pad, which means the first input / output pad is connected to the first P-type heavily doped region 12 through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first P-type heavily doped region 12 through a forward diode.

[0217] Next, perform step 102b to find the first N-type heavily doped region 11 located in the P-type substrate 15 and the second N-type heavily doped region 14 located in the N-well 16 that are adjacent to the first P-type heavily doped region 12.

[0218] In this embodiment, the first N-type heavily doped region 11 is connected to the ground pad, and the second N-type heavily doped region 14 is connected to the power supply pad.

[0219] The first N-type heavily doped region 11 can be directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0220] The second N-type heavily doped region 14 can be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0221] In an embodiment, finding the first N-type heavily doped region 11 located in the P-type substrate 15 and the second N-type heavily doped region 14 located in the N-well that are adjacent to the first P-type heavily doped region 12 includes: taking the first P-type heavily doped region 12 as the center and a preset distance as the radius, identifying the first N-type heavily doped region 11 and the second N-type heavily doped region 14 whose distances to the first P-type heavily doped region 12 are less than the preset distance.

[0222] Next, perform step 103b to find the second P-type heavily doped region 13 located in the P-type substrate 15 that is adjacent to the first N-type heavily doped region 11; wherein the N-well 16 is located on the P-type substrate 15; the region formed by the first P-type heavily doped region 12, the first N-type heavily doped region 11, the second P-type heavily doped region 13, the second N-type heavily doped region 14, the N-well 16, and the P-type substrate 15 is the identified latch structure.

[0223] In this embodiment, the second P-type heavily doped region 13 is connected to the ground pad.

[0224] The second P-type heavily doped region 13 is directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0225] In one embodiment, finding the second P-type heavily doped region 13 that is adjacent to the first N-type heavily doped region 11 and is located within the P-type substrate 15 includes: taking the first N-type heavily doped region 11 as the center and a preset distance as the radius, identifying the second P-type heavily doped region 13 whose distance to the first N-type heavily doped region 11 is less than the preset distance.

[0226] In one embodiment, as Figure 1c shown, there is a first distance L1 between the second P-type heavily doped region 13 and the first N-type heavily doped region 11, a second distance L2 between the first N-type heavily doped region 11 and the first P-type heavily doped region 12, and a third distance L3 between the first P-type heavily doped region 12 and the second N-type heavily doped region 14.

[0227] Taking the first P-type heavily doped region 12 as the center and a preset distance as the radius, identifying the first N-type heavily doped region 11 and the second N-type heavily doped region 14 whose distances to the first P-type heavily doped region 12 are less than the preset distance specifically includes: both the second distance and the third distance are less than the preset distance.

[0228] Further, as Figure 1d and 1e shown, the N-well 16, the P-type substrate 15, and the first N-type heavily doped region 11 form a first parasitic NPN transistor T1. The first P-type heavily doped region 12, the N-well 16, and the P-type substrate 15 form a first parasitic PNP transistor T2.

[0229] The P-type substrate 15 has a first parasitic resistance R PW , the first end of the first parasitic resistance R PW is connected to the second P-type heavily doped region 13, and the second end of the first parasitic resistance R PW is connected to the base of the first parasitic NPN transistor T1.

[0230] The N-well 16 has a second parasitic resistance R NW , the first end of the second parasitic resistance R NW is connected to the second N-type heavily doped region 14, and the second end of the second parasitic resistance R NW is connected to the base of the first parasitic PNP transistor T2.

[0231] The principle of latch - up effect generation in the latch structure is described below: Specifically, T2 is a vertical PNP transistor with an N - well as the base, and the gain from the base to the collector can reach dozens of times. T1 is a lateral NPN transistor with a P - type substrate as the base, and the gain to the collector can reach dozens of times. R NW is the parasitic resistance of the N - well, and R PW is the parasitic resistance of the P - type substrate.

[0232] The above four components, T1, T2, R NW and R PW constitute a thyristor circuit. When there is no external interference and no triggering occurs, the two transistors are in the cut - off state, and the collector current is composed of the reverse leakage current from C - B, with a very small current gain. At this time, the latch - up effect will not occur. When the collector current of one of the transistors suddenly increases to a certain value due to external interference, it will feedback to the other transistor, causing the two transistors to turn on due to triggering (usually, the PNP is easier to trigger). A low - resistance path is formed between the power pad VDD and the ground pad VSS. After that, even if the external interference disappears, due to the positive feedback formed between the two transistors, there will still be leakage between the power pad VDD and the ground pad VSS, that is, the locked state. The latch - up effect is thus generated.

[0233] Figure 2a FIG. is a schematic flow chart of the method for identifying the latch structure provided by the embodiment of the present invention. As shown in the figure, the method includes the following steps:

[0234] Step 201a: In the chip layout, find the first N - type heavily - doped region that is connected to the first input / output pad and is located in the first N - well;

[0235] Step 202a: Find the first P - type heavily - doped region that is adjacent to the first N - type heavily - doped region and is located in the second N - well, and the second P - type heavily - doped region that is located in the P - type substrate;

[0236] Step 203a: Find the second N - type heavily - doped region that is adjacent to the first P - type heavily - doped region and is located in the second N - well; wherein, the first N - well and the second N - well are both located on the P - type substrate; the region composed of the first P - type heavily - doped region, the first N - type heavily - doped region, the second P - type heavily - doped region, the second N - type heavily - doped region, the first N - well, the second N - well, and the P - type substrate is the identified latch structure.

[0237] The method for identifying the latch structure provided by the embodiment of the present invention will be further described in detail below with specific embodiments.

[0238] Figure 2c FIG. is a top - view of a latch structure provided by the embodiment of the present invention; Figure 2dA cross-sectional view of a latch structure provided by an embodiment of the present invention.

[0239] Before performing step 201a, first find the first input / output pad, and the first input / output pad includes pads such as data signal pads (DQ PAD) or address pads (CA PAD).

[0240] Next, as Figure 2d shown, perform step 201a. In the chip layout, find the first N-type heavily doped region 21 that is connected to the first input / output pad and is located in the first N-well 26.

[0241] In one embodiment, the finding of the first N-type heavily doped region 21 that is connected to the first input / output pad and is located in the first N-well 26 includes:

[0242] Find the first N-type heavily doped region 21 that is directly or indirectly connected to the first input / output pad and is located in the first N-well 26.

[0243] Here, finding the first N-type heavily doped region 21 that is directly connected to the first input / output pad means that the first input / output pad is directly connected to the first N-type heavily doped region 21 without passing through other devices.

[0244] Finding the first N-type heavily doped region 21 that is indirectly connected to the first input / output pad means that the first input / output pad is connected to the first N-type heavily doped region 21 through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first N-type heavily doped region 21 through a reverse diode.

[0245] Next, perform step 202a to find the first P-type heavily doped region 22 that is adjacent to the first N-type heavily doped region 21 and is located in the second N-well 27 and the second P-type heavily doped region 23 that is located in the P-type substrate 25.

[0246] In this embodiment, the first P-type heavily doped region 22 is connected to the power supply pad, and the second P-type heavily doped region 23 is connected to the ground pad.

[0247] The first P-type heavily doped region 22 can be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0248] The second P-type heavily doped region 23 can be directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0249] In one embodiment, finding the first P-type heavily doped region 22 adjacent to the first N-type heavily doped region 21 and located in the second N-well 27, and the second P-type heavily doped region 23 located in the P-type substrate 25 includes: centering on the first N-type heavily doped region 21 and using a preset distance as the radius, identifying the first P-type heavily doped region 22 and the second P-type heavily doped region 23 whose distances to the first N-type heavily doped region 21 are less than the preset distance.

[0250] Next, perform step 203a to find the second N-type heavily doped region 24 adjacent to the first P-type heavily doped region 22 and located in the second N-well 27; wherein, the first N-well 26 and the second N-well 27 are both located on the P-type substrate 25; the region formed by the first P-type heavily doped region 22, the first N-type heavily doped region 21, the second P-type heavily doped region 23, the second N-type heavily doped region 24, the first N-well 26, the second N-well 27, and the P-type substrate 25 is the identified latch structure.

[0251] In this embodiment, the second N-type heavily doped region 24 is connected to the power supply pad.

[0252] The second N-type heavily doped region 24 is directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0253] Finding the second N-type heavily doped region 24 adjacent to the first P-type heavily doped region 22 and located in the second N-well 27; includes: centering on the first P-type heavily doped region 22 and using a preset distance as the radius, identifying the second N-type heavily doped region 24 whose distance to the first P-type heavily doped region 22 is less than the preset distance.

[0254] In one embodiment, as Figure 2c shown, there is a first distance L1 between the second P-type heavily doped region 23 and the first N-type heavily doped region 21, a second distance L2 between the first N-type heavily doped region 21 and the first P-type heavily doped region 22, and a third distance L3 between the first P-type heavily doped region 22 and the second N-type heavily doped region 24.

[0255] Centering on the first N-type heavily doped region 21 and using a preset distance as the radius, identifying the first P-type heavily doped region 22 and the second P-type heavily doped region 23 whose distances to the first N-type heavily doped region 21 are less than the preset distance; specifically includes: both the second distance and the first distance are less than the preset distance.

[0256] Figure 2bSchematic flowchart of the method for identifying a latch structure provided in another embodiment of the present invention. As shown in the figure, the method includes the following steps:

[0257] Step 201b: In the chip layout, find the first P-type heavily doped region that is connected to the first input / output pad and is located in the second N-well.

[0258] Step 202b: Find the first N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located in the first N-well, and the second N-type heavily doped region that is located in the second N-well.

[0259] Step 203b: Find the second P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located in the P-type substrate; wherein, the first N-well and the second N-well are both located on the P-type substrate; the region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the first N-well, the second N-well, and the P-type substrate is the identified latch structure.

[0260] The following further elaborates on the method for identifying a latch structure provided in the embodiments of the present invention with reference to specific embodiments.

[0261] Figure 2e Cross-sectional view of a latch structure provided in another embodiment of the present invention.

[0262] Before performing step 201b, first find the first input / output pad, and the first input / output pad includes pads such as data signal pads (DQ PAD) or address pads (CA PAD).

[0263] Then, as Figure 2e shown, perform step 201b. In the chip layout, find the first P-type heavily doped region 22 that is connected to the first input / output pad and is located in the second N-well 27.

[0264] In one embodiment, the finding of the first P-type heavily doped region 22 that is connected to the first input / output pad and is located in the second N-well 27 includes:

[0265] Find the first P-type heavily doped region 22 that is directly or indirectly connected to the first input / output pad and is located in the second N-well 27.

[0266] Here, finding the first P-type heavily doped region 22 that is directly connected to the first input / output pad means that the first input / output pad is directly connected to the first P-type heavily doped region 22 without passing through other devices.

[0267] Find the first P-type heavily doped region 22 that is indirectly connected to the first input / output pad, which means the first input / output pad is connected to the first P-type heavily doped region 22 through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first P-type heavily doped region 22 through a forward diode.

[0268] Next, perform step 202b to find the first N-type heavily doped region 21 adjacent to the first P-type heavily doped region 22 and located in the first N-well 26, and the second N-type heavily doped region 24 located in the second N-well 27.

[0269] In this embodiment, the first N-type heavily doped region 21 is connected to the ground pad, and the second N-type heavily doped region 24 is connected to the power supply pad.

[0270] The first N-type heavily doped region 21 can be directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0271] The second N-type heavily doped region 24 can be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0272] In one embodiment, the step of finding the first N-type heavily doped region 21 adjacent to the first P-type heavily doped region 22 and located in the first N-well 26, and the second N-type heavily doped region 24 located in the second N-well 27; includes: taking the first P-type heavily doped region 22 as the center and a preset distance as the radius, identifying the first N-type heavily doped region 21 and the second N-type heavily doped region 24 whose distances to the first P-type heavily doped region 22 are less than the preset distance.

[0273] Next, perform step 203b to find the second P-type heavily doped region 23 adjacent to the first N-type heavily doped region 21 and located in the P-type substrate 25; wherein, the first N-well 26 and the second N-well 27 are both located on the P-type substrate 25; the region formed by the first P-type heavily doped region 22, the first N-type heavily doped region 21, the second P-type heavily doped region 23, the second N-type heavily doped region 24, the first N-well 26, the second N-well 27, and the P-type substrate 25 is the identified latch structure.

[0274] In this embodiment, the second P-type heavily doped region 23 is connected to the ground pad.

[0275] The second P-type heavily doped region 23 is directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0276] In one embodiment, finding the second P-type heavily doped region 23 that is adjacent to the first N-type heavily doped region 21 and is located within the P-type substrate 25 includes: taking the first N-type heavily doped region 21 as the center and a preset distance as the radius, identifying the second P-type heavily doped region 23 whose distance to the first N-type heavily doped region 21 is less than the preset distance.

[0277] In one embodiment, as Figure 2c shown, there is a first distance L1 between the second P-type heavily doped region 23 and the first N-type heavily doped region 21, a second distance L2 between the first N-type heavily doped region 21 and the first P-type heavily doped region 22, and a third distance L3 between the first P-type heavily doped region 22 and the second N-type heavily doped region 24.

[0278] Taking the first P-type heavily doped region 22 as the center and a preset distance as the radius, identifying the first N-type heavily doped region 21 and the second N-type heavily doped region 24 whose distances to the first P-type heavily doped region 22 are less than the preset distance specifically includes: both the second distance and the third distance are less than the preset distance.

[0279] Furthermore, as Figure 2d and 2e shown, the second N-well 27, the P-type substrate 25, and the first N-type heavily doped region 21 form a first parasitic NPN transistor T1. The first P-type heavily doped region 22, the second N-well 27, and the P-type substrate 25 form a first parasitic PNP transistor T2.

[0280] The P-type substrate 25 has a first parasitic resistor R PW , the first end of the first parasitic resistor R PW is connected to the second P-type heavily doped region 23, and the second end of the first parasitic resistor R PW is connected to the base of the first parasitic NPN transistor T1.

[0281] The second N-well 27 has a second parasitic resistor R NW , the first end of the second parasitic resistor R NW is connected to the second N-type heavily doped region 24, and the second end of the second parasitic resistor R NW is connected to the base of the first parasitic PNP transistor T2.

[0282] The principle of latch-up effect generation in the latch structure is described below: Specifically, T2 is a vertical PNP transistor with an N-well as the base, and the gain from the base to the collector can reach dozens of times. T1 is a lateral NPN transistor with a P-type substrate as the base, and the gain to the collector can reach dozens of times. R NW is the parasitic resistance of the second N-well, and R PW is the parasitic resistance of the P-type substrate.

[0283] The above four components, T1, T2, R NW and R PW form a thyristor circuit. When there is no external interference and no triggering occurs, the two transistors are in the cut-off state, and the collector current is composed of the reverse leakage current of C-B, with a very small current gain. At this time, the latch-up effect will not occur. When the collector current of one of the transistors suddenly increases to a certain value due to external interference, it will feedback to the other transistor, causing the two transistors to turn on due to triggering (usually PNP is easier to trigger). A low-resistance path is formed between the power pad VDD and the ground pad VSS. After that, even if the external interference disappears, due to the positive feedback formed between the two transistors, there will still be leakage between the power pad VDD and the ground pad VSS, that is, the locked state. The latch-up effect is thus generated.

[0284] Figure 3a FIG. is a schematic flow chart of the method for identifying the latch structure provided by the embodiment of the present invention. As shown in the figure, the method includes the following steps:

[0285] Step 301a: In the chip layout, find the first N-type heavily doped region that is connected to the first input / output pad and is located in the deep N-well;

[0286] Step 302a: Find the first P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located in the second N-well, and the second P-type heavily doped region that is located in the P-type substrate;

[0287] Step 303a: Find the second N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located in the second N-well; wherein, the deep N-well is located in the first N-well, and the first N-well and the second N-well are both located on the P-type substrate; the region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure.

[0288] The method for identifying the latch structure provided by the embodiment of the present invention will be further described in detail below with specific embodiments.

[0289] Figure 3cThe top view of a latch structure provided by an embodiment of the present invention; Figure 3d The cross-sectional view of a latch structure provided by an embodiment of the present invention.

[0290] Before performing step 301a, first find the first input / output pad, and the first input / output pad includes pads such as data signal pads (DQ PAD) or address pads (CA PAD).

[0291] Next, as Figure 3d shown, perform step 301a. In the chip layout, find the first N-type heavily doped region 31 that is connected to the first input / output pad and is located in the deep N-well 36.

[0292] In one embodiment, the finding of the first N-type heavily doped region 31 that is connected to the first input / output pad and is located in the deep N-well 36 includes:

[0293] Find the first N-type heavily doped region 31 that is directly or indirectly connected to the first input / output pad and is located in the deep N-well 36.

[0294] Here, finding the first N-type heavily doped region 31 that is directly connected to the first input / output pad means that the first input / output pad is directly connected to the first N-type heavily doped region 31 without passing through other devices.

[0295] Finding the first N-type heavily doped region 31 that is indirectly connected to the first input / output pad means that the first input / output pad is connected to the first N-type heavily doped region 31 through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first N-type heavily doped region 31 through a reverse diode.

[0296] Next, perform step 302a to find the first P-type heavily doped region 32 that is adjacent to the first N-type heavily doped region 31 and is located in the second N-well 38, and the second P-type heavily doped region 33 that is located in the P-type substrate 35.

[0297] In this embodiment, the first P-type heavily doped region 32 is connected to the power supply pad, and the second P-type heavily doped region 33 is connected to the ground pad.

[0298] The first P-type heavily doped region 32 can be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0299] The second P-type heavily doped region 33 is directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0300] In one embodiment, finding the first P-type heavily doped region 32 adjacent to the first N-type heavily doped region 31 and located in the second N-well 38 and the second P-type heavily doped region 33 located in the P-type substrate 35 includes: centering on the first N-type heavily doped region 31 and using a preset distance as the radius, identifying the first P-type heavily doped region 32 and the second P-type heavily doped region 33 whose distances to the first N-type heavily doped region 31 are less than the preset distance.

[0301] Next, perform step 303a to find the second N-type heavily doped region 34 adjacent to the first P-type heavily doped region 32 and located in the second N-well 38; wherein, the deep N-well 36 is located in the first N-well 37, and both the first N-well 37 and the second N-well 38 are located on the P-type substrate 35; the region formed by the first P-type heavily doped region 32, the first N-type heavily doped region 31, the second P-type heavily doped region 33, the second N-type heavily doped region 34, the deep N-well 36, the first N-well 37, the second N-well 38, and the P-type substrate 35 is the identified latch structure.

[0302] In this embodiment, the second N-type heavily doped region 34 is connected to the power supply pad.

[0303] The second N-type heavily doped region 34 is directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0304] Finding the second N-type heavily doped region 34 adjacent to the first P-type heavily doped region 32 and located in the second N-well 38 includes: centering on the first P-type heavily doped region 32 and using a preset distance as the radius, identifying the second N-type heavily doped region 34 whose distance to the first P-type heavily doped region 32 is less than the preset distance.

[0305] In one embodiment, as Figure 3c shown, there is a first distance L1 between the second P-type heavily doped region 33 and the first N-type heavily doped region 31, a second distance L2 between the first N-type heavily doped region 31 and the first P-type heavily doped region 32, and a third distance L3 between the first P-type heavily doped region 32 and the second N-type heavily doped region 34.

[0306] Taking the first N-type heavily doped region 31 as the center and with a preset distance as the radius, identify the first P-type heavily doped region 32 and the second P-type heavily doped region 33 whose distances to the first N-type heavily doped region 31 are less than the preset distance; specifically including: both the second distance and the first distance are less than the preset distance.

[0307] Figure 3b The flowchart of the identification method for the latch structure provided by the embodiment of the present invention is shown as follows. The method includes the following steps:

[0308] Step 301b: In the chip layout, find the first P-type heavily doped region that is connected to the first input / output pad and is located in the second N-well.

[0309] Step 302b: Find the first N-type heavily doped region adjacent to the first P-type heavily doped region and located in the deep N-well, and the second N-type heavily doped region located in the second N-well.

[0310] Step 303b: Find the second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the P-type substrate; wherein, the deep N-well is located in the first N-well, and both the first N-well and the second N-well are located on the P-type substrate; the region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure.

[0311] Figure 3e A cross-sectional view of a latch structure provided by another embodiment of the present invention.

[0312] Before performing step 301b, first find the first input / output pad, and the first input / output pad includes pads such as data signal pads (DQ PAD) or address pads (CA PAD).

[0313] Next, as Figure 3e shown, perform step 301b. In the chip layout, find the first P-type heavily doped region 32 that is connected to the first input / output pad and is located in the second N-well 38.

[0314] In one embodiment, the finding of the first P-type heavily doped region 32 that is connected to the first input / output pad and is located in the second N-well 38 includes:

[0315] Find the first P-type heavily doped region 32 that is directly or indirectly connected to the first input / output pad and is located in the second N-well 38.

[0316] Here, find the first P-type heavily doped region 32 that is directly connected to the first input / output pad, which means there is a direct connection between the first input / output pad and the first P-type heavily doped region 32 without passing through other devices.

[0317] Find the first P-type heavily doped region 32 that is indirectly connected to the first input / output pad, which means the first input / output pad is connected to the first P-type heavily doped region 32 through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first P-type heavily doped region 32 through a forward diode.

[0318] Next, perform step 302b to find the first N-type heavily doped region 31 that is adjacent to the first P-type heavily doped region 32 and is located in the deep N-well 36, and the second N-type heavily doped region 34 that is located in the second N-well 38.

[0319] In this embodiment, the first N-type heavily doped region 31 is connected to the ground pad, and the second N-type heavily doped region 34 is connected to the power supply pad.

[0320] The first N-type heavily doped region 31 can be directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0321] The second N-type heavily doped region 34 can be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0322] In one embodiment, the step of finding the first N-type heavily doped region 31 that is adjacent to the first P-type heavily doped region 32 and is located in the deep N-well 36, and the second N-type heavily doped region 34 that is located in the second N-well 38; includes: taking the first P-type heavily doped region 32 as the center and a preset distance as the radius, and identifying the first N-type heavily doped region 31 and the second N-type heavily doped region 34 whose distances to the first P-type heavily doped region 32 are less than the preset distance.

[0323] Next, step 303b is executed to find a second P-type heavily doped region 33 that is adjacent to the first N-type heavily doped region 31 and is located within the P-type substrate 35; wherein, the deep N-well 36 is located within the first N-well 37, and both the first N-well 37 and the second N-well 38 are located on the P-type substrate 35; the region formed by the first P-type heavily doped region 32, the first N-type heavily doped region 31, the second P-type heavily doped region 33, the second N-type heavily doped region 34, the deep N-well 36, the first N-well 37, the second N-well 38, and the P-type substrate 35 is the identified latch-up structure.

[0324] In this embodiment, the second P-type heavily doped region 33 is connected to a ground pad.

[0325] The second P-type heavily doped region 33 is directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0326] In one embodiment, the step of finding a second P-type heavily doped region 33 that is adjacent to the first N-type heavily doped region 31 and is located within the P-type substrate 35 includes: taking the first N-type heavily doped region 31 as the center and a preset distance as the radius, identifying a second P-type heavily doped region 33 whose distance to the first N-type heavily doped region 31 is less than the preset distance.

[0327] In one embodiment, as Figure 3c shown, there is a first distance L1 between the second P-type heavily doped region 33 and the first N-type heavily doped region 31, a second distance L2 between the first N-type heavily doped region 31 and the first P-type heavily doped region 32, and a third distance L3 between the first P-type heavily doped region 32 and the second N-type heavily doped region 34.

[0328] The step of taking the first P-type heavily doped region 32 as the center and a preset distance as the radius, and identifying the first N-type heavily doped region 31 and the second N-type heavily doped region 34 whose distances to the first P-type heavily doped region 32 are less than the preset distance includes: both the second distance and the third distance are less than the preset distance.

[0329] Further, as Figure 3d and Figure 3e shown, the second N-well 38, the P-type substrate 35, and the deep N-well 36 form a first parasitic NPN transistor T1. The first P-type heavily doped region 32, the second N-well 38, and the P-type substrate 35 form a first parasitic PNP transistor T2.

[0330] The P-type substrate 35 has a first parasitic resistance R PW , the first parasitic resistance RPW The first end of PW is connected to the second P-type heavily doped region 33, and the first parasitic resistor R

[0331] The second N-well 38 has a second parasitic resistor R NW The second parasitic resistor R NW The first end of is connected to the second N-type heavily doped region 34, and the second parasitic resistor R NW The second end of is connected to the base of the first parasitic PNP transistor T2.

[0332] The principle of the latch-up effect generation in the latch-up structure is described below: Specifically, T2 is a vertical PNP transistor, the base is the N-well, and the gain from the base to the collector can reach dozens of times. T1 is a lateral NPN transistor, the base is the P-type substrate, and the gain to the collector can reach dozens of times. R NW is the parasitic resistor of the second N-well, and R PW is the parasitic resistor of the P-type substrate.

[0333] The above four elements T1, T2, R NW and R PW constitute a thyristor circuit. When there is no external interference and no triggering occurs, the two transistors are in the cut-off state, and the collector current is composed of the reverse leakage current of C-B, and the current gain is very small. At this time, the latch-up effect will not occur. When the collector current of one of the transistors suddenly increases to a certain value due to external interference, it will feedback to the other transistor, so that the two transistors are turned on due to triggering (usually PNP is easier to trigger). A low-resistance path is formed between the power supply pad VDD and the ground pad VSS. After that, even if the external interference disappears, due to the positive feedback formed between the two transistors, there will still be leakage between the power supply pad VDD and the ground pad VSS, that is, the locked state. The latch-up effect is generated therefrom.

[0334] Figure 4a FIG. is a schematic flow chart of the method for identifying the latch-up structure provided by the embodiment of the present invention. As shown in the figure, the method includes the following steps:

[0335] Step 401a: In the chip layout, find the first P-type heavily doped region that is connected to the first input / output pad and is located in the deep N-well;

[0336] Step 402a: Find the first N-type heavily doped region adjacent to the first P-type heavily doped region and located in the P-well and the second N-type heavily doped region located in the deep N-well;

[0337] Step 403a: Find a second P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located within the P well; wherein, the P well is located within the deep N well, the deep N well is located within the N well, and the N well is located on a P-type substrate; the region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P well, the deep N well, the N well, and the P-type substrate is the identified latch structure.

[0338] The method for identifying a latch structure provided by an embodiment of the present invention will be further described in detail below in conjunction with specific embodiments.

[0339] Figure 4c It is a top view of a latch structure provided by an embodiment of the present invention; Figure 4d It is a cross-sectional view of a latch structure provided by an embodiment of the present invention.

[0340] Before performing step 401a, first find a first input / output pad, and the first input / output pad includes pads such as a data signal pad (DQ PAD) or an address pad (CA PAD).

[0341] Next, as Figure 4d shown, perform step 401a. In the chip layout, find a first P-type heavily doped region 41 that is connected to the first input / output pad and is located within the deep N well 47.

[0342] In one embodiment, the finding of the first P-type heavily doped region 41 that is connected to the first input / output pad and is located within the deep N well 47 includes:

[0343] Find a first P-type heavily doped region 41 that is directly or indirectly connected to the first input / output pad and is located within the deep N well 47.

[0344] Here, finding the first P-type heavily doped region 41 that is directly connected to the first input / output pad means that the first input / output pad is directly connected to the first P-type heavily doped region 41 without passing through other devices.

[0345] Finding the first P-type heavily doped region 41 that is indirectly connected to the first input / output pad means that the first input / output pad is connected to the first P-type heavily doped region 41 through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first P-type heavily doped region 41 through a forward diode.

[0346] Next, perform step 402a to find a first N-type heavily doped region 42 adjacent to the first P-type heavily doped region 41 and located within the P well 46, and a second N-type heavily doped region 43 located within the deep N well 47.

[0347] In this embodiment, the first N-type heavily doped region 42 is connected to a ground pad, and the second N-type heavily doped region 43 is connected to a power pad.

[0348] The first N-type heavily doped region 42 may be directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it may be connected through a resistor with a small resistance value, a switching device, or a diode.

[0349] The second N-type heavily doped region 43 may be directly or indirectly connected to the power pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it may be connected through a resistor with a small resistance value, a switching device, or a diode.

[0350] In one embodiment, finding the first N-type heavily doped region 42 adjacent to the first P-type heavily doped region 41 and located within the P well 46, and the second N-type heavily doped region 43 located within the deep N well 47; includes: taking the first P-type heavily doped region 41 as the center and a preset distance as the radius, identifying the first N-type heavily doped region 42 and the second N-type heavily doped region 43 whose distances to the first P-type heavily doped region 41 are less than the preset distance.

[0351] Next, perform step 403a to find a second P-type heavily doped region 44 adjacent to the first N-type heavily doped region 42 and located within the P well 46; wherein, the P well 46 is located within the deep N well 47, the deep N well 47 is located within the N well 48, and the N well 48 is located on the P-type substrate 45; the region formed by the first P-type heavily doped region 41, the first N-type heavily doped region 42, the second P-type heavily doped region 44, the second N-type heavily doped region 43, the P well 46, the deep N well 47, the N well 48, and the P-type substrate 45 is the identified latch structure.

[0352] In this embodiment, the second P-type heavily doped region 44 is connected to a ground pad.

[0353] The second P-type heavily doped region 44 may be directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it may be connected through a resistor with a small resistance value, a switching device, or a diode.

[0354] Finding a second P-type heavily doped region 44 that is adjacent to the first N-type heavily doped region 42 and is located within the P-well 46; includes: centering on the first N-type heavily doped region 42 and using a preset distance as the radius, identifying a second P-type heavily doped region 44 whose distance to the first N-type heavily doped region 42 is less than the preset distance.

[0355] In one embodiment, as Figure 4c shown, there is a first distance L1 between the second N-type heavily doped region 43 and the first P-type heavily doped region 41, a second distance L2 between the first P-type heavily doped region 41 and the first N-type heavily doped region 42, and a third distance L3 between the first N-type heavily doped region 42 and the second P-type heavily doped region 44.

[0356] Centering on the first P-type heavily doped region 41 and using a preset distance as the radius, identifying the first N-type heavily doped region 42 and the second N-type heavily doped region 43 whose distances to the first P-type heavily doped region 41 are less than the preset distance, specifically includes: both the second distance and the first distance are less than the preset distance.

[0357] Figure 4b It is a flowchart of the identification method of the latch structure provided by the embodiment of the present invention. As shown, the method includes the following steps:

[0358] Step 401b: In the chip layout, find a first N-type heavily doped region that is connected to the first input / output pad and is located within the P-well;

[0359] Step 402b: Find a first P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located within the deep N-well and a second P-type heavily doped region that is located within the P-well;

[0360] Step 403b: Find a second N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located within the deep N-well; wherein, the P-well is located within the deep N-well, the deep N-well is located within the N-well, and the N-well is located on the P-type substrate; the region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the N-well, and the P-type substrate is the identified latch structure.

[0361] The following further elaborates on the identification method of the latch structure provided by the embodiment of the present invention in combination with specific embodiments.

[0362] Figure 4e It is a cross-sectional view of a latch structure provided by another embodiment of the present invention.

[0363] Before performing step 401b, first find the first input / output pad, which includes pads such as data signal pads (DQ PAD) or address pads (CA PAD).

[0364] Next, as Figure 4e shown, perform step 401b. In the chip layout, find the first N-type heavily doped region 42 that is connected to the first input / output pad and is located within the P-well 46.

[0365] In one embodiment, finding the first N-type heavily doped region 42 that is connected to the first input / output pad and is located within the P-well 46 includes:[[]]END

[0366] finding the first N-type heavily doped region 42 that is directly or indirectly connected to the first input / output pad and is located within the P-well 46.

[0367] Here, finding the first N-type heavily doped region 42 that is directly connected to the first input / output pad means that the first N-type heavily doped regions 42 are directly connected without passing through other devices.

[0368] Finding the first N-type heavily doped region 42 that is indirectly connected to the first input / output pad means that the first input / output pad is connected to the first N-type heavily doped region 42 through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first N-type heavily doped region 42 through a reverse diode.

[0369] Next, perform step 402b to find the first P-type heavily doped region 41 that is adjacent to the first N-type heavily doped region 42 and is located within the deep N-well 47, and the second P-type heavily doped region 44 that is located within the P-well 46.

[0370] In this embodiment, the first P-type heavily doped region 41 is connected to the power supply pad, and the second P-type heavily doped region 44 is connected to the ground pad.

[0371] The first P-type heavily doped region 41 can be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0372] The second P-type heavily doped region 44 can be directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0373] In one embodiment, finding the first P-type heavily doped region 41 adjacent to the first N-type heavily doped region 42 and located in the deep N-well 47 and the second P-type heavily doped region 44 located in the P-well 46 includes: centering on the first N-type heavily doped region 42 and using a preset distance as the radius, identifying the first P-type heavily doped region 41 and the second P-type heavily doped region 44 whose distances to the first N-type heavily doped region 42 are less than the preset distance.

[0374] Next, perform step 403b to find the second N-type heavily doped region 43 adjacent to the first P-type heavily doped region 41 and located in the deep N-well 47. Among them, the P-well 46 is located in the deep N-well 47, the deep N-well 47 is located in the N-well 48, and the N-well 48 is located on the P-type substrate 45. The region formed by the first P-type heavily doped region 41, the first N-type heavily doped region 42, the second P-type heavily doped region 44, the second N-type heavily doped region 43, the P-well 46, the deep N-well 47, the N-well 48, and the P-type substrate 45 is the identified latch structure.

[0375] In this embodiment, the second N-type heavily doped region 43 is connected to the power supply pad.

[0376] The second N-type heavily doped region 43 is directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0377] In one embodiment, finding the second N-type heavily doped region 43 adjacent to the first P-type heavily doped region 41 and located in the deep N-well 47 includes: centering on the first P-type heavily doped region 41 and using a preset distance as the radius, identifying the second N-type heavily doped region 43 whose distance to the first P-type heavily doped region 41 is less than the preset distance.

[0378] In one embodiment, as Figure 4c shown, there is a first distance L1 between the second N-type heavily doped region 43 and the first P-type heavily doped region 41, a second distance L2 between the first P-type heavily doped region 41 and the first N-type heavily doped region 42, and a third distance L3 between the first N-type heavily doped region 42 and the second P-type heavily doped region 44.

[0379] The identifying the first P-type heavily doped region 41 and the second P-type heavily doped region 44 whose distances to the first N-type heavily doped region 42 are less than the preset distance by centering on the first N-type heavily doped region 42 and using a preset distance as the radius specifically includes: both the second distance and the third distance are less than the preset distance.

[0380] Further, as shown in Figure 4d and Figure 4e , the first P-type heavily doped region 41, the deep N-well 47, and the second P-type heavily doped region 44 form a first parasitic PNP transistor T1. The first N-type heavily doped region 42, the P-well 46, and the deep N-well 47 form a first parasitic NPN transistor T2.

[0381] The deep N-well 47 has a first parasitic resistance R DNW . The first end of the first parasitic resistance R DNW is connected to the second N-type heavily doped region 43, and the second end of the first parasitic resistance R DNW is connected to the base of the first parasitic PNP transistor.

[0382] The P-well 46 has a second parasitic resistance R PW . The first end of the second parasitic resistance R PW is connected to the second P-type heavily doped region 44, and the second end of the second parasitic resistance R PW is connected to the base of the first parasitic NPN transistor T2 and the collector of the first parasitic PNP transistor T1.

[0383] The principle of the latch-up effect is described below: Specifically, T1 is a vertical PNP transistor, the base is the N-well, and the gain from the base to the collector can reach several hundred times. T2 is a lateral NPN transistor, the base is the P-type substrate, and the gain to the collector can reach dozens of times. R DNW is the parasitic resistance of the deep N-well, and R PW is the parasitic resistance of the P-well.

[0384] The above four elements T1, T2, R DNW and R PW constitute a thyristor circuit. When there is no external interference and no triggering occurs, the two transistors are in the cut-off state, and the collector current is composed of the reverse leakage current of C-B, and the current gain is very small. At this time, the latch-up effect will not occur. When the collector current of one of the transistors suddenly increases to a certain value due to external interference, it will feedback to the other transistor, causing the two transistors to turn on due to triggering (usually the PNP is easier to trigger). A low-resistance path is formed between the power supply pad VDD and the ground pad VSS. After that, even if the external interference disappears, due to the positive feedback formed between the two transistors, there will still be leakage between the power supply pad VDD and the ground pad VSS, that is, the locked state. The latch-up effect is generated thereby.

[0385] Figure 5a is a schematic flowchart of the method for identifying the latch-up structure provided by the embodiment of the present invention. As shown in the figure, the method includes the following steps:

[0386] Step 501a: In the chip layout, find the first P-type heavily doped region located in the P-well and connected to the first input / output pad, or the first N-type heavily doped region located in the P-type substrate.

[0387] Step 502a: Find the second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the N-well.

[0388] Step 503a: Find the second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the P-type substrate; wherein, the P-well is located in the deep N-well, the deep N-well is located in the N-well, and the N-well is located on the P-type substrate; the region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the N-well, and the P-type substrate is the identified latch structure.

[0389] The following further elaborates on the method for identifying the latch structure provided by the embodiments of the present invention in combination with specific embodiments.

[0390] Figure 5c It is a top view of a latch structure provided by an embodiment of the present invention; Figure 5d It is a cross-sectional view of a latch structure provided by an embodiment of the present invention.

[0391] Before performing Step 501a, first find the first input / output pad, and the first input / output pad includes pads such as data signal pads (DQ PAD) or address pads (CA PAD).

[0392] Then, as Figure 5d shown, perform Step 501a. In the chip layout, find the first P-type heavily doped region 51 that is connected to the first input / output pad and located in the P-well 56.

[0393] In one embodiment, the finding of the first P-type heavily doped region 51 that is connected to the first input / output pad and located in the P-well 56 includes:

[0394] Find the first P-type heavily doped region 51 that is directly or indirectly connected to the first input / output pad and located in the P-well 56.

[0395] Here, finding the first P-type heavily doped region 51 directly connected to the first input / output pad means that the first input / output pad is directly connected to the first P-type heavily doped region 51 without passing through other devices.

[0396] Find the first P-type heavily doped region 51 that is indirectly connected to the first input / output pad, which means the first input / output pad is connected to the first P-type heavily doped region 51 through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first P-type heavily doped region 51 through a forward diode.

[0397] Next, perform step 502a to find the first N-type heavily doped region 52 located in the P-type substrate 55 and the second N-type heavily doped region 53 located in the N-well 58 that are adjacent to the first P-type heavily doped region 51.

[0398] In this embodiment, the first N-type heavily doped region 52 is connected to the ground pad, and the second N-type heavily doped region 53 is connected to the power supply pad.

[0399] The first N-type heavily doped region 52 can be directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0400] The second N-type heavily doped region 53 can be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0401] In one embodiment, the step of finding the first N-type heavily doped region 52 located in the P-type substrate 55 and the second N-type heavily doped region 53 located in the N-well 58 that are adjacent to the first P-type heavily doped region 51 includes: taking the first P-type heavily doped region 51 as the center and a preset distance as the radius, and identifying the first N-type heavily doped region 52 and the second N-type heavily doped region 53 whose distances to the first P-type heavily doped region 51 are less than the preset distance.

[0402] Next, perform step 503a to find the second P-type heavily doped region 54 located in the P-type substrate 55 that is adjacent to the first N-type heavily doped region 52; where the P-well 56 is located in the deep N-well 57, the deep N-well 57 is located in the N-well 58, the N-well 58 is located on the P-type substrate 55; the region formed by the first P-type heavily doped region 51, the first N-type heavily doped region 52, the second P-type heavily doped region 54, the second N-type heavily doped region 53, the P-well 56, the deep N-well 57, the N-well 58, and the P-type substrate 55 is the identified latch-up structure.

[0403] In this embodiment, the second P-type heavily doped region 54 is connected to the ground pad.

[0404] The second P-type heavily doped region 54 is directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0405] Finding the second P-type heavily doped region 54 adjacent to the first N-type heavily doped region 52 and located within the P-type substrate 55 includes: centering on the first N-type heavily doped region 52 and using a preset distance as the radius to identify the second P-type heavily doped region 54 whose distance to the first N-type heavily doped region 52 is less than the preset distance.

[0406] In one embodiment, as Figure 5c shown, there is a first distance L1 between the second N-type heavily doped region 53 and the first P-type heavily doped region 51, a second distance L2 between the first P-type heavily doped region 51 and the first N-type heavily doped region 52, and a third distance L3 between the first N-type heavily doped region 52 and the second P-type heavily doped region 54.

[0407] Centering on the first P-type heavily doped region 51 and using a preset distance as the radius to identify the first N-type heavily doped region 52 and the second N-type heavily doped region 53 whose distances to the first P-type heavily doped region 51 are less than the preset distance specifically includes: both the second distance and the first distance are less than the preset distance.

[0408] Figure 5b It is a schematic flowchart of the recognition method for the latch structure provided by another embodiment of the present invention. As shown, the method includes the following steps:

[0409] Step 501b: In the chip layout, find the first N-type heavily doped region connected to the first input / output pad and located within the P-type substrate;

[0410] Step 502b: Find the first P-type heavily doped region adjacent to the first N-type heavily doped region and located within the P-well, and the second P-type heavily doped region located within the P-type substrate;

[0411] Step 503b: Find the second N-type heavily doped region adjacent to the first P-type heavily doped region and located within the N-well; wherein, the P-well is located within the deep N-well, the deep N-well is located within the N-well, the N-well is located on the P-type substrate; the region composed of the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the N-well, and the P-type substrate is the identified latch structure.

[0412] The recognition method of the latch structure provided by the embodiments of the present invention will be further described in detail below in conjunction with specific embodiments.

[0413] Figure 5e A cross-sectional view of a latch structure provided by another embodiment of the present invention.

[0414] Before performing step 501b, first find the first input / output pad, and the first input / output pad includes pads such as data signal pads (DQ PAD) or address pads (CA PAD).

[0415] Next, as Figure 5e shown, perform step 501b. In the chip layout, find the first N-type heavily doped region 52 that is connected to the first input / output pad and is located in the P-type substrate 55;

[0416] In one embodiment, the finding of the first N-type heavily doped region 52 that is connected to the first input / output pad and is located in the P-type substrate 55 includes:

[0417] Find the first N-type heavily doped region 52 that is directly or indirectly connected to the first input / output pad and is located in the P-type substrate 55.

[0418] Here, finding the first N-type heavily doped region 52 directly connected to the first input / output pad means that the first input / output pad is directly connected to the first N-type heavily doped region 52 without passing through other devices.

[0419] Finding the first N-type heavily doped region 52 indirectly connected to the first input / output pad means that the first input / output pad is connected to the first N-type heavily doped region 52 through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first N-type heavily doped region 52 through a reverse diode.

[0420] Next, perform step 502b to find the first P-type heavily doped region 51 adjacent to the first N-type heavily doped region 52 and located in the P-well 56 and the second P-type heavily doped region 54 located in the P-type substrate 55.

[0421] In this embodiment, the first P-type heavily doped region 51 is connected to the power supply pad, and the second P-type heavily doped region 54 is connected to the ground pad.

[0422] The first P-type heavily doped region 51 can be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0423] The second P-type heavily doped region 54 is directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0424] Finding the first P-type heavily doped region 51 adjacent to the first N-type heavily doped region 52 and located within the P-well 56, and the second P-type heavily doped region 54 located within the P-type substrate 55; includes: centering on the first N-type heavily doped region 52 and using a preset distance as the radius, identifying the first P-type heavily doped region 51 and the second P-type heavily doped region 54 whose distances to the first N-type heavily doped region 52 are less than the preset distance.

[0425] Next, perform step 503b to find the second N-type heavily doped region 53 adjacent to the first P-type heavily doped region 51 and located within the N-well 58; wherein, the P-well 56 is located within the deep N-well 57, the deep N-well 57 is located within the N-well 58, the N-well 58 is located on the P-type substrate 55; the region formed by the first P-type heavily doped region 51, the first N-type heavily doped region 52, the second P-type heavily doped region 54, the second N-type heavily doped region 53, the P-well 56, the deep N-well 57, the N-well 58, and the P-type substrate 55 is the identified latch structure.

[0426] In this embodiment, the second N-type heavily doped region 53 is connected to the power supply pad.

[0427] The second N-type heavily doped region 53 is directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0428] Finding the second N-type heavily doped region 53 adjacent to the first P-type heavily doped region 51 and located within the N-well 58; includes: centering on the first P-type heavily doped region 51 and using a preset distance as the radius, identifying the second N-type heavily doped region 53 whose distance to the first P-type heavily doped region 51 is less than the preset distance.

[0429] In one embodiment, as Figure 5c shown, there is a first distance L1 between the second N-type heavily doped region 53 and the first P-type heavily doped region 51, a second distance L2 between the first P-type heavily doped region 51 and the first N-type heavily doped region 52, and a third distance L3 between the first N-type heavily doped region 52 and the second P-type heavily doped region 54.

[0430] Centering around the first N-type heavily doped region 52 and with a preset distance as the radius, a first P-type heavily doped region 51 and a second P-type heavily doped region 54 whose distances to the first N-type heavily doped region 52 are less than the preset distance are identified. Specifically, the second distance and the third distance are less than the preset distance.

[0431] Further, as Figure 5d and Figure 5e shown, the P-well 56, the deep N-well 57, and the P-type substrate 55 form a first parasitic PNP transistor T1. The deep N-well 57, the P-type substrate 55, and the first N-type heavily doped region 52 form a first parasitic NPN transistor T2.

[0432] The deep N-well 57 has a first parasitic resistor R DNW , and the first end of the first parasitic resistor R DNW is connected to the second N-type heavily doped region 53, and the second end of the first parasitic resistor R DNW is connected to the base of the first parasitic PNP transistor T1.

[0433] The P-type substrate 55 has a second parasitic resistor R PW , and the first end of the second parasitic resistor R PW is connected to the second P-type heavily doped region 54, and the second end of the second parasitic resistor R PW is connected to the base of the first parasitic NPN transistor T2 and the collector of the first parasitic PNP transistor T1.

[0434] The principle of the latch-up effect is described below: Specifically, T1 is a vertical PNP transistor, the base is the N-well, and the gain from the base to the collector can reach several hundred times. T2 is a lateral NPN transistor, the base is the P-type substrate, and the gain to the collector can reach dozens of times. R DNW is the parasitic resistor of the deep N-well, and R PW is the parasitic resistor of the P-type substrate.

[0435] The above four elements T1, T2, R DNW and R PW constitute a thyristor circuit. When there is no external interference and no triggering occurs, the two transistors are in the cut-off state, and the collector current is composed of the reverse leakage current of C-B, and the current gain is very small. At this time, the latch-up effect will not occur. When the collector current of one of the transistors suddenly increases to a certain value due to external interference, it will feedback to the other transistor, causing the two transistors to turn on due to triggering (usually the PNP is easier to trigger). A low-resistance path is formed between the power supply pad VDD and the ground pad VSS. After that, even if the external interference disappears, due to the positive feedback formed between the two transistors, there will still be leakage between the power supply pad VDD and the ground pad VSS, that is, the locked state. The latch-up effect is thus generated.

[0436] Figure 6a The flowchart of the method for identifying the latch structure provided by the embodiment of the present invention is shown as follows. The method includes the following steps:

[0437] Step 601a: In the chip layout, find the first P-type heavily doped region that is connected to the first input / output pad and is located in the P-well.

[0438] Step 602a: Find the first N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located in the second N-well, and the second N-type heavily doped region that is located in the first N-well.

[0439] Step 603a: Find the second P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located in the P-type substrate. Wherein, the P-well is located in the deep N-well, the deep N-well is located in the first N-well, and both the first N-well and the second N-well are located on the P-type substrate; the region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure.

[0440] The following further elaborates on the method for identifying the latch structure provided by the embodiment of the present invention in conjunction with specific embodiments.

[0441] Figure 6c The top view of a latch structure provided by the embodiment of the present invention; Figure 6d The cross-sectional view of a latch structure provided by the embodiment of the present invention.

[0442] Before performing step 601a, first find the first input / output pad, and the first input / output pad includes pads such as data signal pads (DQ PAD) or address pads (CA PAD).

[0443] Next, as Figure 6d shown, perform step 601a. In the chip layout, find the first P-type heavily doped region 61 that is connected to the first input / output pad and is located in the P-well 66.

[0444] In an embodiment, the finding of the first P-type heavily doped region 61 that is connected to the first input / output pad and is located in the P-well 66 includes:

[0445] Find the first P-type heavily doped region 61 that is directly or indirectly connected to the first input / output pad and is located in the P-well 66.

[0446] Here, find the first P-type heavily doped region 61 that is directly connected to the first input / output pad, which means that the first input / output pad is directly connected to the first P-type heavily doped region 61 without passing through other devices.

[0447] Find the first P-type heavily doped region 61 that is indirectly connected to the first input / output pad, which means that the first input / output pad is connected to the first P-type heavily doped region 61 through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first P-type heavily doped region 61 through a forward diode.

[0448] Next, perform step 602a to find the first N-type heavily doped region 62 located in the second N-well 69 and the second N-type heavily doped region 63 located in the first N-well 68 that are adjacent to the first P-type heavily doped region 61.

[0449] In this embodiment, the first N-type heavily doped region 62 is connected to the ground pad, and the second N-type heavily doped region 63 is connected to the power supply pad.

[0450] The first N-type heavily doped region 62 can be directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0451] The second N-type heavily doped region 63 can be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0452] In one embodiment, the step of finding the first N-type heavily doped region 62 located in the second N-well 69 and the second N-type heavily doped region 63 located in the first N-well 68 that are adjacent to the first P-type heavily doped region 61 includes: taking the first P-type heavily doped region 61 as the center and a preset distance as the radius, identifying the first N-type heavily doped region 62 and the second N-type heavily doped region 63 whose distances to the first P-type heavily doped region 61 are less than the preset distance.

[0453] Next, perform step 603a to find a second P-type heavily doped region 64 that is adjacent to the first N-type heavily doped region 62 and is located within the P-type substrate 65. Among them, the P-well 66 is located within the deep N-well 67, the deep N-well 67 is located within the first N-well 68, and both the first N-well 68 and the second N-well 69 are located on the P-type substrate 65. The region formed by the first P-type heavily doped region 61, the first N-type heavily doped region 62, the second P-type heavily doped region 64, the second N-type heavily doped region 63, the P-well 66, the deep N-well 67, the first N-well 68, the second N-well 69, and the P-type substrate 65 is the identified latch structure.

[0454] In this embodiment, the second P-type heavily doped region 64 is connected to the ground pad.

[0455] The second P-type heavily doped region 64 is directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0456] The step of finding the second P-type heavily doped region 64 that is adjacent to the first N-type heavily doped region 62 and is located within the P-type substrate 65 includes: taking the first N-type heavily doped region 62 as the center and a preset distance as the radius, and identifying the second P-type heavily doped region 64 whose distance to the first N-type heavily doped region 62 is less than the preset distance.

[0457] In one embodiment, as Figure 6c shown, there is a first distance L1 between the second N-type heavily doped region 63 and the first P-type heavily doped region 61, a second distance L2 between the first P-type heavily doped region 61 and the first N-type heavily doped region 62, and a third distance L3 between the first N-type heavily doped region 62 and the second P-type heavily doped region 64.

[0458] Taking the first P-type heavily doped region 61 as the center and a preset distance as the radius, identifying the first N-type heavily doped region 62 and the second N-type heavily doped region 63 whose distances to the first P-type heavily doped region 61 are less than the preset distance. Specifically, it includes: both the second distance and the first distance are less than the preset distance.

[0459] Figure 6b It is a flowchart of the method for identifying a latch structure provided by an embodiment of the present invention. As shown in the figure, the method includes the following steps:

[0460] Step 601b: In the chip layout, find a first N-type heavily doped region that is connected to the first input / output pad and is located within the second N-well.

[0461] Step 602b: Identify a first P-type heavily doped region within the P well and a second P-type heavily doped region within the P-type substrate that are adjacent to the first N-type heavily doped region.

[0462] Step 603b: Identify a second N-type heavily doped region within the first N well that is adjacent to the first P-type heavily doped region; wherein the P well is within the deep N well, the deep N well is within the first N well, and both the first N well and the second N well are on the P-type substrate; the region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P well, the deep N well, the first N well, the second N well, and the P-type substrate is the identified latch structure.

[0463] The following further elaborates on the method for identifying the latch structure provided by the embodiments of the present invention in conjunction with specific embodiments.

[0464] Figure 6e This is a cross-sectional view of a latch structure provided by another embodiment of the present invention.

[0465] Before performing step 601b, first identify the first input / output pad, and the first input / output pad includes pads such as data signal pads (DQ PAD) or address pads (CA PAD).

[0466] Next, as Figure 6e shown, perform step 601b. In the chip layout, identify the first N-type heavily doped region 62 that is connected to the first input / output pad and is within the second N well 69.

[0467] In one embodiment, the identifying the first N-type heavily doped region 62 that is connected to the first input / output pad and is within the second N well 69 includes:

[0468] Identify the first N-type heavily doped region 62 that is directly or indirectly connected to the first input / output pad and is within the second N well 69.

[0469] Here, identifying the first N-type heavily doped region 62 that is directly connected to the first input / output pad means that the first input / output pad is directly connected to the first N-type heavily doped region 62 without passing through other devices.

[0470] Identifying the first N-type heavily doped region 62 that is indirectly connected to the first input / output pad means that the first input / output pad is connected to the first N-type heavily doped region 62 through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first N-type heavily doped region 62 through a reverse diode.

[0471] Next, perform step 602b to find the first P-type heavily doped region 61 adjacent to the first N-type heavily doped region 62 and located within the P-well 66, and the second P-type heavily doped region 64 located within the P-type substrate 65.

[0472] In this embodiment, the first P-type heavily doped region 61 is connected to the power supply pad, and the second P-type heavily doped region 64 is connected to the ground pad.

[0473] The first P-type heavily doped region 61 may be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it may be connected through a resistor with a small resistance value, a switching device, or a diode.

[0474] The second P-type heavily doped region 64 may be directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it may be connected through a resistor with a small resistance value, a switching device, or a diode.

[0475] The step of finding the first P-type heavily doped region 61 adjacent to the first N-type heavily doped region 62 and located within the P-well 66, and the second P-type heavily doped region 64 located within the P-type substrate 65; includes: centering on the first N-type heavily doped region 62 and using a preset distance as the radius, identifying the first P-type heavily doped region 61 and the second P-type heavily doped region 64 whose distances to the first N-type heavily doped region 62 are less than the preset distance.

[0476] Next, perform step 603b to find the second N-type heavily doped region 63 adjacent to the first P-type heavily doped region 61 and located within the first N-well 68; wherein, the P-well 66 is located within the deep N-well 67, the deep N-well 67 is located within the first N-well 68, the first N-well 68 and the second N-well 69 are both located on the P-type substrate 65; the region formed by the first P-type heavily doped region 61, the first N-type heavily doped region 62, the second P-type heavily doped region 64, the second N-type heavily doped region 63, the P-well 66, the deep N-well 67, the first N-well 68, the second N-well 69, and the P-type substrate 65 is the identified latch structure.

[0477] In this embodiment, the second N-type heavily doped region 63 is connected to the power supply pad.

[0478] The second N-type heavily doped region 63 may be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it may be connected through a resistor with a small resistance value, a switching device, or a diode.

[0479] Find the second N-type heavily doped region 63 that is adjacent to the first P-type heavily doped region 61 and is located within the first N-well 68; including: with the first P-type heavily doped region 61 as the center and a preset distance as the radius, identify the second N-type heavily doped region 63 whose distance to the first P-type heavily doped region 61 is less than the preset distance.

[0480] In one embodiment, as Figure 6c shown, there is a first distance L1 between the second N-type heavily doped region 63 and the first P-type heavily doped region 61, a second distance L2 between the first P-type heavily doped region 61 and the first N-type heavily doped region 62, and a third distance L3 between the first N-type heavily doped region 62 and the second P-type heavily doped region 64.

[0481] With the first N-type heavily doped region 62 as the center and a preset distance as the radius, identify the first P-type heavily doped region 61 and the second P-type heavily doped region 64 whose distances to the first N-type heavily doped region 62 are less than the preset distance; specifically including: both the second distance and the third distance are less than the preset distance.

[0482] Furthermore, as Figure 6d and Figure 6e shown, the P-well 66, the deep N-well 67, and the P-type substrate 65 form a first parasitic PNP transistor T1. The deep N-well 67, the P-type substrate 65, and the second N-well 69 form a first parasitic NPN transistor T2.

[0483] The deep N-well 67 has a first parasitic resistance R DNW , the first end of the first parasitic resistance R DNW is connected to the second N-type heavily doped region 63, and the second end of the first parasitic resistance R DNW is connected to the base of the first parasitic PNP transistor T1.

[0484] The P-type substrate 65 has a second parasitic resistance R PW , the first end of the second parasitic resistance R PW is connected to the second P-type heavily doped region 64, and the second end of the second parasitic resistance R PW is connected to the base of the first parasitic NPN transistor T2 and the collector of the first parasitic PNP transistor T1.

[0485] The following describes the principle of the latch-up effect: Specifically, T1 is a vertical PNP transistor, the base is the N-well, and the gain from the base to the collector can reach several hundred times. T2 is a lateral NPN transistor, the base is the P-type substrate, and the gain to the collector can reach several tens of times. R DNW is the parasitic resistance of the deep N-well, and R PW is the parasitic resistance of the P-type substrate.

[0486] The above four components T1, T2, R DNW and R PW constitute a thyristor circuit. When there is no external interference causing triggering, the two transistors are in the cut-off state, and the collector current is composed of the reverse leakage current of C-B, with a very small current gain. At this time, the latching effect will not occur. When the collector current of one of the transistors suddenly increases to a certain value due to external interference, it will feedback to the other transistor, causing the two transistors to turn on due to triggering (usually PNP is easier to trigger). A low-resistance path is formed between the power pad VDD and the ground pad VSS. After that, even if the external interference disappears, due to the positive feedback formed between the two transistors, there will still be leakage between the power pad VDD and the ground pad VSS, that is, the locked state. The latching effect is thus generated.

[0487] Figure 7a FIG. is a schematic flow chart of a method for identifying a latching structure provided by an embodiment of the present invention. As shown in the figure, the method includes the following steps:

[0488] Step 701a: In the chip layout, find the first P-type heavily doped region that is connected to the first input / output pad and is located in the P-well;

[0489] Step 702a: Find the first N-type heavily doped region that is adjacent to the first P-type heavily doped region and is located in the second deep N-well and the second N-type heavily doped region that is located in the first N-well;

[0490] Step 703a: Find the second P-type heavily doped region that is adjacent to the first N-type heavily doped region and is located in the P-type substrate; wherein, the P-well is located in the first deep N-well, the first deep N-well is located in the first N-well, the second deep N-well is located in the second N-well, the first N-well and the second N-well are both located on the P-type substrate; the region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the first deep N-well, the second deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latching structure.

[0491] The following further elaborates on the method for identifying a latching structure provided by an embodiment of the present invention in combination with specific embodiments.

[0492] Figure 7c FIG. is a top view of a latching structure provided by an embodiment of the present invention; Figure 7d FIG. is a cross-sectional view of a latching structure provided by an embodiment of the present invention.

[0493] Before performing step 701a, first find the first input / output pad, where the first input / output pad includes pads such as data signal pads (DQ PAD) or address pads (CA PAD).

[0494] Next, as Figure 7d shown, perform step 701a. In the chip layout, find the first P-type heavily doped region 71 that is connected to the first input / output pad and is located within the P-well 76.

[0495] In one embodiment, finding the first P-type heavily doped region 71 that is connected to the first input / output pad and is located within the P-well 76 includes:

[0496] finding the first P-type heavily doped region 71 that is directly or indirectly connected to the first input / output pad and is located within the P-well 76.

[0497] Here, finding the first P-type heavily doped region 71 that is directly connected to the first input / output pad means that there is a direct connection between the first input / output pad and the first P-type heavily doped region 71 without passing through other devices.

[0498] Finding the first P-type heavily doped region 71 that is indirectly connected to the first input / output pad means that the first input / output pad is connected to the first P-type heavily doped region 71 through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first P-type heavily doped region 71 through a forward diode.

[0499] Next, perform step 702a to find the first N-type heavily doped region 72 that is adjacent to the first P-type heavily doped region 71 and is located within the second deep N-well 78, and the second N-type heavily doped region 73 that is located within the first N-well 79.

[0500] In this embodiment, the first N-type heavily doped region 72 is connected to the ground pad, and the second N-type heavily doped region 73 is connected to the power supply pad.

[0501] The first N-type heavily doped region 72 can be directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0502] The second N-type heavily doped region 73 can be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance, a switching device, or a diode.

[0503] In one embodiment, finding the first N-type heavily doped region 72 adjacent to the first P-type heavily doped region 71 and located in the second deep N-well 78, and the second N-type heavily doped region 73 located in the first N-well 79; includes: centering on the first P-type heavily doped region 71 and with a preset distance as the radius, identifying the first N-type heavily doped region 72 and the second N-type heavily doped region 73 whose distances to the first P-type heavily doped region 71 are less than the preset distance.

[0504] Next, perform step 703a to find the second P-type heavily doped region 74 adjacent to the first N-type heavily doped region 72 and located in the P-type substrate 75; wherein, the P-well 76 is located in the first deep N-well 77, the first deep N-well 77 is located in the first N-well 79, the second deep N-well 78 is located in the second N-well 80, both the first N-well 79 and the second N-well 80 are located on the P-type substrate 75; the region formed by the first P-type heavily doped region 71, the first N-type heavily doped region 72, the second P-type heavily doped region 74, the second N-type heavily doped region 73, the P-well 76, the first deep N-well 77, the second deep N-well 78, the first N-well 79, the second N-well 80, and the P-type substrate 75 is the identified latch-up structure.

[0505] In this embodiment, the second P-type heavily doped region 74 is connected to the ground pad.

[0506] The second P-type heavily doped region 74 is directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0507] Finding the second P-type heavily doped region 74 adjacent to the first N-type heavily doped region 72 and located in the P-type substrate 75; includes: centering on the first N-type heavily doped region 72 and with a preset distance as the radius, identifying the second P-type heavily doped region 74 whose distance to the first N-type heavily doped region 72 is less than the preset distance.

[0508] In one embodiment, as Figure 7c shown, there is a first distance L1 between the second N-type heavily doped region 73 and the first P-type heavily doped region 71, a second distance L2 between the first P-type heavily doped region 71 and the first N-type heavily doped region 72, and a third distance L3 between the first N-type heavily doped region 72 and the second P-type heavily doped region 74.

[0509] Centered on the first P-type heavily doped region 71, with a preset distance as the radius, identify the first N-type heavily doped region 72 and the second N-type heavily doped region 73 whose distances to the first P-type heavily doped region 71 are less than the preset distance; specifically including: both the second distance and the first distance are less than the preset distance.

[0510] Figure 7b As shown in the flowchart of the recognition method for the latch structure provided in another embodiment of the present invention, the method includes the following steps:

[0511] Step 701b: In the chip layout, find the first N-type heavily doped region that is connected to the first input / output pad and is located in the second deep N-well.

[0512] Step 702b: Find the first P-type heavily doped region adjacent to the first N-type heavily doped region and located in the P-well, and the second P-type heavily doped region located in the P-type substrate.

[0513] Step 703b: Find the second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the first N-well; wherein, the P-well is located in the first deep N-well, the first deep N-well is located in the first N-well, the second deep N-well is located in the second N-well, the first N-well and the second N-well are both located on the P-type substrate; the region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the first deep N-well, the second deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure.

[0514] The following further elaborates on the recognition method for the latch structure provided in the embodiments of the present invention with specific embodiments.

[0515] Figure 7e A cross-sectional view of a latch structure provided in another embodiment of the present invention.

[0516] Before performing step 701b, first find the first input / output pad, and the first input / output pad includes pads such as data signal pads (DQ PAD) or address pads (CA PAD).

[0517] Next, as Figure 7e shown, perform step 701b, and in the chip layout, find the first N-type heavily doped region 72 that is connected to the first input / output pad and is located in the second deep N-well 78.

[0518] In one embodiment, the finding of the first N-type heavily doped region 72 that is connected to the first input / output pad and is located in the second deep N-well 78 includes:

[0519] Find the first N-type heavily doped region 72 that is directly or indirectly connected to the first input / output pad and is located within the second deep N-well 78.

[0520] Here, finding the first N-type heavily doped region 72 that is directly connected to the first input / output pad means that there is a direct connection between the first input / output pad and the first N-type heavily doped region 72 without passing through other devices.

[0521] Finding the first N-type heavily doped region 72 that is indirectly connected to the first input / output pad means that the first input / output pad is connected to the first N-type heavily doped region 72 through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode. More specifically, the first input / output pad can be connected to the first N-type heavily doped region 72 through a reverse diode.

[0522] Next, perform step 702b to find the first P-type heavily doped region 71 located within the P-well 76 and the second P-type heavily doped region 74 located within the P-type substrate 75 that are adjacent to the first N-type heavily doped region 72.

[0523] In this embodiment, the first P-type heavily doped region 71 is connected to the power supply pad, and the second P-type heavily doped region 74 is connected to the ground pad.

[0524] The first P-type heavily doped region 71 can be directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0525] The second P-type heavily doped region 74 can be directly or indirectly connected to the ground pad. The indirect connection includes being connected through a path that can transmit a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0526] In one embodiment, finding the first P-type heavily doped region 71 located within the P-well 76 and the second P-type heavily doped region 74 located within the P-type substrate 75 that are adjacent to the first N-type heavily doped region 72 includes: centering on the first N-type heavily doped region 72 and using a preset distance as the radius to identify the first P-type heavily doped region 71 and the second P-type heavily doped region 74 whose distances to the first N-type heavily doped region 72 are less than the preset distance. Here, the preset distance described in the embodiments of the present invention can be obtained according to the design rules of the chip layout.

[0527] Next, perform step 703b to find a second N-type heavily doped region 73 that is adjacent to the first P-type heavily doped region 71 and is located within the first N-well 79; wherein, the P-well 76 is located within the first deep N-well 77, the first deep N-well 77 is located within the first N-well 79, the second deep N-well 78 is located within the second N-well 80, and both the first N-well 79 and the second N-well 80 are located on the P-type substrate 75; the region formed by the first P-type heavily doped region 71, the first N-type heavily doped region 72, the second P-type heavily doped region 74, the second N-type heavily doped region 73, the P-well 76, the first deep N-well 77, the second deep N-well 78, the first N-well 79, the second N-well 80, and the P-type substrate 75 is the identified latch-up structure.

[0528] In this embodiment, the second N-type heavily doped region 73 is connected to the power supply pad.

[0529] The second N-type heavily doped region 73 is directly or indirectly connected to the power supply pad. The indirect connection includes being connected through a path capable of transmitting a large current. Specifically, for example, it can be connected through a resistor with a small resistance value, a switching device, or a diode.

[0530] In one embodiment, the step of finding the second N-type heavily doped region 73 that is adjacent to the first P-type heavily doped region 71 and is located within the first N-well 79 includes: taking the first P-type heavily doped region 71 as the center and a preset distance as the radius, identifying the second N-type heavily doped region 73 whose distance to the first P-type heavily doped region 71 is less than the preset distance.

[0531] In one embodiment, as Figure 7c shown, there is a first distance L1 between the second N-type heavily doped region 73 and the first P-type heavily doped region 71, a second distance L2 between the first P-type heavily doped region 71 and the first N-type heavily doped region 72, and a third distance L3 between the first N-type heavily doped region 72 and the second P-type heavily doped region 74.

[0532] Taking the first N-type heavily doped region 72 as the center and a preset distance as the radius, identifying the first P-type heavily doped region 71 and the second P-type heavily doped region 74 whose distances to the first N-type heavily doped region 72 are less than the preset distance specifically includes: both the second distance and the third distance are less than the preset distance.

[0533] Furthermore, as Figure 7d and Figure 7e shown, the P-well 76, the first deep N-well 77, and the P-type substrate 75 form a first parasitic PNP transistor T1. The first deep N-well 77, the P-type substrate 75, and the second deep N-well 78 form a first parasitic NPN transistor T2.

[0534] The first deep N-well 77 has a first parasitic resistance R DNW , and the first end of the first parasitic resistance R DNW is connected to the second N-type heavily doped region 73, and the second end of the first parasitic resistance R DNW is connected to the base of the first parasitic PNP transistor T1.

[0535] The P-type substrate 75 has a second parasitic resistance R PW , and the first end of the second parasitic resistance R PW is connected to the second P-type heavily doped region 74, and the second end of the second parasitic resistance R PW is connected to the base of the first parasitic NPN transistor T2 and the collector of the first parasitic PNP transistor T1.

[0536] The principle of the generation of the latch-up effect is described below: Specifically, T1 is a vertical PNP transistor, the base is the N-well, and the gain from the base to the collector can reach several hundred times. T2 is a lateral NPN transistor, the base is the P-type substrate, and the gain to the collector can reach dozens of times. R DNW is the parasitic resistance of the first deep N-well, and R PW is the parasitic resistance of the P-type substrate.

[0537] The above four elements T1, T2, R DNW and R PW constitute a thyristor circuit. When there is no external interference and no triggering occurs, the two transistors are in the cut-off state, and the collector current is composed of the reverse leakage current of C-B, and the current gain is very small. At this time, the latch-up effect will not occur. When the collector current of one of the transistors suddenly increases to a certain value due to external interference, it will feedback to the other transistor, so that the two transistors are turned on due to triggering (usually the PNP is easier to trigger). A low-resistance path is formed between the power supply pad VDD and the ground pad VSS. After that, even if the external interference disappears, due to the positive feedback formed between the two transistors, there will still be leakage between the power supply pad VDD and the ground pad VSS, that is, the locked state. The latch-up effect is generated therefrom.

[0538] As described above, it is only the preferred embodiment of the present invention, and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for identifying a latch structure, characterized in that, The method includes: In the chip layout, find the first P-type heavily doped region that is connected to the first input / output pad and is located within the P-well; Find the first N-type heavily doped region located within the P-type substrate and the second N-type heavily doped region located within the N-well that are adjacent to the first P-type heavily doped region; Find the second P-type heavily doped region located within the P-type substrate that is adjacent to the first N-type heavily doped region; wherein, the P-well is located within the deep N-well, the deep N-well is located within the N-well, and the N-well is located on the P-type substrate; The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the N-well, and the P-type substrate is the identified latch-up structure; or, In the chip layout, find the first N-type heavily doped region that is connected to the first input / output pad and is located within the P-type substrate; Find the first P-type heavily doped region located within the P-well and the second P-type heavily doped region located within the P-type substrate that are adjacent to the first N-type heavily doped region; Find the second N-type heavily doped region located within the N-well that is adjacent to the first P-type heavily doped region; wherein, the P-well is located within the deep N-well, the deep N-well is located within the N-well, and the N-well is located on the P-type substrate; The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the N-well, and the P-type substrate is the identified latch-up structure.

2. The method according to claim 1, wherein The step of finding the first N-type heavily doped region located within the P-type substrate and the second N-type heavily doped region located within the N-well that are adjacent to the first P-type heavily doped region; includes: Centering on the first P-type heavily doped region and with a preset distance as the radius, identify the first N-type heavily doped region and the second N-type heavily doped region whose distances to the first P-type heavily doped region are less than the preset distance; The step of finding the first P-type heavily doped region located within the P-well and the second P-type heavily doped region located within the P-type substrate that are adjacent to the first N-type heavily doped region; includes: Centering on the first N-type heavily doped region and with a preset distance as the radius, identify the first P-type heavily doped region and the second P-type heavily doped region whose distances to the first N-type heavily doped region are less than the preset distance.

3. The method according to claim 1 or 2, wherein The step of finding the first P-type heavily doped region that is connected to the first input / output pad and is located within the P-well; includes: Find the first P-type heavily doped region that is directly or indirectly connected to the first input / output pad and is located within the P-well; The step of finding the first N-type heavily doped region that is connected to the first input / output pad and is located within the P-type substrate; includes: Find the first N-type heavily doped region that is directly or indirectly connected to the first input / output pad and is located within the P-type substrate.

4. A method for identifying a latch structure, characterized in that, The method includes: In the chip layout, find the first P-type heavily doped region that is connected to the first input / output pad and is located within the P-well; Find the first N-type heavily doped region adjacent to the first P-type heavily doped region and located in the second N-well, and the second N-type heavily doped region located in the first N-well; Find the second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the P-type substrate; wherein, the P-well is located in the deep N-well, the deep N-well is located in the first N-well, and both the first N-well and the second N-well are located on the P-type substrate; The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure; or, In the chip layout, find the first N-type heavily doped region connected to the first input / output pad and located in the second N-well; Find the first P-type heavily doped region adjacent to the first N-type heavily doped region and located in the P-well, and the second P-type heavily doped region located in the P-type substrate; Find the second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the first N-well; wherein, the P-well is located in the deep N-well, the deep N-well is located in the first N-well, and both the first N-well and the second N-well are located on the P-type substrate; The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure.

5. The method according to claim 4, wherein, The step of finding the first N-type heavily doped region adjacent to the first P-type heavily doped region and located in the second N-well, and the second N-type heavily doped region located in the first N-well; includes: Taking the first P-type heavily doped region as the center and a preset distance as the radius, identify the first N-type heavily doped region and the second N-type heavily doped region whose distances to the first P-type heavily doped region are less than the preset distance; The step of finding the first P-type heavily doped region adjacent to the first N-type heavily doped region and located in the P-well, and the second P-type heavily doped region located in the P-type substrate; includes: Taking the first N-type heavily doped region as the center and a preset distance as the radius, identify the first P-type heavily doped region and the second P-type heavily doped region whose distances to the first N-type heavily doped region are less than the preset distance.

6. The method according to claim 4 or 5, wherein, The step of finding the first P-type heavily doped region connected to the first input / output pad and located in the P-well; includes: Find the first P-type heavily doped region directly or indirectly connected to the first input / output pad and located in the P-well; The step of finding the first N-type heavily doped region connected to the first input / output pad and located in the second N-well; includes: Find the first N-type heavily doped region directly or indirectly connected to the first input / output pad and located in the second N-well.

7. A method for identifying a latch structure, characterized in that The method includes: In the chip layout, find the first P-type heavily doped region connected to the first input / output pad and located in the P-well; Find a first N-type heavily doped region adjacent to the first P-type heavily doped region and located within the second deep N-well, and a second N-type heavily doped region located within the first N-well; Find a second P-type heavily doped region adjacent to the first N-type heavily doped region and located within the P-type substrate; wherein, the P-well is located within the first deep N-well, the first deep N-well is located within the first N-well, the second deep N-well is located within the second N-well, and both the first N-well and the second N-well are located on the P-type substrate; The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the first deep N-well, the second deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure; or, In the chip layout, find a first N-type heavily doped region connected to the first input / output pad and located within the second deep N-well; Find a first P-type heavily doped region adjacent to the first N-type heavily doped region and located within the P-well, and a second P-type heavily doped region located within the P-type substrate; Find a second N-type heavily doped region adjacent to the first P-type heavily doped region and located within the first N-well; wherein, the P-well is located within the first deep N-well, the first deep N-well is located within the first N-well, the second deep N-well is located within the second N-well, and both the first N-well and the second N-well are located on the P-type substrate; The region formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the P-well, the first deep N-well, the second deep N-well, the first N-well, the second N-well, and the P-type substrate is the identified latch structure.

8. The method according to claim 7, wherein, The finding of the first N-type heavily doped region adjacent to the first P-type heavily doped region and located within the second deep N-well, and the second N-type heavily doped region located within the first N-well; includes: Centering on the first P-type heavily doped region and with a preset distance as the radius, identify a first N-type heavily doped region and a second N-type heavily doped region whose distances to the first P-type heavily doped region are less than the preset distance; The finding of the first P-type heavily doped region adjacent to the first N-type heavily doped region and located within the P-well, and the second P-type heavily doped region located within the P-type substrate; includes: Centering on the first N-type heavily doped region and with a preset distance as the radius, identify a first P-type heavily doped region and a second P-type heavily doped region whose distances to the first N-type heavily doped region are less than the preset distance.

9. The method according to claim 7 or 8, wherein, The finding of the first P-type heavily doped region connected to the first input / output pad and located within the P-well; includes: Find a first P-type heavily doped region directly or indirectly connected to the first input / output pad and located within the P-well; The finding of the first N-type heavily doped region connected to the first input / output pad and located within the second N-well; includes: Find a first N-type heavily doped region that is directly or indirectly connected to the first input / output pad and is located within the second N-well.

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