A method for increasing air gap by using etch-back process

Abstract

The present invention discloses a method for increasing an air gap by utilizing an etch-back process, which can effectively increase the volume of the air gap and reduce the parasitic capacitance value. A semiconductor device includes a substrate, an interlayer dielectric layer, and a first photomask, which are sequentially distributed from bottom to top. The method includes: selecting an air gap region, opening a diffusion barrier in the selected air gap region, etching the interlayer dielectric layer where the air gap is to be generated to form an air gap cavity, removing the first photomask, depositing a conformal dielectric barrier layer, filling the air gap cavity with a first filler, etching back the first filler, stacking a second filler in a first etched groove, and making the second filler cover the upper surface of the conformal dielectric barrier layer and the diffusion barrier, covering the upper surface of the second filler with a second photomask, etching the second filler in the first etched region to form a second etched groove, removing the second photomask, etching the first filler in the air gap cavity, and depositing a non-conformal dielectric in the second etched groove to form an air gap.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, in particular to a method for increasing an air gap by utilizing an etch-back process. Background Art

[0002] When charges are forced to move in an electric field, the dielectric in a conductor or semiconductor hinders this movement, causing the charges to accumulate and be stored. The amount of stored charge is the capacitance value. In the integrated circuit manufacturing process, to reduce the feedback voltage generated by transistors or improve the filtering effect of filters, the capacitance value of parasitic capacitance must be reduced. Currently, the method for reducing capacitance value is to reduce the K value (i.e., dielectric constant) of the dielectric. Changing the dielectric constant is mainly achieved by changing the chemical composition of the dielectric or by introducing porosity into the semiconductor.

[0003] However, the lower the K value of the dielectric material, the higher the production cost. Introducing porosity in semiconductors is relatively inexpensive. Introducing porosity, or creating an air gap, creates empty space within the semiconductor, improving the insulation between components within the semiconductor. This method of introducing porosity was introduced by IBM in 2007. It primarily utilizes the low dielectric constant of air to reduce parasitic capacitance. The dielectric constant is related to the volume of the air gap; the larger the air gap volume, the lower the dielectric constant, which helps reduce parasitic capacitance. However, current manufacturing processes limit further increases in the air gap volume, making it impossible to meet the low parasitic capacitance requirements of integrated circuits. Summary of the Invention

[0004] In view of the above problems in the prior art, the present invention provides a method for increasing the air gap by utilizing an etch-back process, which can effectively increase the volume of the air gap and reduce the parasitic capacitance value.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A method for increasing an air gap by using an etch-back process, the method being used to form an air gap in a dielectric layer of a semiconductor device, the semiconductor device comprising a substrate, an interlayer dielectric layer, a first barrier layer, and a plurality of metal layers spaced apart within the substrate, wherein a barrier layer is disposed around the periphery of the metal layers. The method comprises: S1, selecting an air gap region, the air gap region comprising at least two air gaps to be formed, the air gap to be formed being a region between two adjacent metal layers;

[0007] S2, disposing a first photomask on the upper surface of the first barrier layer;

[0008] S3, etching the first barrier layer and the interlayer dielectric layer where the air gap is to be formed in sequence to form an air gap cavity;

[0009] S4, after removing the first photomask above the first barrier layer, depositing a conformal dielectric barrier layer on the upper surface of the first barrier layer, the exposed surface of the barrier layer, and within the air gap cavity;

[0010] S5, filling the air gap cavity with a first filler, and making the first filler cover the upper surface of the conformal dielectric barrier layer;

[0011] S6, etching back the first filler to remove the first blocking layer and the first filler above the exposed barrier layer, and remove the first filler at the top of the air gap cavity, forming a first etched groove with a certain depth at the upper portion of the air gap cavity;

[0012] S7, stacking a second filler in the first etched groove, and making the second filler cover the upper surface of the first filler and the conformal dielectric barrier layer;

[0013] S8. Covering the upper surface of the second filler with a second photomask, wherein the second photomask is provided with a pattern of a certain width, the pattern corresponding to the first etched region and having a width consistent with the width of the first etched region, the pattern width being greater than the maximum width of a single barrier layer and less than the sum of the width of the single barrier layer and the width of the air gap;

[0014] S9, etching the second filler in the first etching area to form a second etching groove;

[0015] S10, after removing the second photomask, etching the first filler in the air gap cavity;

[0016] S11. Growing a non-conformal dielectric in the first etched region, and forming an air gap in the air gap cavity below the non-conformal dielectric.

[0017] It is further characterized in that

[0018] The semiconductor device is an FDSOI transistor;

[0019] The gate line width of the FDSOI transistor is 4nm to 12nm;

[0020] In step S1, the air gaps to be generated are evenly spaced and distributed in the interlayer dielectric layer between the metal layers;

[0021] In step S2, the material of the metal layer is copper, and the material of the barrier layer is tantalum or tantalum nitride (ie, TaN);

[0022] In step S3, a dry etching process is used to etch the interlayer dielectric layer where the air gap is to be formed, and the gas used for the dry etching includes but is not limited to at least one of nitrogen, hydrogen, and ammonia;

[0023] In step S4, a conformal dielectric barrier layer is deposited by an atomic layer deposition process, wherein the conformal dielectric barrier layer is made of a carbon-containing silicon oxide film (i.e., SiOCH film) or silicon carbon nitride (i.e., SiCN);

[0024] In step S5 , the material of the first filler is an organic bottom anti-reflective coating (BARC) or amorphous carbon / amorphous carbon (APF);

[0025] In step S6, the first filler is etched by dry etching. The depth of the first etched groove is the vertical distance from the top of the first filler to the top of the barrier layer after etching.

[0026] In step S7, the material of the second filler is the same as that of the interlayer dielectric layer, and the second filler is an oxide dielectric material;

[0027] In step S9, the first filler in the air gap cavity is etched using a dry etching process;

[0028] In step S10, the second filler in the first etching area is etched using a photolithography etching process;

[0029] In step S11 , the material of the non-conformal dielectric is the same as that of the second filler and the interlayer dielectric layer.

[0030] The above-described structure of the present invention can achieve the following beneficial effects: This method forms an air gap by filling the air gap cavity with a first filler, etching back the first filler, filling the second filler in a second etched groove, sequentially etching the second filler and the first filler, and then growing a non-conformal dielectric (i.e., the second filler) into the second etched groove. During the air gap formation process, a first etched region is obtained by etching through a photolithography process, and the width of the first etched region is limited by the width of the photoresist pattern in the photolithography process, so that the width of the first etched region is greater than the maximum width of a single barrier layer and less than the sum of the width of the single barrier layer and the width of the air gap, thereby obtaining a first etched region with a smaller opening (smaller size). This first etched region is a backfill region for growing a non-conformal dielectric (i.e., backfilling the second filler), and the width of the backfilled second filler is limited by the width of the first etched region. While maintaining the thickness of the non-conformal dielectric, the reduction in the width of the backfill region reduces the size of the subsequent non-conformal dielectric layer used to form the void. This not only reduces the backfill time of the second filler and increases the speed of void formation, but also prevents the problem of non-conformal dielectric growing at the bottom of the air gap cavity due to an overly large opening, thereby reducing the volume of the void. The process method of this application effectively increases the volume of the resulting air gap, meeting the low parasitic capacitance requirements of integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of an air gap structure formed using an existing process;

[0032] Figure 2 It is a scatter plot of the parasitic capacitance value changing with the volume of the air gap structure (i.e., the void volume) and the depth of dielectric damage;

[0033] Figure 3 Schematic diagram of the structure of the air gap to be generated by using the existing process or steps S1 and S2 of the present invention;

[0034] Figure 4 This is a schematic diagram of the structure of forming an air gap cavity using the existing process and step S3 of the present invention;

[0035] Figure 5 This is a schematic diagram of the structure after removing the first photomask and depositing the conformal dielectric barrier layer using the existing process and step S4 of the present invention;

[0036] Figure 6 6a is a schematic diagram of the structure after the air gap is formed using the existing process. Figure 6 6b is an enlarged actual effect diagram after the air gap is formed by the existing process;

[0037] Figure 7 Schematic diagram of the structure after the air gap cavity is filled with the first filler in step S5 of the present invention;

[0038] Figure 8 This is a schematic diagram of the structure after etching the first filler in step S6 of the present invention to form a first etched groove;

[0039] Figure 9 A schematic structural diagram of covering the upper surface of the second filler with a second photomask in step S8 of the present invention;

[0040] Figure 10 This is a schematic structural diagram after the second etching groove is formed by step S9 of the present invention;

[0041] Figure 11 This is a schematic diagram of the structure after the first filler is etched in step S10 of the present invention;

[0042] Figure 12 Schematic diagram of the structure in which a void is formed after depositing a non-conformal dielectric in step S11 of the present invention;

[0043] Figure 13 4 is a process flow chart of the method of the present invention. DETAILED DESCRIPTION

[0044] Different embodiments or examples are provided below to implement different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0045] Figure 1 Several schematic diagrams of air gap structures formed using existing processes are provided. Figure 1 In Figures a, b, and c, the air gap depths are 54 nm, 65 nm, and 84 nm, respectively, and the maximum widths are all 18.5 nm. Based on the depths and maximum widths, the standardized void volumes of the air gaps in Figures a, b, and c are 1 nm, respectively. 3 , 1.4nm 3 , 2nm 3 , establish the relationship between these standardized gap volume parameters and parasitic capacitance values scatter plot, see Figure 2 2a in Figure 2a, scatter plot of the relationship between low dielectric damage depth and parasitic capacitance value, see Figure 2 2b in the Figure 2 From the scattered point distribution of 2a, we can see that the void volume increases and the parasitic capacitance decreases. Figure 2 As can be seen from Figure 2b, the damage depth of the low-dielectric dielectric increases and the parasitic capacitance value decreases. Therefore, the damage depth of the low-dielectric dielectric and the void volume are highly correlated with the parasitic capacitance value, and the increase in the void volume is conducive to the reduction of the parasitic capacitance value.

[0046] Figures 3 to 6 A structural diagram for fabricating an air gap using an existing process is provided. First, a semiconductor device is provided, comprising, arranged from bottom to top, a substrate 1, an interlayer dielectric layer 2, a first barrier layer 9, and metal layers 6 spaced apart in the interlayer dielectric layer, wherein the metal layers 6 are copper. An air gap 5 is fabricated in the interlayer dielectric layer 2. The air gap fabrication process comprises: A1, selecting an air gap region, which is the region between two adjacent metal layers and includes at least two air gaps to be formed; A2, disposing a first mask 4 on the surface of the first barrier layer, the first mask 4 covering the upper surface of the first barrier layer, and having an etched pattern for light transmission therein, the etched pattern corresponding to the air gap region to be etched and the upper portion of the barrier layer, as shown in FIG. Figure 3 A3, sequentially etching the first barrier layer above the barrier layer, the interlayer dielectric layer to be generated air gap 7, forming an air gap cavity 8; A4, removing the first mask above the first barrier layer 2 that is not etched, see Figure 4A conformal dielectric barrier layer 16 is deposited on the upper surface of the first barrier layer, within the etching cavity 8 and on both sides of the exposed barrier layer surface, see Figure 5 A5, a non-conformal dielectric 10 is grown on the bottom of the air gap cavity 8, above the first barrier layer 9, and above the conformal dielectric barrier layer 16 to form a gap 5. The final gap structure is shown in FIG. Figure 6 The non-conformal dielectric 10 is mainly formed by a thin film machine and a chemical vapor deposition method. During the chemical vapor deposition process, not only the non-conformal dielectric 10 is grown on the upper part (see Figure 6 In the middle region N), the gas enters the bottom of the gap cavity 8 and is deposited at the bottom of the gap cavity 8 to form a non-conformal dielectric 10, as shown in FIG. Figure 6 In the region M, the volume of the gap is small and cannot meet the low parasitic capacitance value requirement of the integrated circuit.

[0047] In response to the technical problem that the void volume in the prior art is small and cannot meet the low parasitic capacitance value requirements of integrated circuits, the following provides a specific embodiment of an etching and etching back process method for increasing the void volume. The method is used to produce a dielectric layer in a semiconductor device, forming a larger air gap 5 in the dielectric layer to reduce the parasitic capacitance value of the semiconductor device. The semiconductor device includes a substrate 1, an interlayer dielectric layer 2, a first barrier layer 9, and a metal layer 6 spaced apart in the interlayer dielectric layer, and a barrier layer 60 wrapped around the metal layer 6. The metal layer is copper, the material of the substrate 1 is silicon carbon nitride (SiCN), the material of the interlayer dielectric layer is a low dielectric constant material (LK), such as silicon dioxide, SiLK, etc., and the material of the first barrier layer 9 is silicon oxynitride (SiON).

[0048] See Figure 13 The specific steps of the etching and etching back process method include: S1, selecting an air gap area, the air gap area is located between two adjacent metal layers 5, and in this embodiment, the air gap area includes two air gaps 7 to be generated, and each air gap 7 to be generated is evenly spaced and distributed in the interlayer dielectric layer 2.

[0049] S2. A first photomask 4 is provided on the surface of the first barrier layer 9. The first photomask 4 covers the upper surface of the first barrier layer 9, and an etching pattern (photoresist pattern) for light transmission is provided in the first photomask 4. The etching pattern corresponds to the air gap area to be etched and the barrier layer area between the air gap areas. Figure 3In this embodiment, the barrier layer 60 is tantalum (Ta) or tantalum nitride (TaN) and is used to prevent diffusion. Since copper ions are highly mobile and active, the barrier layer 60 can prevent the copper ions from dispersing and diffusing to other areas. The thinner the barrier layer and the more uniform the coating, the more effective it is in blocking copper ions. The barrier layer does not react with the surrounding materials, so the surrounding materials will not diffuse into the metal layer and will not corrode the metal layer protected by the barrier layer. The barrier layer can protect the integrity of the internal copper wires from being affected by surrounding interlayer dielectric layers, silicon carbon nitride substrates, silicon oxynitride, and other materials, thereby extending the life of semiconductor devices and preventing electrical performance from being affected.

[0050] S3, firstly, the first barrier layer corresponding to the etching pattern is etched by a photolithography process, and then the interlayer dielectric layer where the air gap is to be generated is etched by a dry etching process to form an air gap cavity 8, as shown in FIG. Figure 4 The gases used in dry etching include one or more of nitrogen, hydrogen, and ammonia.

[0051] S4, after removing the first mask 4 above the interlayer dielectric layer 2, a conformal dielectric barrier layer 16 is deposited on the upper surface of the first barrier layer, in the etching cavity 8, and on the exposed barrier layer surfaces on both sides. Figure 5 Specifically, first, the semiconductor device after the processing in step S3 is placed in a photoresist stripper for photoresist removal, and then the anti-reflective layer is cleaned by wet cleaning to achieve the first mask removal. Then, a conformal dielectric barrier layer 16 is deposited on the upper surface of the etched first barrier layer, in the air gap cavity 8, and on the upper surface edges of the diffusion barriers on both sides. The conformal dielectric barrier layer is deposited by an atomic layer deposition process. In this embodiment, the conformal dielectric barrier layer is made of SiOCH film.

[0052] S5, filling the air gap cavity 8 with a first filler 11, and making the first filler 11 cover the upper surface of the conformal dielectric barrier layer 16, Figure 7 In this embodiment, the first filler is made of an organic bottom anti-reflective coating (BARC) or amorphous carbon (APF). The deposition of the first filler protects the interior of the air gap 8 to prevent other materials (such as the second filler) from growing in the air gap 8 during subsequent processes, which would result in a reduction in the volume of the resulting air gap.

[0053] S6, using dry etching to etch back the first filler 11, remove the first filler 11 above the unetched first barrier layer 9, and remove the first filler 11 at the top of the air gap cavity 8, forming a first etched groove 12 with a certain depth at the upper part of the air gap cavity 8, Figure 8The depth of the first etched groove 12 is the vertical distance from the top of the first filler 11 to the top of the barrier layer 60 on both sides after etching. In this embodiment, the depth of the first etched groove 12 is 1000 angstroms. The provision of the first etched groove 12 facilitates the subsequent filling of the second filler.

[0054] S7. Stack a second filler 13 in the first etched groove 12, and make the second filler 13 cover the exposed conformal dielectric barrier layer 16 and the upper surface of the unetched first barrier layer 9. The material of the second filler 13 is the same as that of the interlayer dielectric layer 2. The second filler is an oxide dielectric material. In this embodiment, the oxide dielectric material is a low dielectric material LK.

[0055] S8, the second mask 14 is covered on the upper surface of the second filler 13, and a pattern of a certain width is set on the second mask 14. Figure 9 The pattern corresponds to the first etched area and the pattern width is consistent with the width of the first etched area. The pattern width is greater than the maximum width of a single barrier layer and less than the sum of the barrier layer width and the air gap width.

[0056] S9, etching the second filler 13 in the first etching area by a photolithography process to form a second etching groove 15, wherein the width a of the second etching groove 15 is greater than the maximum width b of a single barrier layer and less than the sum of the barrier layer width b and the air gap width c, that is, a<b+c, see Figure 10 .

[0057] S10, after removing the second photomask 14, the first filler in the air gap cavity is etched by dry etching process, Figure 11 The cleaning method of the second photomask is the same as that of the first photomask. The gas used in dry etching includes oxygen (O2) or carbon dioxide (CO2).

[0058] S11, using chemical vapor deposition process to grow non-conformal dielectric 10 in the second etched groove (ie, backfill the second filler) to form an air gap, see Figure 12 The material of the non-conformal dielectric is the same as that of the second filler and the interlayer dielectric layer. In this embodiment, the materials of the non-conformal dielectric 10 and the second filler are both low-dielectric constant materials. Backfilling the second filler means that the non-conformal dielectric on both sides of the first etched area grows in three directions: upward, left, and right. The conformal dielectric growing to the left and right combines in the area close to the axis of the first etched area to fill the opening area formed in the first etched area, thereby covering the opening above the air gap cavity and forming an air gap between the two connected shielding layers below the conformal dielectric.

[0059] The above method is applied to the process of semiconductor devices, the semiconductor devices are FDSOI transistors but not limited to FDSOI transistors, and the gate line width of the FDSOI transistor is 4nm to 12nm. The air gap structure obtained by the method of the present invention is as follows Figure 12 As shown, the air gap structure obtained by the existing process method is as follows Figure 6 As shown, from Figure 6 、 Figure 12 It can be seen that the maximum width of the air gap is the same in both cases, but the obtained air gap depth is different. Figure 6 In the FDSOI transistor, not only a non-conformal dielectric layer is grown on the top of the gap (see Figure 6 In the region N in FIG, and because the opening is large, a non-conformal dielectric layer will also grow at the bottom (see FIG. Figure 6 In the region M), only the upper non-conformal dielectric layer is grown in this application, see Figure 12 Therefore, under the condition that the volume of the air gap cavity remains unchanged, the air gap volume calculated according to the maximum width and depth of the air gap is different. Figure 12 It can be seen that the air gap volume obtained by the method of the present application is significantly increased. Since the low dielectric damage depth and the gap volume are highly correlated with the parasitic capacitance value, the air gap structure obtained by the method of the present application can significantly reduce the parasitic capacitance value.

[0060] The reason why a larger air gap can be obtained by using the process of the present application is that the second etching groove 15 formed in the first etching area is the backfill area A. Figure 10 , used to grow non-conformal dielectrics (i.e., backfill the second filler), while the region used to grow non-conformal dielectrics in the prior art is shown in FIG. Figure 5 In area B, Figure 10 Region A in Figure 5 Compared with the region B in FIG, it can be seen that the width of region A in the present application is significantly smaller than that of region B. Under the condition that the thickness and total width of the non-conformal dielectric remain unchanged, the reduction in the width of the backfill region in the present application reduces the size of the non-conformal dielectric layer subsequently grown for void formation. Figure 12 This not only reduces the backfilling time of the second filler and increases the speed of void formation, but also prevents the problem of non-conformal dielectric growing at the bottom of the air gap cavity due to the opening being too large, thereby reducing the volume of the void.

[0061] The method of the present invention effectively increases the volume of the air gap in the interlayer dielectric layer through steps S1 to S11: filling the air gap cavity with a first filler, etching back the first filler, filling the second etched groove with a second filler, etching the second filler and the first filler in sequence, and then backfilling the second etched groove with the second filler. That is, without changing the existing basic process and architecture (that is, steps S1 to S4 are the same as steps A1 to A4), the air gap volume is increased, it is easy to implement, and has scalability at different process points. That is, the method of the present invention is applicable to all dielectric layer etching processes and is also applicable to FDSOI devices with gate line widths of 7nm to 90nm. The method of the present application is applied to the production of FDSOI devices, and the produced FDSOI devices are applied to the dielectric connection of DRAM memory and the deep channel connection line of NAND memory. The increase in the volume of the air gap in the interlayer dielectric layer effectively reduces the parasitic capacitance in the integrated circuit.

[0062] The above are only preferred embodiments of the present application, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations directly derived or imagined by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the scope of protection of the present invention.

Claims

1. A method for increasing an air gap by using an etch-back process, the method being used to produce an air gap in a dielectric layer of a semiconductor device, wherein the semiconductor device comprises, arranged from bottom to top, a substrate, an interlayer dielectric layer, a first barrier layer, and a plurality of metal layers spaced apart within the substrate, wherein a barrier layer is disposed around each of the metal layers, wherein: The method comprises: S1, selecting an air gap region, wherein the air gap region comprises at least two air gaps to be generated, and the air gap to be generated is a region between two adjacent metal layers; S2, disposing a first photomask on the upper surface of the first barrier layer; S3, sequentially etching the first barrier layer in the air gap area and the interlayer dielectric layer in the area where the air gap is to be formed to form an air gap cavity; S4, after removing the first photomask above the unetched first barrier layer, depositing a conformal dielectric barrier layer on the upper surface of the unetched first barrier layer, the exposed barrier layer surface, and the air gap cavity; S5, filling the air gap cavity with a first filler, and making the first filler cover the upper surface of the conformal dielectric barrier layer; S6. Etching back the first filler: removing the first blocking layer and the first filler above the exposed barrier layer, and removing the first filler at the top of the air gap cavity, to form a first etched groove with a certain depth at the upper portion of the air gap cavity; S7, stacking a second filler in the first etched groove, and making the second filler cover the upper surface of the first filler and the conformal dielectric barrier layer; S8. Covering the upper surface of the second filler with a second photomask, wherein the second photomask is provided with a pattern of a certain width, the pattern corresponding to the first etched region and having a width consistent with the width of the first etched region, the pattern width being greater than the maximum width of a single barrier layer and less than the sum of the width of the single barrier layer and the width of the air gap; S9, etching the second filler in the first etching area to form a second etching groove; S10, after removing the second photomask, etching the first filler in the air gap cavity; S11. Growing a non-conformal dielectric in the first etched region, and forming an air gap in the air gap cavity below the non-conformal dielectric.

2. The method for increasing the air gap by using an etch-back process according to claim 1, wherein: In step S1 , the air gaps to be generated are evenly spaced and distributed in the interlayer dielectric layer between the metal layers.

3. The method for increasing the air gap by using an etch-back process according to claim 1 or 2, characterized in that: The material of the metal layer is copper, and the material of the barrier layer is tantalum or tantalum nitride.

4. The method for increasing the air gap by using an etch-back process according to claim 3, wherein: In step S3, a dry etching process is used to etch the interlayer dielectric layer where the air gap is to be formed, and the gas used in the dry etching process includes at least one of nitrogen, hydrogen, and ammonia.

5. The method for increasing the air gap by using an etch-back process according to claim 4, wherein: In step S4, the conformal dielectric barrier layer is deposited by atomic layer deposition, and the material of the conformal dielectric barrier layer is SiOCH film or silicon carbon nitride; in step S5, the material of the first filler is amorphous carbon.

6. The method for increasing the air gap by using an etch-back process according to claim 1 or 5, characterized in that: In step S6, the first filler is etched by dry etching, and the depth of the first etched groove is the vertical distance from the top of the first filler to the top of the barrier layer after etching.

7. The method for increasing the air gap by using an etch-back process according to claim 6, wherein: In step S7 , the material of the second filler is the same as the material of the interlayer dielectric layer, and the second filler is an oxide dielectric material.

8. The method for increasing the air gap by using an etch-back process according to claim 7, wherein: In step S9, the first filler in the air gap cavity is etched using a dry etching process.

9. The method for increasing the air gap by using an etch-back process according to claim 8, wherein: In step S10, the second filler in the first etching area is etched using a photolithography process.

10. The method for increasing the air gap by using an etch-back process according to claim 9, wherein: In step S11 , the material of the non-conformal dielectric is the same as the material of the second filler.

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