Bonded semiconductor structure and method of making the same

Abstract

A bonded semiconductor structure and a method of making the same are disclosed. The bonded semiconductor structure includes a first device wafer and a second device wafer. The first device wafer includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer disposed on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer disposed on the second dielectric layer and bonded to the first bonding layer, and a second bonding pad disposed in the second dielectric layer and through the second bonding layer and at least a portion of the first bonding layer. An electrically conductive bonding interface is included between the first bonding pad and the second bonding pad, and a dielectric bonding interface is included between the first bonding layer and the second bonding layer, wherein a step difference is included between the electrically conductive bonding interface and the dielectric bonding interface.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a bonded semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] 3D IC refers to a technology of converting a traditional two-dimensional chip into a three-dimensional stacked chip by wafer level bonding and through silicon via (TSV) technology. Since 3D IC can effectively utilize space, shorten the distance of circuit transmission, and provide an extremely low resistance connection, it has gradually become a mainstream technology for power converters, low noise amplifiers, radio frequency (RF) or millimeter wave (MMW) elements. However, there are still problems to be improved in the current 3D IC, such as poor bonding quality between bonding pads, which leads to abnormal signal transmission. SUMMARY

[0003] The present application aims to provide a bonded semiconductor structure and a manufacturing method thereof, which mainly utilizes the concave-convex structure design between the bonding pads to ensure the close contact between the two aligned bonding pads, and to reduce the stress on the bonding interface, thereby obtaining improved bonding quality.

[0004] An embodiment of the present application provides a bonded semiconductor structure, comprising a first element wafer and a second element wafer disposed on the first element wafer. The first element wafer comprises a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer disposed on the first dielectric layer. The second element wafer comprises a second dielectric layer, a second bonding layer disposed on the second dielectric layer and bonded with the first bonding layer, and a second bonding pad disposed in the second dielectric layer and passing through the second bonding layer and at least part of the first bonding layer. A conductive bonding interface is included between the first bonding pad and the second bonding pad. A dielectric bonding interface is included between the first bonding layer and the second bonding layer. A step difference is included between the conductive bonding interface and the dielectric bonding interface.

[0005] Another embodiment of the present application provides a method for fabricating a bonded semiconductor structure. First, a first device wafer and a second device wafer are provided, wherein the first device wafer includes a first bonding pad exposed from a first bonding layer, and the second device wafer includes a second bonding pad exposed from a second bonding layer. Then, a portion of the first bonding pad is removed to expose a sidewall of the first bonding layer, and a portion of the second bonding layer is removed to expose a sidewall of the second bonding pad. Next, the first device wafer and the second device wafer are bonded to form a dielectric bonding interface between the first bonding layer and the second bonding layer, and a conductive bonding interface between the first bonding pad and the second bonding pad, wherein the conductive bonding interface and the dielectric bonding interface include a step difference. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figures 1 to 5 A schematic cross-sectional view of a method for fabricating a bonded semiconductor structure according to a first embodiment of the present application;

[0007] Figure 6 A schematic cross-sectional view of a bonded semiconductor structure according to a first embodiment of the present application; Figure 5 A schematic cross-sectional view of a method for fabricating a bonded semiconductor structure according to a first embodiment of the present application;

[0008] Figure 7 A schematic cross-sectional view of a method for fabricating a bonded semiconductor structure according to a second embodiment of the present application;

[0009] Figure 8 A schematic cross-sectional view of a method for fabricating a bonded semiconductor structure according to a third embodiment of the present application;

[0010] Figure 9 A schematic cross-sectional view of a method for fabricating a bonded semiconductor structure according to a fourth embodiment of the present application;

[0011] Figure 10 A schematic cross-sectional view of a method for fabricating a bonded semiconductor structure according to a fifth embodiment of the present application.

[0012] LIST OF ELEMENTS

[0013] 100 first device wafer

[0014] 110 substrate

[0015] 112 semiconductor device

[0016] 114 interconnection layer

[0017] 120 conductive structure

[0018] 121 first bonding structure

[0019] 122 first dielectric layer

[0020] 124 first bonding layer

[0021] 126 first bonding pad

[0022] 130 recess

[0023] 200 second element wafer

[0024] 210 base

[0025] 212 semiconductor element

[0026] 214 interconnect layer

[0027] 220 conductive structure

[0028] 221 second bonding structure

[0029] 222 second dielectric layer

[0030] 224 second bonding layer

[0031] 226 second bonding pad

[0032] 310 dielectric bonding interface

[0033] 320 conductive bonding interface

[0034] 330 gap

[0035] 410 bonded semiconductor structure

[0036] 420 bonded semiconductor structure

[0037] 430 bonded semiconductor structure

[0038] 440 bonded semiconductor structure

[0039] 450 bonded semiconductor structure

[0040] 2260 protrusion

[0041] 2262 step

[0042] 124s sidewall

[0043] 126a top surface

[0044] 226a top surface

[0045] 226s sidewall

[0046] A1 included angle

[0047] D1 depth

[0048] H step difference

[0049] P1 removal fabrication process

[0050] P3 bonding fabrication process

[0051] T1 thickness

[0052] T2 thickness

[0053] T3 thickness

[0054] T4 thickness

[0055] T5 thickness

[0056] W1 width DETAILED DESCRIPTION

[0057] In order to make the above objectives, features and advantages of the present application more comprehensible, specific preferred embodiments along with the accompanying drawings are described below. The accompanying drawings are schematic and not drawn to scale, and the same or similar features are generally designated by the same reference numerals. The embodiments described herein and the accompanying drawings are for reference and illustration only and are not intended to limit the present application. The scope of the present application is defined by the claims. Those of equivalent meaning to the claims of the present application should also be included in the scope of the present application.

[0058] The terms "on", "over", and "above" are to be interpreted in the broadest possible way consistent with the context. Consequently, the term "on" when used without the specification that it is "directly on" is not meant to exclude the presence of interposed features or layers. Similarly, the terms "over" or "above" are not meant to exclude the presence of interposed features or layers, nor are they meant to require that the feature or layer be located "directly over" or "directly above" the feature with which they are in contact.

[0059] To facilitate description, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for describing elements' and features' relationship to one another as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientations depicted in the figures. The elements can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0060] Figures 1 to 5 A cross-sectional view of a method of fabricating a bonded semiconductor structure according to a first embodiment of the present application. Figure 6 A cross-sectional view of a method of fabricating a bonded semiconductor structure according to a first embodiment of the present application. Figure 5 An enlarged view of a portion of the bonded semiconductor structure shown. Please refer to Figure 1The method of fabricating a semiconductor structure includes providing a first device wafer 100 including a substrate 110, an interconnect layer 114 disposed on the substrate 110, and a first bonding structure 121 disposed on the interconnect layer 114. The substrate 110 can be a silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon-germanium substrate, a group III-V semiconductor substrate, or other suitable material. The substrate 110 can include semiconductor devices 112, such as transistors, diodes, capacitors, inductors, resistors, and other active or passive devices, but is not limited thereto. The interconnect layer 114 includes multiple dielectric material layers (not shown) and conductive structures (only conductive structures 120 at the top layer of the interconnect layer 114 are shown for simplicity) formed in the dielectric material layers. The dielectric material layers can include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), nitrogen-doped carbon silicon (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), carbon silicon oxide (SiCOH), spin-on glass, porous low-k dielectric materials, organic polymer dielectric materials, or other suitable dielectric materials. The conductive structures can be made of metal materials such as cobalt (Co), copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable metal materials or metal compounds, but are not limited thereto. According to one embodiment, the conductive structure material can include copper. In some embodiments, the interconnect layer 114 can also include other circuit elements such as capacitors, inductors, resistors, embedded memory, and the like, which are not shown for simplicity.

[0061] The first bonding structure 121 includes a first dielectric layer 122, a first bonding layer 124 on the first dielectric layer 122, and a plurality of first bonding pads 126 through the first bonding layer 124 and the first dielectric layer 122 and in contact with the conductive structure 120. The material of the first dielectric layer 122 can be selected from the dielectric materials applicable to the interconnect layer 114 as described above, which will not be repeated here for the sake of simplicity. According to an embodiment of the present application, the first dielectric layer 122 can include silicon oxide. The first bonding layer 124 includes a dielectric material applicable to wafer bonding with a bonding layer of another die, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), but not limited thereto. According to an embodiment of the present application, the first bonding layer 124 can include silicon carbonitride (SiCN). The first bonding pads 126 can include a metal material applicable to wafer bonding, such as copper (Cu). The fabrication steps of the first bonding structure 121 can include sequentially forming the first dielectric layer 122 and the first bonding layer 124 on the interconnect layer 114, then performing a patterning fabrication process (such as a photolithography and etching fabrication process) to define a plurality of openings in the first dielectric layer 122 and the first bonding layer 124, then forming a metal layer (such as copper) on the first bonding layer 124 and filling the openings, and then performing a removal fabrication process (such as chemical mechanical polishing) to remove the metal layer outside the openings, thereby obtaining the first bonding pads 126 in the openings. In some embodiments, the etching fabrication process of the openings can be controlled to control the shape of the openings, thereby fabricating the first bonding pads 126 with a trapezoidal cross-sectional shape. According to an embodiment of the present application, when the first bonding pads 126 have a thickness Tl, the top surface thereof is substantially flush with the surface of the first bonding layer 124.

[0062] Please refer to Figure 2, the first element wafer 100 is then subjected to a removal fabrication process P1 to remove part of the first bonding pad 126 until a recess 130 exposing the top surface 126a of the first bonding pad 126 and the sidewall 124s of the first bonding layer 124 is obtained. The depth of the recess 130 from the surface of the first bonding layer 124 is D1. The removal fabrication process P1 can include a wet etching fabrication process, a dry etching fabrication process, or a chemical mechanical polishing fabrication process with etching selectivity between the first bonding pad 126 and the first bonding layer 124. According to an embodiment of the present application, the removal fabrication process P1 is a chemical mechanical polishing fabrication process, and can be performed continuously after the chemical mechanical polishing fabrication process for fabricating the first bonding pad 126, or can be performed after the fabrication of the first bonding pad 126 by another chemical mechanical polishing fabrication process with higher removal selectivity for the material of the first bonding pad 126. According to an embodiment of the present application, part of the first bonding layer 124 is also removed during the removal fabrication process P1, so that the inclination angle of the sidewall 124s or the width of the recess 130 after the removal fabrication process P1 can be different from the state before the removal fabrication process P1. As shown in Figure 2 FIG. 14, the included angle A1 between the sidewall 124s of the first bonding layer 124 and the top surface 126a of the first bonding pad 126 can be greater than 90 degrees, and the width W1 of the recess 130 can be slightly greater than the width of the top surface 126a. After the removal fabrication process P1, the first bonding layer 124 has a thickness T4, and the first bonding pad 126 can have a thickness T2.

[0063] Please refer to Figure 3The method of fabricating the semiconductor structure of the present application further includes providing a second element wafer 200 including a substrate 210, an interconnect layer 214 disposed on the substrate 210, and a second bonding structure 221 disposed on the interconnect layer 214. The substrate 210 can include semiconductor elements 212, such as transistors, diodes, capacitors, inductors, resistors, and other active or passive elements, but is not limited thereto. The interconnect layer 214 can include multiple dielectric material layers (not shown) and conductive structures formed in the dielectric material layers (only conductive structures 220 disposed on the top layer of the interconnect layer 214 are shown for simplicity). In some embodiments, the interconnect layer 214 can further include other circuit elements such as capacitors, inductors, resistors, embedded memory, and the like, which are not shown for simplicity. The second bonding structure 221 includes a second dielectric layer 222, a second bonding layer 224 disposed on the second dielectric layer 222, and a plurality of second bonding pads 226 passing through the second bonding layer 224 and the second dielectric layer 222 and contacting the conductive structures 220. The substrate 210, the interconnect layer 214, the conductive structures 220, the second dielectric layer 222, the second bonding layer 224, and the second bonding pads 226 can include materials as described above for the substrate 110, the interconnect layer 114, the conductive structures 120, the first dielectric layer 122, the first bonding layer 124, and the first bonding pads 126, which are not repeated here for simplicity. According to an embodiment of the present application, the conductive structures 220 can include copper (Cu), the second dielectric layer 222 can include silicon oxide, the second bonding layer 224 can include silicon carbon nitride (SiCN), and the second bonding pads 226 can include copper (Cu). According to an embodiment of the present application, the second bonding pads 226 have a thickness T3 such that the top surfaces 226a of the second bonding pads 226 are substantially flush with the surface of the second bonding layer 224. According to an embodiment of the present application, the thickness T3 is greater than the thickness T2.

[0064] Referring to Figure 4 The second element wafer 200 is then subjected to a removal fabrication process P2 to remove portions of the second bonding layer 224 to expose the protruding portions 2260 of the second bonding pads 226. The protruding portions 2260 include top surfaces 226a and sidewalls 226s exposed from the surface of the second bonding layer 224. The removal fabrication process P2 can include a wet etching fabrication process, a dry etching fabrication process, or a chemical mechanical polishing fabrication process having etching selectivity between the second bonding pads 226 and the second bonding layer 224. According to an embodiment of the present application, the removal fabrication process P2 includes a wet etching fabrication process, such as using phosphoric acid (H3PO4) to remove portions of the second bonding layer 224 when the second bonding layer 224 includes silicon carbon nitride (SiCN). After the removal fabrication process P2, the second bonding layer 224 can have a thickness T5. According to an embodiment of the present application, the thickness T5 is less than the thickness T4.

[0065] Referring toFigure 5 and Figure 6 Next, bonding fabrication process P3 is performed, including an alignment step to configure the first component wafer 100 and the second component wafer 200 such that the second bonding layer 224 faces and contacts the first bonding layer 124, and each protrusion 2260 is aligned to be placed in the recess 130. Then, an annealing step is performed to promote bonding between the first bonding layer 124 and the second bonding layer 224, and between the first bonding pad 126 and the second bonding pad 226, to obtain the bonding semiconductor structure 410 of the first embodiment of the present invention. In some embodiments, before bonding fabrication process P3, the first bonding layer 124 and the second bonding layer 224 may undergo surface treatment to remove impurities and / or modify the surface to improve bonding. The temperature of the annealing step may be between 100°C and 400°C.

[0066] like Figure 6 As shown, the present invention comprises a first element wafer 100 and a second element wafer 200 disposed on the first element wafer 100. The first element wafer 100 includes a first dielectric layer 122, a first bonding pad 126 disposed in the first dielectric layer 122, and a first bonding layer 124 disposed on the first dielectric layer 122. The second element wafer 200 includes a second dielectric layer 222, a second bonding layer 224 disposed on the second dielectric layer 222 and bonded to the first bonding layer 124, and a second bonding pad 226 disposed in the second dielectric layer 222, passing through the second bonding layer 224 and the first bonding layer 124, and bonded to the first bonding pad 126. A dielectric bonding interface 310 is provided between the first bonding layer 124 and the second bonding layer 224, and a conductive bonding interface 320 is provided between the top surface 126a of the first bonding pad 126 and the top surface 226a of the second bonding pad 226.

[0067] It is worth noting that the present invention uses a protrusion 2260 and a recess 130 to join the first element wafer 100 and the second element wafer 200. Therefore, a step difference H will be included between the conductive bonding interface 320 and the dielectric bonding interface 310. The step difference H and the recess 130 (see reference) Figure 2 The depth D1 of the recess 130 is related to the thickness T4 of the first bonding layer 124. In this embodiment, when the depth D1 of the recess 130 is approximately equal to the thickness T4 of the first bonding layer 124, the step difference H will be approximately equal to the thickness T4 of the first bonding layer 124. According to an embodiment of the present invention, the width W1 of the recess 130 can be controlled so that after the bonding manufacturing process P3, the sidewall 124s of the first bonding layer 124 is in direct contact with the sidewall of the second bonding pad 226 (i.e., the sidewall 226s of the protrusion 2260).

[0068] The following description will focus on different embodiments of the present invention. For simplicity, the description will primarily focus on the differences between the embodiments, without repeating the similarities. Identical elements in each embodiment are designated with the same reference numerals to facilitate comparison between embodiments.

[0069] Figure 7 This is a schematic cross-sectional view of the bonding semiconductor structure 420 according to a second embodiment of the present invention. In this embodiment, the width W1 of the recess 130 (refer to...) Figure 2 The protrusion 2260 of the second mating pad 226 may be larger than the protrusion 2260 of the second mating pad 226 (see reference). Figure 2 The width of the protrusion 2260 provides space for thermal expansion during the tempering step of the bonding fabrication process P3, thus allowing a stepped portion 2262 to be formed on the portion of the second bonding pad 226 adjacent to the dielectric bonding interface 310. The stepped portion 2262 helps to secure the bonding between the first component wafer 100 and the second component wafer 200. This embodiment also reduces the risk of short circuits with other bonding pads caused by the extrusion of the protrusion 2260 after thermal expansion, and provides a larger bonding pad alignment margin and buffers stress at the bonding interface. In some embodiments, the first dielectric layer 122 near the top surface 126a of the first bonding pad 126 extends from the recess 130 (see reference). Figure 2 When exposed, after bonding the first component wafer 100 and the second component wafer 200, the second bonding pad 226 can contact the first dielectric layer 122.

[0070] Figure 8 This is a schematic cross-sectional view of a bonding semiconductor structure 430 according to a third embodiment of the present invention. In this embodiment, the width W1 of the recess 130 (refer to...) Figure 2 The protrusion 2260 of the second mating pad 226 can be larger than that of the second mating pad 226 (see reference). Figure 2 The width of the protrusion 2260 is such that it will not fill the recess 130 after thermal expansion, thus forming a gap 330 between the sidewall 226s of the protrusion 2260 and the sidewall 124s of the first bonding layer 124. The gap 330 can provide more stress buffering for the bonding interface between the first element wafer 100 and the second element wafer 200.

[0071] Figure 9 and Figure 10 These are schematic cross-sectional views of the bonding semiconductor structure 440 according to the fourth embodiment and the bonding semiconductor structure 450 according to the fifth embodiment of the present invention, respectively. Figure 9 As shown, the depth D1 of the recess 130 can be adjusted by removing the manufacturing process P1 (refer to...). Figure 2) greater than the thickness T4 of the first bonding layer 124, so the second bonding pad 226 will pass through the entire thickness of the first bonding layer 124, and the step difference H between the conductive bonding interface 320 and the dielectric bonding interface 310 will be greater than the thickness T4 of the first bonding layer 124. As shown in FIG. 1 1, when the depth Dl of the recess 130 (refer to FIG. 1 1 ) can be less than the thickness T4 of the first bonding layer 124, so the second bonding pad 226 will only pass through part of the thickness of the first bonding layer 124, and the step difference H between the conductive bonding interface 320 and the dielectric bonding interface 310 will be less than the thickness T4 of the first bonding layer 124. Figure 10 Figure 2

[0072] The present application makes recesses and protrusions on the first and second element wafers respectively, and then aligns each protrusion with a recess to bond the first and second element wafers, thereby improving the problem of poor contact of the bonding pads due to the uneven surface of the interconnection layer and / or the recess of the surface of the bonding pad, and obtaining improved bonding quality.

[0073] The above description is only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall be within the scope of the present application.​​

Claims

1. A bonded semiconductor structure, comprising: a first die including: a first dielectric layer; a first bonding pad disposed in the first dielectric layer; and a first bonding layer disposed on the first dielectric layer; and a second die disposed on the first die and including: a second dielectric layer; a second bonding layer disposed on the second dielectric layer and bonded to the first bonding layer; and a second bonding pad disposed in the second dielectric layer, through the second bonding layer and at least part of the first bonding layer, and bonded to the first bonding pad, wherein an electrically conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step difference.

2. The bonded semiconductor structure of claim 1, wherein the step difference is equal to a thickness of the first bonding layer.

3. The bonded semiconductor structure of claim 1, wherein the step difference is greater than a thickness of the first bonding layer.

4. The bonded semiconductor structure of claim 1, wherein the step difference is less than a thickness of the first bonding layer.

5. The bonded semiconductor structure of claim 1, wherein sidewalls of the first bonding layer are in direct contact with sidewalls of the second bonding pad.

6. The bonded semiconductor structure of claim 1, further comprising a gap between the sidewalls of the first bonding layer and the sidewalls of the second bonding pad.

7. The bonded semiconductor structure of claim 1, wherein an included angle between the sidewalls of the first bonding layer and a top surface of the first bonding pad is greater than 90 degrees.

8. The bonded semiconductor structure of claim 1, wherein the first bonding layer and the second bonding layer have different thicknesses.

9. The bonded semiconductor structure of claim 1, wherein a thickness of the first bonding pad is less than a thickness of the second bonding pad.

10. The bonded semiconductor structure of claim 1, wherein a portion of the second bonding pad adjacent to the dielectric bonding interface includes a step.

11. The bonded semiconductor structure of claim 1, wherein the first bonding layer and the second bonding layer comprise silicon carbon nitride (SiCN).

12. The bonded semiconductor structure of claim 1, wherein the first dielectric layer and the second dielectric layer comprise silicon oxide (SiO2).

13. The bonded semiconductor structure of claim 1, wherein the first bonding pad and the second bonding pad comprise copper.

14. A method of fabricating a bonded semiconductor structure, comprising: providing a first die and a second die, wherein the first die includes a first bonding pad exposed from a first bonding layer and the second die includes a second bonding pad exposed from a second bonding layer; removing a portion of the first bonding pad to expose sidewalls of the first bonding layer; removing a portion of the second bonding layer to expose sidewalls of the second bonding pad; and bonding the first die and the second die to obtain a dielectric bonding interface between the first bonding layer and the second bonding layer and an electrically conductive bonding interface between the first bonding pad and the second bonding pad, wherein the electrically conductive bonding interface and the dielectric bonding interface include a step difference. ​ ​ ​ ​ 15. The method of claim 14, wherein the portion of the first bonding pad is removed by a chemical mechanical polishing fabrication process.

16. The method of claim 14, wherein the portion of the second bonding layer is removed by a wet etching fabrication process.

17. The method of claim 16, wherein the second bonding layer comprises silicon carbon nitride (SiCN) and the wet etching fabrication process comprises using phosphoric acid (H3PO4).

18. The method of claim 14, wherein an included angle between the sidewall of the first bonding layer and a top surface of the first bonding pad is greater than 90 degrees.

19. The method of claim 14, wherein after bonding the first device wafer and the second device wafer, the sidewall of the first bonding layer is in direct contact with the sidewall of the second bonding pad.

20. The method of claim 14, wherein after bonding the first device wafer and the second device wafer, a gap is included between the sidewall of the first bonding layer and the sidewall of the second bonding pad.

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