A diode device for HEMT, its fabrication method, and HEMT

Abstract

This application belongs to the field of semiconductor technology and provides a diode device, fabrication method, and HEMT for use in HEMT. The diode device includes: a semiconductor substrate, a first channel layer, a first barrier layer, multiple second channel layers, multiple second barrier layers, a capping layer, an anode electrode layer, a cathode electrode layer, and an insulating dielectric layer. By alternately stacking multiple second channel layers and multiple second barrier layers on the first barrier layer to form a stepped structure on its first side, an anode electrode layer covering the stepped structure and the capping layer is provided on the first side, and a cathode electrode layer is provided on its second side. An insulating dielectric layer is provided between the anode electrode layer and the cathode electrode layer, so that the capacitance between the anode and the cathode has a higher uniform electric field. At the same time, the electric field can be improved in both the lateral and longitudinal directions to increase the breakdown voltage of the parasitic diode, thus solving the problem of instability of HEMT devices in high-inductive applications due to the lack of a body diode.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a diode device, a fabrication method, and an HEMT for use in HEMT. Background Technology

[0002] As a representative of third-generation semiconductor materials, gallium nitride (GaN) has many excellent properties, such as high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration, and good high-temperature operation capability.

[0003] However, compared to silicon-based metal-oxide-semiconductor field-effect transistors (Si-MOSFETs), gallium nitride-based high electron mobility transistors (HEMTs) do not have a body diode. In high-inductance applications, the reverse current generated can cause the gate voltage of the device to rise, leading to device damage. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a diode device, a fabrication method, and an HEMT for use in HEMTs, aiming to solve the problem in the prior art where the reverse current generated by HEMTs in high-inductance applications causes the device gate voltage to rise, leading to device damage.

[0005] The first aspect of this application provides a diode device for use in HEMT, the diode device comprising:

[0006] Semiconductor substrate;

[0007] A first channel layer is disposed on the semiconductor substrate;

[0008] The first barrier layer is disposed on the first channel layer;

[0009] Multiple second channel layers and multiple second barrier layers are alternately stacked on the first barrier layer, the bottom second channel layer is disposed on the first barrier layer, and the widths of the multiple second channel layers and multiple second barrier layers decrease sequentially to form a stepped structure on the first side of the multiple second channel layers and multiple second barrier layers.

[0010] A capping layer is disposed on top of the second barrier layer;

[0011] An anode electrode layer is disposed on the stepped structure and the capping layer;

[0012] A cathode electrode layer is disposed on the first channel layer and on the second side of a plurality of second channel layers and a plurality of second barrier layers;

[0013] An insulating dielectric layer is disposed on the top of the second barrier layer and is located between the anode electrode layer and the cathode electrode layer and between the cap layer and the cathode electrode layer; wherein the anode electrode layer and the cathode electrode layer are respectively connected to the source and drain of the HEMT.

[0014] In one embodiment, the second sides of the plurality of second channel layers and the plurality of second barrier layers are flush with the second side of the first barrier layer.

[0015] In one embodiment, the cathode electrode layer is further disposed on the second side of the first barrier layer and extends into the first channel layer.

[0016] In one embodiment, the difference between the width of the second barrier layer and the width of the second channel layer on the back side of the second barrier layer is equal to the difference between the width of the second barrier layer and the width of the second channel layer on the front side of the second barrier layer.

[0017] In one embodiment, the upper surface of the insulating dielectric layer is flush with the upper surface of the anode electrode layer.

[0018] In one embodiment, the thickness of the second channel layer is the same as the thickness of the second barrier layer.

[0019] In one embodiment, the insulating dielectric layer is a high dielectric material.

[0020] A second aspect of this application also provides a method for fabricating a diode device applied in HEMT, comprising:

[0021] A first channel layer and a first barrier layer are sequentially formed on a semiconductor substrate;

[0022] Multiple second channel layers and multiple second barrier layers are formed alternately on the first barrier layer; wherein, the bottom second channel layer is disposed on the first barrier layer, and the widths of the multiple second channel layers and multiple second barrier layers decrease sequentially, so as to form a stepped structure on the first side of the multiple second channel layers and multiple second barrier layers.

[0023] A capping layer is formed on the top second barrier layer;

[0024] An anode electrode layer is formed on the stepped structure and the cap layer;

[0025] A cathode electrode layer is formed on the first channel layer; wherein the cathode electrode layer is disposed on the second side of a plurality of second channel layers and a plurality of second barrier layers;

[0026] An insulating dielectric layer is formed on the top second barrier layer, the insulating dielectric layer being located between the anode electrode layer and the cathode electrode layer, and between the cap layer and the cathode electrode layer.

[0027] A third aspect of this application also provides a HEMT, wherein the HEMT integrates a diode device as described in any of the above embodiments; or includes a diode device fabricated by the fabrication method described above.

[0028] In one embodiment, the diode device applied to the HEMT is disposed below the gate, drain, or source of the HEMT, and the anode electrode layer is connected to the source of the HEMT, and the cathode electrode layer is connected to the drain of the HEMT.

[0029] The beneficial effects of this application embodiment compared with the prior art are as follows: by alternately stacking multiple second channel layers and multiple second barrier layers on the first barrier layer to form a stepped structure on its first side, and setting an anode electrode layer covering the stepped structure and the capping layer on the first side, and setting a cathode electrode layer on its second side, and setting an insulating dielectric layer between the anode electrode layer and the cathode electrode layer, the capacitance between the anode and the cathode has a higher uniform electric field. At the same time, the electric field can be improved in both the lateral and longitudinal directions to increase the breakdown voltage of the parasitic diode, thus solving the problem of instability of HEMT devices in high-inductive application scenarios due to the lack of a body diode. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the vertical cross-sectional structure of a gallium nitride-based diode device provided in one embodiment of this application;

[0031] Figure 2 This is a schematic flowchart of a method for fabricating a gallium nitride-based diode device according to an embodiment of this application;

[0032] Figure 3 This is a schematic diagram of a structure in which a first channel layer 210 and a first barrier layer 220 are sequentially formed on a semiconductor substrate 100, according to an embodiment of this application;

[0033] Figure 4 This is a schematic diagram of the structure for forming the second channel layer 310 according to an embodiment of this application;

[0034] Figure 5 This is a schematic diagram of the structure for forming the second mask layer 202 according to an embodiment of this application;

[0035] Figure 6 This is a schematic diagram of the structure after forming the second barrier layer 320 according to one embodiment of this application;

[0036] Figure 7This is a schematic diagram of the structure after forming a multilayer second channel layer 310 and a second barrier layer 320 according to an embodiment of this application;

[0037] Figure 8 This is a schematic diagram of the structure for forming the cap layer 600 according to an embodiment of this application;

[0038] Figure 9 This is a schematic diagram of the structure for forming the anode electrode layer 520 according to an embodiment of this application. Detailed Implementation

[0039] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0040] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0041] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.

[0043] In this specification, references to "one embodiment," "some embodiments," or simply "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," "in a particular embodiment," and "in a particular application," appearing in various parts of this specification, do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0044] As a representative of third-generation semiconductor materials, gallium nitride (GaN) possesses many excellent properties, including a high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration, and good high-temperature operating capability. Third-generation semiconductor devices based on gallium nitride, such as high electron mobility transistors (HEMTs) and heterostructure field-effect transistors (HFETs), have already been applied, showing significant advantages, especially in radio frequency and microwave applications requiring high power and high frequency.

[0045] Compared to MOSFETs, GaN HEMTs do not have a body diode. In high-inductance applications, reverse current can cause the gate voltage to rise, leading to device damage.

[0046] To address the aforementioned technical problems, this application provides a diode device for use in HEMTs. This diode device can be integrated within the HEMT, for example, within a forked HEMT device. A large amount of space is reserved below the drain, source, or gate of the device. Using the same gallium nitride process, the diode device described in this embodiment can be integrated into the space below the drain, source, or gate of the device, preventing accidental opening of the device gate under high inductance and thus preventing device damage.

[0047] In one embodiment, combined Figure 1 As shown, the diode device in this embodiment includes: a semiconductor substrate 100, a first channel layer 210, a first barrier layer 220, a plurality of second channel layers 310, a plurality of second barrier layers 320, a capping layer 600, an anode electrode layer 520, a cathode electrode layer 510, and an insulating dielectric layer 400.

[0048] In this embodiment, a first channel layer 210 is disposed on a semiconductor substrate 100, and a first barrier layer 220 is disposed on the first channel layer 220; a plurality of second channel layers 310 and a plurality of second barrier layers 320 are alternately stacked on the first barrier layer 220, with the bottom second channel layer 310 disposed on the first barrier layer 220, and the plurality of second channel layers 310 and the plurality of second barrier layers 320 decreasing in size sequentially to form a stepped structure on the first side of the plurality of second channel layers 310 and the plurality of second barrier layers 320.

[0049] A capping layer 600 is disposed on the top second barrier layer 320; an anode electrode layer 520 covers the stepped structure and the capping layer 600; a cathode electrode layer 510 is disposed on the first channel layer 210 and on the second side of the plurality of second channel layers 310 and the plurality of second barrier layers 320; an insulating dielectric layer 400 is disposed on the top second barrier layer 320 and is located between the anode electrode layer 520 and the cathode electrode layer 510 and between the capping layer 600 and the cathode electrode layer 510; wherein, the anode electrode layer 520 and the cathode electrode layer 510 are respectively connected to the source and drain of the HEMT.

[0050] In this embodiment, since the diode device has multiple channel layers and multiple barrier layers, and the channel layers and barrier layers are stacked alternately, the diode device has multiple two-dimensional electron gas channels. Under forward bias, the multiple two-dimensional electron gas channels below, which are depleted by the capping layer (the capping layer can be P-type gallium nitride), reopen, forming a multi-channel two-dimensional electron gas, reducing the on-resistance of the device. Under reverse bias, multiple field plates at the anode electrode layer form a stepped structure, which reduces the electric field peaks at the anode electrode layer below. At the same time, due to the depletion effect of the capping layer on the two-dimensional electron gas below, the surface electric field of the device is improved.

[0051] In one embodiment, the insulating dielectric layer 400 between the anode electrode layer 520 and the cathode electrode layer 510 is a high dielectric material. Since the capacitor formed between the anode electrode layer 520, the insulating dielectric layer 400, and the cathode electrode layer 510 has a higher uniform electric field, it can also adjust the electric field below the insulating dielectric layer 400, thereby improving the electric field inside the device in both the lateral and longitudinal directions, and greatly improving the withstand voltage of the device.

[0052] In one embodiment, the insulating dielectric layer 400 may be lanthanum oxide or silicon oxide.

[0053] In one embodiment, the first channel layer 210 and the second channel layer 310 can be N-type gallium nitride layers.

[0054] In one embodiment, the first barrier layer 220 and the second barrier layer 320 can be AlGaN layers.

[0055] In one embodiment, combined Figure 1 As shown, the cathode electrode layer 510 is located on the second side of the first barrier layer 220, the second channel layer 310, and the second barrier layer 320, and the first side edge of the cathode electrode layer 510 is flush with the second side edge of the first barrier layer 220, the second channel layer 310, and the second barrier layer 320. The distance between the first side edge of the first barrier layer 220, the second channel layer 310, and the second barrier layer 320 and the cathode electrode layer 510 gradually decreases.

[0056] In one embodiment, multiple second channel layers 310 and multiple second barrier layers 320 are alternately stacked, and the distance between their left edge positions and the cathode electrode layer 510 decreases layer by layer from bottom to top. At this time, the multiple second channel layers 310 and multiple second barrier layers 320 form a stepped structure. Since the anode electrode layer 510 covers the stepped structure, the anode electrode layer 510 can be composed of multiple electrode field plates. Under reverse bias, the multiple electrode field plates of the anode electrode layer 510 reduce the electric field peak at the anode below, thereby adjusting the electric field in its direction.

[0057] In one embodiment, the cathode electrode layer 510 has a rectangular structure.

[0058] In one embodiment, the first side edge of the first channel layer 210 is flush with the first side edge of the first barrier layer 220, and the second side edge of the first barrier layer 220 is flush with the second side edge of the first channel layer 210.

[0059] In one embodiment, the second sides of the plurality of second channel layers 310 and the plurality of second barrier layers 320 are flush with the second side of the first barrier layer 220.

[0060] In one embodiment, the cathode electrode layer 510 is also disposed on the second side of the first barrier layer 220 and extends into the first channel layer 210.

[0061] In this embodiment, the depth to which the cathode electrode layer 510 extends into the first channel layer 210 is less than the thickness of the first barrier layer 220.

[0062] In one embodiment, the distances between the first barrier layer 220, the second channel layer 310, the first side edge of the second barrier layer 320 and the cathode electrode layer 510 are arranged in an arithmetic sequence.

[0063] In one embodiment, the difference between the width of the second barrier layer 320 and the width of the second channel layer 310 on the back side of the second barrier layer 320 is equal to the difference between the width of the second barrier layer 320 and the width of the second channel layer 310 on the front side of the second barrier layer 320.

[0064] In one embodiment, the upper surface of the insulating dielectric layer 400 is flush with the upper surface of the anode electrode layer 520.

[0065] In one embodiment, the thickness of the second channel layer 310 is the same as the thickness of the second barrier layer 320.

[0066] In one embodiment, there can be two second channel layers 310 and two second barrier layers 320. The first barrier layer 220, first channel layer 310, second barrier layer 320, and second barrier layer 320 are sequentially stacked on the first channel layer 210, and the widths of the first barrier layer 220, first channel layer 310, second barrier layer 320, and second barrier layer 320 decrease progressively. Figure 1 As shown.

[0067] This application also provides a method for fabricating a diode device applied to HEMT, see [link to relevant documentation]. Figure 2 As shown, the preparation method in this embodiment includes steps S10 to S60.

[0068] In step S10, combined Figure 3 As shown, a first channel layer 210 and a first barrier layer 220 are sequentially formed on a semiconductor substrate 100.

[0069] In this embodiment, the first channel layer 210 and the first barrier layer 220 have the same width. The first channel layer 210 can be formed on the surface of the semiconductor substrate 100 by depositing channel material on the substrate and then depositing barrier material on the surface of the first channel layer 210.

[0070] In one embodiment, the thickness of the first channel layer 210 is greater than the thickness of the first barrier layer 220.

[0071] In one embodiment, the thickness of the first channel layer 210 is three times the thickness of the first barrier layer 220.

[0072] In one embodiment, the first channel layer 210 may be an N-type gallium nitride layer.

[0073] In one embodiment, the first barrier layer 220 can be an AlGaN layer.

[0074] In step S20, combined Figures 3 to 7 As shown, a plurality of second channel layers 310 and a plurality of second barrier layers 320 are formed alternately on the first barrier layer 220.

[0075] In this embodiment, the bottom second channel layer 310 is disposed on the first barrier layer 220, and the widths of the plurality of second channel layers 310 and the plurality of second barrier layers 320 decrease sequentially to form a stepped structure on the first side of the plurality of second channel layers 310 and the plurality of second barrier layers 320.

[0076] In one embodiment, step S20, forming a plurality of alternately stacked second channel layers 310 and a plurality of second barrier layers 320 on the first barrier layer 220, may specifically include steps S21 to S24.

[0077] In step S21, combined Figure 3 As shown, a first mask layer 201 is formed on the first barrier layer 220. The first mask layer 201 is located in the central region of the surface of the first barrier layer 220. The distance between the left edge of the first mask layer 201 and the left edge of the first barrier layer 220 is equal to the distance between the right edge of the first mask layer 201 and the right edge of the first barrier layer 220.

[0078] In one embodiment, a first mask layer 201 can be formed on the surface of the first barrier layer 220 by depositing silicon nitride material, and the silicon nitride material can be etched using a photomask or photoresist so that the first mask layer 201 is located in the central region of the surface of the first barrier layer 220.

[0079] In step S22, combined Figure 4 As shown, a second channel layer 310 is formed on the surface of the first barrier layer 220 by depositing channel layer material, and the second channel layer 310 is treated by chemical mechanical polishing so that the thickness of the second channel layer 310 is equal to the thickness of the first mask layer 201.

[0080] Since the first mask layer 201 is located in the central region of the surface of the first barrier layer 220, a second channel layer 310 is provided on both sides of the first mask layer 201, and the widths of the second channel layers 310 on both sides of the first mask layer 201 are equal.

[0081] In one embodiment, a gallium nitride layer can be formed on the surface of the first barrier layer 220 as a second channel layer 310 by depositing gallium nitride material.

[0082] In step S23, combined Figure 5 As shown, a second mask layer 202 is formed on the surface of the first mask layer 201 and the second channel layer 310. The second mask layer 202 is located on the first mask layer 201, and the width of the second mask layer 202 is greater than the width of the first mask layer 201. The distance between the left edge of the second mask layer 202 and the left edge of the first mask layer 201 is equal to the distance between the right edge of the second mask layer 202 and the right edge of the first mask layer 201.

[0083] The distance between the left edge of the second mask layer 202 and the left edge of the first barrier layer 220 is equal to the distance between the right edge of the second mask layer 202 and the right edge of the first barrier layer 220.

[0084] In one embodiment, a second mask layer 202 can be formed on the surface of a first mask layer 201 by depositing silicon nitride material, and the silicon nitride material can be etched using a photomask or photoresist so that the width of the second mask layer 202 is greater than the width of the first mask layer 201, and the distance between the left edge of the second mask layer 202 and the left edge of the first mask layer 201 is equal to the distance between the right edge of the second mask layer 202 and the right edge of the first mask layer 201.

[0085] In step S24, combined Figure 6 As shown, the deposited channel layer material forms a second barrier layer 320 on the surface of the second channel layer 310, and the second barrier layer 320 is treated by chemical mechanical polishing so that the thickness of the second barrier layer 320 is equal to the thickness of the second mask layer 202.

[0086] The second mask layer 202 is located on the first mask layer 201. The second mask layer 202 has a second barrier layer 320 on both sides, and the widths of the second barrier layers 320 on both sides of the second mask layer 202 are equal.

[0087] In one embodiment, a gallium nitride (GaN) aluminum layer can be formed on the surface of the second channel layer 310 as a second barrier layer 320 by depositing gallium nitride aluminum material.

[0088] Combination Figure 7 As shown, repeat steps S21 to S24 above to form a third mask layer 203 on the second mask layer 202, then form a top second channel layer 310, then form a fourth mask layer 205 on the third mask layer 204, and form a top second barrier layer 320.

[0089] In specific applications, the number of layers of the second channel layer 310 and the second barrier layer 320 is determined by the number of repetitions of steps S21 to S24, and the width of each subsequent mask layer is greater than the width of the previous mask layer, so that the stacked and alternately arranged second channel layer 310 and second barrier layer 320 have a stepped structure.

[0090] In one embodiment, there can be two second channel layers 310 and two second barrier layers 320. The first barrier layer 220, first channel layer 310, second barrier layer 320, and second barrier layer 320 are sequentially stacked on the first channel layer 210, and the widths of the first barrier layer 220, first channel layer 310, second barrier layer 320, and second barrier layer 320 decrease progressively. Figure 1 As shown.

[0091] In one embodiment, the second channel layer 310 may be an N-type gallium nitride layer.

[0092] In one embodiment, the second barrier layer 320 can be an AlGaN layer.

[0093] In step S30, combined Figure 8 As shown, a capping layer 600 is formed on the top second barrier layer 320.

[0094] In this embodiment, the multiple mask layers in step S20 are removed, and then the barrier layer and channel layer formed in step S20 are cut along the central region of the first mask layer 201 to form the following structure: Figure 8 The stepped structure includes a barrier layer and a channel layer.

[0095] A P-type gallium nitride layer is formed by depositing P-type gallium nitride material on the top second barrier layer 320, and the P-type gallium nitride layer is etched to remove the P-type gallium nitride material in a portion of the second side of the P-type gallium nitride layer to form a capping layer 600. The edge of the first side of the capping layer 600 is aligned with the edge of the first side of the top second barrier layer 320.

[0096] In step S40, as Figure 9 As shown, an anode electrode layer 520 is formed on the stepped structure and the cap layer 600.

[0097] In this embodiment, the anode electrode layer 520 covers the stepped structure and the capping layer 600. Since the back side of the anode electrode layer 520 matches the stepped structure, the back side of the anode electrode layer 520 also has a stepped structure. The anode electrode layer 520 can be equivalent to a multilayer electrode field plate, and each electrode field plate corresponds to the second channel layer 310 or the second barrier layer 320.

[0098] In one embodiment, the first side edge of the anode electrode layer 520 is flush with the first side edge of the first barrier layer 220, and the second side edge of the anode electrode layer 520 is flush with the second side edge of the cap layer 600, with the first and second sides opposite to each other.

[0099] In step S50, a cathode electrode layer 510 is formed on the first channel layer 210.

[0100] In this embodiment, the cathode electrode layer 510 is disposed on the second side of the plurality of second channel layers 310 and the plurality of second barrier layers 320, and the distance between the first edge of the cathode electrode layer 510 and the anode electrode layer 520 is greater than the width of the cathode electrode layer 510.

[0101] In one embodiment, the cathode electrode layer 510 is also disposed on the second side of the first barrier layer 220 and extends into the first channel layer 210.

[0102] In this embodiment, the depth to which the cathode electrode layer 510 extends into the first channel layer 210 is less than the thickness of the first barrier layer 220.

[0103] In one embodiment, the distances between the first barrier layer 220, the second channel layer 310, the first side edge of the second barrier layer 320 and the cathode electrode layer 510 are arranged in an arithmetic sequence.

[0104] In one embodiment, the difference between the width of the second barrier layer 320 and the width of the second channel layer 310 on the back side of the second barrier layer 320 is equal to the difference between the width of the second barrier layer 320 and the width of the second channel layer 310 on the front side of the second barrier layer 320.

[0105] In step S60, combined Figure 1 As shown, an insulating dielectric layer 400 is formed on the top second barrier layer 320, and the insulating dielectric layer 400 is located between the anode electrode layer 520 and the cathode electrode layer 510 and between the cap layer 600 and the cathode electrode layer 510.

[0106] In one embodiment, the upper surface of the insulating dielectric layer 400 is flush with the upper surface of the anode electrode layer 520.

[0107] In one embodiment, multiple second channel layers 310 and multiple second barrier layers 320 are alternately stacked, and the distance between their left edge positions and the cathode electrode layer 510 decreases layer by layer from bottom to top. At this time, the multiple second channel layers 310 and multiple second barrier layers 320 form a stepped structure. Since the anode electrode layer 510 covers the stepped structure, the anode electrode layer 510 can be composed of multiple electrode field plates. Under reverse bias, the multiple electrode field plates of the anode electrode layer 510 reduce the electric field peak at the anode below, thereby adjusting the electric field in its direction.

[0108] In this embodiment, since the diode device has multiple channel layers and multiple barrier layers, and the channel layers and barrier layers are stacked alternately, the diode device has multiple two-dimensional electron gas channels. Under forward bias, the multiple two-dimensional electron gas channels below, which are depleted by the capping layer (the capping layer can be P-type gallium nitride), reopen, forming a multi-channel two-dimensional electron gas, reducing the on-resistance of the device. Under reverse bias, multiple field plates at the anode electrode layer form a stepped structure, which reduces the electric field peaks at the anode electrode layer below. At the same time, due to the depletion effect of the capping layer on the two-dimensional electron gas below, the surface electric field of the device is improved.

[0109] In one embodiment, the insulating dielectric layer 400 between the anode electrode layer 520 and the cathode electrode layer 510 is a high dielectric material. Since the capacitor formed between the anode electrode layer 520, the insulating dielectric layer 400, and the cathode electrode layer 510 has a higher uniform electric field, it can also adjust the electric field below the insulating dielectric layer 400, thereby improving the electric field inside the device in both the lateral and longitudinal directions, and greatly improving the withstand voltage of the device.

[0110] In one embodiment, the insulating dielectric layer 400 may be lanthanum oxide or silicon oxide.

[0111] This application also provides a gallium nitride HEMT, which integrates a gallium nitride-based diode device as described in any of the above embodiments.

[0112] This application also provides a gallium nitride HEMT, which integrates a gallium nitride-based diode device fabricated by the fabrication method described in the above embodiments.

[0113] In specific applications, the gallium nitride-based diode device in the above embodiments shares the channel layer, barrier layer, and semiconductor substrate with the gallium nitride HEMT.

[0114] In one embodiment, a gallium nitride-based diode device is disposed below the gate, drain, or source of a gallium nitride HEMT, and the anode electrode layer is connected to the source of the gallium nitride HEMT, and the cathode electrode layer is connected to the drain of the gallium nitride HEMT.

[0115] The beneficial effects of this application embodiment compared with the prior art are as follows: by alternately stacking multiple second channel layers and multiple second barrier layers on the first barrier layer to form a stepped structure on its first side, and setting an anode electrode layer covering the stepped structure and the capping layer on the first side, and setting a cathode electrode layer on its second side, and setting an insulating dielectric layer between the anode electrode layer and the cathode electrode layer, the capacitance between the anode and the cathode has a higher uniform electric field. At the same time, the electric field can be improved in both the lateral and longitudinal directions to increase the breakdown voltage of the parasitic diode, thus solving the problem of instability of HEMT devices in high-inductive application scenarios due to the lack of a body diode.

[0116] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions is used as an example. In practical applications, the above-described functional areas can be assigned to different doped regions as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above.

[0117] In the embodiments, the doped regions can be integrated into one functional region, or each doped region can exist independently, or two or more doped regions can be integrated into one functional region. The integrated functional region can be implemented using the same type of dopant ion or multiple types of dopant ions. Furthermore, the specific names of each doped region are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the doped region in the fabrication method of the above device can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0118] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A diode device for use in HEMT, characterized in that, The diode device includes: Semiconductor substrate; A first channel layer is disposed on the semiconductor substrate; The first barrier layer is disposed on the first channel layer; Multiple second channel layers and multiple second barrier layers are alternately stacked on the first barrier layer, the bottom second channel layer is disposed on the first barrier layer, and the widths of the multiple second channel layers and multiple second barrier layers decrease sequentially to form a stepped structure on the first side of the multiple second channel layers and multiple second barrier layers. A capping layer is disposed on top of the second barrier layer; An anode electrode layer is disposed on the stepped structure and the capping layer; A cathode electrode layer is disposed on the first channel layer and on the second side of a plurality of second channel layers and a plurality of second barrier layers; An insulating dielectric layer is disposed on the top of the second barrier layer and is located between the anode electrode layer and the cathode electrode layer and between the cap layer and the cathode electrode layer; wherein the anode electrode layer and the cathode electrode layer are respectively connected to the source and drain of the HEMT.

2. The diode device as described in claim 1, characterized in that, The second sides of the plurality of second channel layers and the plurality of second barrier layers are flush with the second side of the first barrier layer.

3. The diode device as described in claim 2, characterized in that, The cathode electrode layer is also disposed on the second side of the first barrier layer and extends into the first channel layer.

4. The diode device as described in claim 2, characterized in that, The difference between the width of the second barrier layer and the width of the second channel layer on the back side of the second barrier layer is equal to the difference between the width of the second barrier layer and the width of the second channel layer on the front side of the second barrier layer.

5. The diode device according to any one of claims 1-4, characterized in that, The upper surface of the insulating dielectric layer is flush with the upper surface of the anode electrode layer.

6. The diode device according to any one of claims 1-4, characterized in that, The thickness of the second channel layer is the same as the thickness of the second barrier layer.

7. The diode device according to any one of claims 1-4, characterized in that, The insulating dielectric layer is a high dielectric material.

8. A method for fabricating a diode device for HEMT, characterized in that, include: A first channel layer and a first barrier layer are sequentially formed on a semiconductor substrate; Multiple second channel layers and multiple second barrier layers are formed alternately on the first barrier layer; wherein, the bottom second channel layer is disposed on the first barrier layer, and the widths of the multiple second channel layers and multiple second barrier layers decrease sequentially, so as to form a stepped structure on the first side of the multiple second channel layers and multiple second barrier layers. A capping layer is formed on the top second barrier layer; An anode electrode layer is formed on the stepped structure and the cap layer; A cathode electrode layer is formed on the first channel layer; wherein the cathode electrode layer is disposed on the second side of a plurality of second channel layers and a plurality of second barrier layers; An insulating dielectric layer is formed on the top second barrier layer, the insulating dielectric layer being located between the anode electrode layer and the cathode electrode layer, and between the cap layer and the cathode electrode layer.

9. A HEMT, characterized in that, The HEMT integrates a diode device as described in any one of claims 1-7; or includes a diode device prepared by the preparation method described in claim 8.

10. The HEMT as described in claim 9, characterized in that, The diode device applied to the HEMT is disposed below the gate, drain, or source of the HEMT, and the anode electrode layer is connected to the source of the HEMT, and the cathode electrode layer is connected to the drain of the HEMT.

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