High-voltage enhancement-mode HEMT devices that suppress current collapse
By introducing a P-GaN hole injection structure and a high-resistivity capping layer into GaN-based HEMT devices, the problem of current collapse effect is solved, and the high voltage withstand and high frequency performance are improved, making them suitable for high-frequency and high-power applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2022-11-30
- Publication Date
- 2026-05-26
Smart Images
Figure CN115842041B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology and relates to a high electron mobility transistor (HEMT), specifically a high voltage-enhanced HEMT device that suppresses current collapse. Background Technology
[0002] In wide-bandgap compound semiconductor electronic devices, GaN materials possess advantages such as wide bandgap, high critical breakdown electric field, high electron saturation velocity, high thermal conductivity, and strong radiation resistance. Therefore, GaN-based HEMTs exhibit strong high-frequency, high-voltage, high-temperature, and harsh-environment resistance capabilities. GaN-based HEMTs are among the main devices used in high-frequency, high-power applications and are currently a research hotspot, with significant progress made in related development in recent years. However, the stability and reliability of GaN-based HEMT devices still need to be addressed. Among these, the current collapse effect is a major obstacle hindering their practical application—when the device operates under high-frequency, high-signal conditions, the output current decreases significantly, leading to a reduction in output power. The existence of the current collapse effect has severely hampered the high-frequency, high-power applications of GaN-based HEMTs.
[0003] The main cause of the current collapse effect is the "virtual gate" effect caused by surface traps. Using a P-GaN gate can increase the potential at the heterojunction, thereby achieving the device's normal off state. However, hole injection from the gate will generate a large number of electrons. Electrons from the gate electrode will drift along the surface of the barrier layer to the drain under the action of the electric field. When they flow through the surface states, they are captured, resulting in a depletion region on the surface of the barrier layer, which is similar to adding an "virtual gate". This reduces the channel electron concentration, reduces the device's output current, and causes current collapse. In 2016, Panasonic of Japan proposed a hybrid drain-gate injected GaN transistor (GMT) with a P-GaN region introduced on the surface of the device barrier layer and on the drain side near the gate. The P-GaN region is electrically connected to the drain. In the off-state, this structure can inject holes into the barrier layer, which recombine with electrons trapped by traps on the barrier layer surface to suppress the "virtual gate" effect, effectively suppressing current collapse (Current-collapse-free operations up to 850V by GaN-GIT utilizing hole injection from drain[C] / / IEEE International Symposium on Power Semiconductor Devices & Ics.IEEE, 2015.). Research on this structure has been deepening in recent years. Since the "virtual gate" effect mainly occurs near the gate, achieving optimal hole injection requires placing the structure as close to the gate as possible. However, the P-GaN structure in this study needs to be short-circuited with the drain, which presents a challenge to improving device performance: shortening the distance between the structure and the gate results in a substantial shortening of the drift region, leading to a decrease in the device's breakdown voltage; conversely, extending the distance to the gate to obtain a longer drift region for improved breakdown voltage results in longer surface charge transport, reducing surface trap recombination efficiency and decreasing the suppression effect on current collapse. Therefore, to address these technical problems, it is essential to design a novel GaN-based HEMT device structure that can introduce a hole injection structure without shortening the device's drift region. Summary of the Invention
[0004] To address the problems of shortened drift region and difficulty in simultaneously suppressing current collapse and device breakdown voltage caused by existing hybrid drain-gate injection transistor device structures, this invention proposes a novel high-breakdown-voltage enhancement-mode HEMT device structure that suppresses current collapse.
[0005] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:
[0006] A high-voltage enhancement-mode HEMT device that suppresses current collapse includes a substrate 1, an unintentionally doped GaN layer 2 disposed on the substrate 1, and an unintentionally doped Al layer disposed on the GaN layer 2. x Ga 1-x N layers 3, 0 < x < 1, where GaN layer 2 and Al x Ga 1-x A two-dimensional electron gas conductive channel is formed at the N-layer 3 contact interface; Al x Ga 1-x From left to right, layer N3 consists of a source 4, a P-GaN gate 5, a P-GaN hole injection structure 7, and a drain 8. The P-GaN hole injection structure 7 is located between the P-GaN gate 5 and the drain 8, and has no direct contact with either the P-GaN gate 5 or the drain 8. The source 4 and the drain 8 form ohmic contacts with the two-dimensional electron gas conductive channel. A gate metal 6 is deposited on the top of the P-GaN gate 5 to form a Schottky contact. The barrier layer below the P-GaN gate 5 has grooves so that the two-dimensional electron gas conductive channel is in a fully depleted or partially depleted state when no voltage is applied. The barrier layer below the P-GaN hole injection structure 7 has a certain thickness so that the two-dimensional electron gas conductive channel cannot be completely depleted.
[0007] High-resistivity capping layer 9 covers the P-GaN gate 5, gate metal 6, P-GaN hole injection structure 7, upper surface of drain 8, and Al between the source side of P-GaN gate 5 and drain 8. x Ga 1-x On the upper surface of layer N3, the high-resistivity capping layer 9 is made of a high-resistivity material with a sheet resistance of 10 ohms. 9 -10 11 The material is on the order of Ω / ; the P-GaN hole injection structure 7 runs through the entire drift region, and the high-resistivity capping layer 9 forms an electrical connection with the gate metal 6, the P-GaN hole injection structure 7 and the drain 8 that can conduct current.
[0008] As a preferred embodiment, the cross-sectional shape of the high-resistivity capping layer 9 along the direction from the source side of the P-GaN gate 5 to the drain 8 is stepped.
[0009] As a preferred embodiment, the high-resistivity capping layer 9 extends towards the source side, covering the upper surface of the source 4 and the Al between the source 4 and the P-GaN gate 5. x Ga 1-x On the upper surface of layer N3, the high-resistivity capping layer 9 forms an electrical connection with the source 4 that enables current to be conducted.
[0010] The working principle of the device provided by this invention is as follows:
[0011] A P-GaN hole injection structure 7 is additionally introduced next to the P-GaN gate 5 of the GaN-based HEMT. Due to the presence of the high-resistivity capping layer, after applying a high drain voltage, the P-GaN hole injection structure 7 receives an appropriate positive voltage and injects holes into the barrier layer. This injection current is introduced from the drain 8 by the high-resistivity capping layer, which has the advantage of not having to cross the entire drift region and not needing to shrink the drift region. The injected holes recombine with electrons trapped by the surface traps of the barrier layer to suppress the "virtual gate" effect, effectively suppressing the current collapse of the transistor under high drain voltage.
[0012] The beneficial effects of this invention are as follows: Since the "virtual gate" effect mainly occurs near the gate, compared with hybrid drain-gate injection transistor devices, the P-GaN hole injection structure 7 in this invention can be close enough to the gate, allowing for more complete surface trap recombination; at the same time, it avoids long-distance surface charge transport, resulting in faster surface charge transfer and improving surface trap recombination efficiency to achieve the best hole injection effect. This invention effectively suppresses current collapse without shortening the drift region, avoiding premature device breakdown caused by a short drift region. Simultaneously, the P-GaN hole injection structure 7 can serve as a breakdown voltage region to increase the device's breakdown voltage. Furthermore, the introduction of a high-resistivity capping layer can act as a high-resistivity field plate to discharge electrons from the barrier layer surface to the gate. The high-resistivity capping layer weakens the electric field at the gate edge, reducing the electron injection efficiency to the surface and further suppressing current collapse. The HEMT device proposed in this invention effectively suppresses current collapse of the transistor under high drain voltage while ensuring high breakdown voltage, making it suitable for applications with high requirements for output power and operating frequency. Attached Figure Description
[0013] Figure 1 This is a schematic diagram of a high-voltage enhancement-mode HEMT device structure that suppresses current collapse, as provided in Embodiment 1 of the present invention.
[0014] Figure 2 This is a schematic diagram of a high-voltage enhancement-mode HEMT device structure that suppresses current collapse, as provided in Embodiment 2 of the present invention.
[0015] Figure 3 This is a schematic diagram of a high-voltage enhancement-mode HEMT device structure that suppresses current collapse, as provided in Embodiment 3 of the present invention.
[0016] Figure 4 This is a schematic diagram of the structure of growing a GaN layer on the upper surface of a substrate provided by the present invention.
[0017] Figure 5 The present invention provides a method for growing Al on the surface of a GaN layer. x Ga 1-x A schematic diagram of the N-layer structure.
[0018] Figure 6 The present invention provides in Al x Ga 1-x A schematic diagram of a structure in which N layers are partially thinned.
[0019] Figure 7 The present invention provides in Al x Ga 1-x Schematic diagram of a structure in which a P-GaN layer is grown on the upper surface of an N-layer.
[0020] Figure 8 The present invention provides in Al x Ga 1-x A schematic diagram of the structure formed by etching P-GaN gate and P-GaN hole injection structure on the surface of N layer.
[0021] Figure 9 This invention provides a structural diagram of a source and drain electrode formed in ohmic contact with a two-dimensional conductive channel on the upper surface of a GaN layer.
[0022] Figure 10 This is a schematic diagram of the structure of the gate metal formed on the upper surface of the P-GaN gate to form a Schottky contact with the P-GaN gate, as provided by the present invention.
[0023] Figure 11 The present invention provides in Al x Ga 1-x A schematic diagram of a structure in which a high-resistivity material is covered in the P-GaN gate-to-drain region on the surface of the N-layer.
[0024] Figure 12 This is a schematic diagram of the structure provided by the present invention, in which a high-resistivity capping layer is etched into a stepped shape.
[0025] Figure 13 To provide the present invention in Al x Ga 1-x A schematic diagram of a structure in which a high-resistivity material is covered in the source-to-drain region on the N-layer surface.
[0026] In the diagram: 1 is the substrate, 2 is the GaN layer, and 3 is the Al layer. x Ga 1-x N-layer, 4 is the source, 5 is the P-GaN gate, 6 is the gate metal, 7 is the P-GaN hole injection structure, 8 is the drain, 9 is the high-resistivity capping layer, and 10 is the P-GaN layer. Detailed Implementation
[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0028] Example 1
[0029] like Figure 1 As shown, a high-voltage enhancement-mode HEMT device that suppresses current collapse includes a substrate 1, an unintentionally doped GaN layer 2 disposed on the substrate 1, and an unintentionally doped Al layer disposed on the GaN layer 2. x Ga 1-x N layers 3, 0 < x < 1, where GaN layer 2 and Al x Ga 1-x A two-dimensional electron gas conductive channel is formed at the N-layer 3 contact interface; Al x Ga 1-x From left to right, layer N3 consists of a source 4, a P-GaN gate 5, a P-GaN hole injection structure 7, and a drain 8. The P-GaN hole injection structure 7 is located between the P-GaN gate 5 and the drain 8, and has no direct contact with either the P-GaN gate 5 or the drain 8. The source 4 and the drain 8 form ohmic contacts with the two-dimensional electron gas conductive channel. A gate metal 6 is deposited on the top of the P-GaN gate 5 to form a Schottky contact. The barrier layer below the P-GaN gate 5 has grooves so that the two-dimensional electron gas conductive channel is in a fully depleted or partially depleted state when no voltage is applied. The barrier layer below the P-GaN hole injection structure 7 has a certain thickness so that the two-dimensional electron gas conductive channel cannot be completely depleted.
[0030] High-resistivity capping layer 9 covers the P-GaN gate 5, gate metal 6, P-GaN hole injection structure 7, upper surface of drain 8, and Al between the source side of P-GaN gate 5 and drain 8. x Ga 1-x On the upper surface of layer N3, the high-resistivity capping layer 9 is made of a high-resistivity material with a sheet resistance of 10 ohms. 9 -10 11 The material is on the order of Ω / ; the P-GaN hole injection structure 7 runs through the entire drift region, and the high-resistivity capping layer 9 forms an electrical connection with the gate metal 6, the P-GaN hole injection structure 7 and the drain 8 that can conduct current.
[0031] The working process of this invention is described in detail below.
[0032] For traditional GaN-based HEMT devices, the current collapse effect severely hinders their high-frequency, high-power applications. When the device operates under high-frequency, large-signal conditions, the output current decreases significantly, resulting in a reduction in output power.
[0033] A P-GaN hole injection structure 7 is additionally introduced next to the gate 5 of the GaN-based HEMT. Due to the presence of the high-resistivity capping layer 9, after applying a high drain voltage, the P-GaN hole injection structure 7 receives an appropriate positive voltage and injects holes into the barrier layer. This injection current is introduced from the drain 8 by the high-resistivity capping layer 9, which has the advantage of not having to cross the entire drift region and not needing to shorten the drift region. The injected holes recombine with electrons trapped by the surface traps of the barrier layer to suppress the "virtual gate" effect, effectively suppressing the current collapse of the transistor under high drain voltage. While effectively suppressing the current collapse effect, it does not cause the shortening of the drift region, avoiding premature device breakdown caused by a short drift region. At the same time, the P-GaN hole injection structure 7 can also serve as a breakdown voltage region to improve the breakdown voltage of the device. In addition, the introduction of the high-resistivity capping layer 9 can also act as a high-resistivity field plate to discharge electrons from the surface of the barrier layer to the gate. The high-resistivity capping layer 9 weakens the electric field at the gate edge, reducing the electron injection efficiency to the surface and further suppressing current collapse.
[0034] Figures 4 to 11 The invention illustrates a method for fabricating a high-voltage enhancement-mode HEMT device with current-damping suppression according to the present invention. This example, in conjunction with the accompanying drawings, details the fabrication process of the high-voltage enhancement-mode HEMT device with current-damping suppression, wherein GaN layer 2 and Al... x Ga 1-x All N layers 3 are unintentionally doped.
[0035] A method for fabricating a high-voltage enhancement-mode HEMT device that suppresses current collapse includes the following steps:
[0036] Step 1: Grow a GaN layer 2 with a thickness of 2 μm on the upper surface of substrate 1, such as... Figure 4 As shown.
[0037] Step 2: Grow an Al layer with a thickness of 50 nm on the GaN layer 2. x Ga 1-x N layers 3, such as Figure 5 As shown.
[0038] Step 3, in Al x Ga 1-x The gate site on layer N3 is thinned by 33nm, such as... Figure 6 As shown.
[0039] Step 4, in Al x Ga 1-xA 100 nm thick P-GaN layer 10 is grown on top of N layer 3, such as Figure 7 As shown.
[0040] Step 5: On the surface of the P-GaN layer 10, patterned etching is performed to form the P-GaN gate 5 and the P-GaN hole injection structure 7, as shown below. Figure 8 As shown.
[0041] Step 6: Perform implantation isolation to create the active region, then fabricate source electrode 4 and drain electrode 8 on the surface of the active region, and ensure that source electrode 4 and drain electrode 8 are connected to GaN layer 2 and Al. x Ga 1-x The two-dimensional conductive channel at the N-layer 3 interface forms an ohmic contact, such as Figure 9 As shown.
[0042] Step 7: Fabricate gate metal 6 above the P-GaN gate 5 to form a Schottky contact with the P-GaN gate 5, such as... Figure 10 As shown.
[0043] Step 8, in Al x Ga 1-x A high-resistivity capping layer 9 with a thickness of 300 nm is grown in the region from the P-GaN gate 5, gate metal 6, P-GaN hole injection structure 7 to the drain 8 on layer N3. Figure 11 As shown.
[0044] Example 2
[0045] like Figure 2 As shown, the difference between this embodiment and Embodiment 1 is that the cross-sectional shape of the high-resistivity capping layer 9 along the direction from the source side of the P-GaN gate 5 to the drain 8 is stepped.
[0046] This embodiment also provides a fabrication method: a method for fabricating a high-voltage enhancement-mode HEMT device that suppresses current collapse, comprising the following steps:
[0047] Step 1: Grow a GaN layer 2 with a thickness of 2 μm on the upper surface of substrate 1, such as... Figure 4 As shown.
[0048] Step 2: Grow an Al layer with a thickness of 50 nm on the GaN layer 2. x Ga 1-x N layers 3, such as Figure 5 As shown.
[0049] Step 3, in Al x Ga 1-x The gate site on layer N3 is thinned by 33nm, such as... Figure 6 As shown.
[0050] Step 4, in Al x Ga1-x A 100 nm thick P-GaN layer 10 is grown on top of N layer 3, such as Figure 7 As shown.
[0051] Step 5: On the surface of the P-GaN layer 10, patterned etching is performed to form the P-GaN gate 5 and the P-GaN hole injection structure 7, as shown below. Figure 8 As shown.
[0052] Step 6: Perform implantation isolation to create the active region, then fabricate source electrode 4 and drain electrode 8 on the surface of the active region, and ensure that source electrode 4 and drain electrode 8 are connected to GaN layer 2 and Al. x Ga 1-x The two-dimensional conductive channel at the N-layer 3 interface forms an ohmic contact, such as Figure 9 As shown.
[0053] Step 7: Fabricate gate metal 6 above the P-GaN gate 5 to form a Schottky contact with the P-GaN gate 5, such as... Figure 10 As shown.
[0054] Step 8, in Al x Ga 1-x A high-resistivity capping layer 9 with a thickness of 400 nm is grown in the region from the P-GaN gate 5, gate metal 6, P-GaN hole injection structure 7 to the drain 8 on layer N3. Figure 11 As shown.
[0055] Step 9: Etch the high-resistivity capping layer 9 into a stepped shape, such as... Figure 12 As shown.
[0056] Example 3
[0057] like Figure 3 As shown, the difference between this embodiment and Embodiment 1 is that the high-resistivity capping layer 9 extends towards the source side, covering the upper surface of the source 4 and the Al between the source 4 and the P-GaN gate 5. x Ga 1-x On the upper surface of layer N3, the high-resistivity capping layer 9 forms an electrical connection with the source 4 that enables current to be conducted.
[0058] This embodiment also provides a fabrication method: a method for fabricating a high-voltage enhancement-mode HEMT device that suppresses current collapse, comprising the following steps:
[0059] Step 1: Grow a GaN layer 2 with a thickness of 2 μm on the upper surface of substrate 1, such as... Figure 4 As shown.
[0060] Step 2: Grow an Al layer with a thickness of 50 nm on the GaN layer 2. x Ga 1-x N layers 3, such as Figure 5 As shown.
[0061] Step 3, in Al x Ga 1-x The gate site on layer N3 is thinned by 33nm, such as... Figure 6 As shown.
[0062] Step 4, in Al x Ga 1-x A 100 nm thick P-GaN layer 10 is grown on top of N layer 3, such as Figure 7 As shown.
[0063] Step 5: On the surface of the P-GaN layer 10, patterned etching is performed to form the P-GaN gate 5 and the P-GaN hole injection structure 7, as shown below. Figure 8 As shown.
[0064] Step 6: Perform implantation isolation to create the active region, then fabricate source electrode 4 and drain electrode 8 on the surface of the active region, and ensure that source electrode 4 and drain electrode 8 are connected to GaN layer 2 and Al. x Ga 1-x The two-dimensional conductive channel at the N-layer 3 interface forms an ohmic contact, such as Figure 9 As shown.
[0065] Step 7: Fabricate gate metal 6 above the P-GaN gate 5 to form a Schottky contact with the P-GaN gate 5, such as... Figure 10 As shown.
[0066] Step 8, in Al x Ga 1-x N-layer 3 source electrode 4, P-GaN gate 5, gate metal 6, P-GaN hole injection structure 7 to drain electrode 8, a high-resistivity capping layer with a thickness of 300nm is grown 9, such as Figure 13 As shown.
[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A high-voltage enhancement-mode HEMT device that suppresses current collapse, characterized in that: Includes a substrate (1), an unintentionally doped GaN layer (2) disposed on the substrate (1), and an unintentionally doped Al layer disposed on the GaN layer (2). x Ga 1-x N layers (3), 0 < x < 1, where GaN layer (2) and Al x Ga 1-x A two-dimensional electron gas conductive channel is formed at the contact interface of the N-layer (3); Al x Ga 1-x The N-layer (3) is provided with a source (4), a P-GaN gate (5), a P-GaN hole injection structure (7), and a drain (8) from left to right. The P-GaN hole injection structure (7) is located between the P-GaN gate (5) and the drain (8) and has no direct contact with either the P-GaN gate (5) or the drain (8). The source (4) and the drain (8) form ohmic contacts with the two-dimensional electron gas conductive channel. A gate metal (6) is deposited on the upper part of the P-GaN gate (5) and forms a Schottky contact. The barrier layer below the P-GaN gate (5) has a groove so that the two-dimensional electron gas conductive channel is in a fully depleted or partially depleted state when no voltage is applied. The barrier layer below the P-GaN hole injection structure (7) has a certain thickness so that the two-dimensional electron gas conductive channel cannot be completely depleted. A high-resistivity capping layer (9) covers the P-GaN gate (5), gate metal (6), P-GaN hole injection structure (7), upper surface of drain (8), and Al between the source side of P-GaN gate (5) and drain (8). x Ga 1-x The upper surface region of layer N (3) has a high-resistivity capping layer (9) made of high-resistivity material with a sheet resistance of 10. 9 -10 11 The material is on the order of Ω / ; the P-GaN hole injection structure (7) runs through the entire drift region, and the high-resistivity capping layer (9) forms an electrical connection with the gate metal (6), the P-GaN hole injection structure (7) and the drain (8) that can conduct current.
2. The high-voltage enhancement-mode HEMT device for suppressing current collapse according to claim 1, characterized in that: The cross-sectional shape of the high-resistivity capping layer (9) along the direction from the source side of the P-GaN gate (5) to the drain (8) is stepped.
3. The high-voltage enhancement-mode HEMT device for suppressing current collapse according to claim 1, characterized in that: The high-resistivity capping layer (9) extends towards the source side, covering the upper surface of the source electrode (4) and the Al between the source electrode (4) and the P-GaN gate (5). x Ga 1-x On the upper surface of the N layer (3), the high-resistivity capping layer (9) and the source electrode (4) form an electrical connection that enables current to be conducted.