Three-dimensional memory and methods of making the same, memory systems

Abstract

Embodiments of the present disclosure disclose a method for manufacturing a three-dimensional memory, comprising: providing a semiconductor layer; the semiconductor layer comprising a first region and a second region arranged along a first direction, the first direction being perpendicular to a thickness direction of the semiconductor layer; forming a stack structure of a plurality of insulating layers and a plurality of sacrificial layers alternately stacked on the semiconductor layer; forming a plurality of channel structures penetrating through the stack structure on the first region; forming a first gate slit extending along the first direction and penetrating through the stack structure on the second region; removing part of the sacrificial layers on the second region through the first gate slit; forming a second gate slit extending along the first direction and penetrating through the stack structure on the first region, the first gate slit and the second gate slit being in communication; and removing the sacrificial layers on the first region through the second gate slit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a three-dimensional memory and a manufacturing method thereof, and a memory system. BACKGROUND

[0002] Three-dimensional memory is a new type of flash memory, and a three-dimensional memory device solves the limitations of two-dimensional or planar flash memory by vertically stacking multiple layers of data storage units. The three-dimensional memory device has excellent precision, supports higher storage capacity in smaller space, has low cost and low power consumption, and can fully meet many needs. However, three-dimensional memory still faces many challenges.

[0003] DISCLOSURE

[0004] Embodiments of the present disclosure provide a three-dimensional memory and a manufacturing method thereof, and a memory system.

[0005] According to an aspect of the present disclosure, a manufacturing method of a three-dimensional memory is provided, comprising:

[0006] providing a semiconductor layer; the semiconductor layer comprises a first region and a second region arranged along a first direction, the first direction being perpendicular to a thickness direction of the semiconductor layer;

[0007] forming a stack structure of a plurality of insulating layers and a plurality of sacrificial layers alternately stacked on the semiconductor layer;

[0008] forming a plurality of channel structures penetrating the stack structure on the first region; and forming a first gate slit extending along the first direction and penetrating the stack structure on the second region;

[0009] removing part of the sacrificial layers on the second region through the first gate slit;

[0010] forming a second gate slit extending along the first direction and penetrating the stack structure on the first region, the first gate slit and the second gate slit being in communication;

[0011] removing the sacrificial layers on the first region through the second gate slit.

[0012] In the above scheme, the stack structure comprises a plurality of sub-stack structures stacked in a second direction, and the channel structure comprises a plurality of sub-channel structures stacked in the second direction, and each sub-channel structure in each sub-stack structure penetrates the sub-stack structure; the second direction is the thickness direction of the semiconductor layer.

[0013] In the above scheme, the forming of the stack structure and the channel structure comprises:

[0014] forming a first sub-stack structure on the semiconductor layer;

[0015] forming a first sub-tunnel hole penetrating through the first sub-stack structure on the first region, and filling the first sub-tunnel hole with a first sacrificial material;

[0016] forming a second sub-stack structure on the first sub-stack structure;

[0017] forming a second sub-tunnel hole penetrating through the second sub-stack structure on the first region, and filling the second sub-tunnel hole with the first sacrificial material; the second sub-tunnel hole is in communication with the first sub-tunnel hole;

[0018] forming a third sub-stack structure on the second sub-stack structure;

[0019] forming a third sub-tunnel hole penetrating through the third sub-stack structure on the first region, the third sub-tunnel hole is in communication with the second sub-tunnel hole;

[0020] removing the first sacrificial material in the first sub-tunnel hole and the second sub-tunnel hole, and forming a first sub-tunnel structure, a second sub-tunnel structure, and a third sub-tunnel structure in the first sub-tunnel hole, the second sub-tunnel hole, and the third sub-tunnel hole.

[0021] In the above solution, the forming of the second gate slit penetrating through the stack structure and extending along the first direction comprises:

[0022] forming a first sub-gate slit penetrating through the first sub-stack structure on the first region while forming the first sub-tunnel hole;

[0023] filling the first sub-gate slit with the first sacrificial material while filling the first sub-tunnel hole with the first sacrificial material;

[0024] forming a second sub-gate slit penetrating through the second sub-stack structure on the first region while forming the second sub-tunnel hole; the second sub-gate slit is in communication with the first sub-gate slit;

[0025] filling the second sub-gate slit with the first sacrificial material while filling the second sub-tunnel hole with the first sacrificial material;

[0026] forming a third sub-gate slit penetrating through the third sub-stack structure and extending along the first direction on the first region after removing part of the sacrificial layer on the second region; the third sub-gate slit is in communication with the second sub-gate slit;

[0027] removing the first sacrificial material in the first sub-gate slit and the second sub-gate slit, the first sub-gate slit, the second sub-gate slit, and the third sub-gate slit collectively constitute the second gate slit.

[0028] In the above aspect, the removing the portion of the sacrificial layer on the second region comprises:

[0029] The removing the portion of the sacrificial layer on the second region forms a first fill region;

[0030] The method further comprises:

[0031] forming a second sacrificial material in the first fill region and the first gate slit.

[0032] In the above aspect, the removing the portion of the sacrificial layer on the second region comprises:

[0033] The removing the portion of the sacrificial layer on the second region forms a first fill region;

[0034] The method further comprises:

[0035] forming a third sacrificial material in the second fill region and the second gate slit.

[0036] forming a contact hole through the stack structure on the second region;

[0037] The removing the second sacrificial material and the third sacrificial material.

[0038] In the above aspect, the removing the portion of the sacrificial layer on the second region comprises:

[0039] The removing the portion of the sacrificial layer on the second region forms a first fill region;

[0040] The method further comprises:

[0041] forming a contact hole through the stack structure on the second region before forming the third sub-gate slit;

[0042] The removing the second sacrificial material and the third sacrificial material.

[0043] In the above aspect, the method further comprises:

[0044] forming a conductive material in the first fill region and the second fill region after removing the second sacrificial material;

[0045] filling an insulating material in the first gate slit and the second gate slit.

[0046] In the above aspect, the semiconductor layer further comprises a third region; the third region is located between the first region and the second region, and a dummy channel structure through the stack structure is formed in the third region.

[0047] The method further includes:

[0048] forming a third gate slit while forming the second gate slit; the third gate slit extends along the first direction and penetrates the stack structure on the third region, and the third gate slit is in communication with the first gate slit and the second gate slit.

[0049] According to another aspect of the present disclosure, there is provided a three-dimensional memory formed using the manufacturing method according to any of the above-mentioned solutions.

[0050] According to another aspect of the present disclosure, there is provided another three-dimensional memory, which includes:

[0051] a stack structure; the stack structure includes insulating layers and conductive layers alternately stacked, and includes an array region and a contact region arranged along a first direction, the first direction being perpendicular to a second direction, the second direction being a direction in which the insulating layers and the conductive layers are stacked;

[0052] a channel structure located in the array region;

[0053] a first gate isolation structure located in the contact region, penetrating the stack structure and extending along the first direction;

[0054] a second gate isolation structure located in the array region, penetrating the stack structure and extending along the first direction, the second gate isolation structure being connected to the first gate isolation structure, the material of the first gate isolation structure being the same as or different from the material of the second gate isolation structure.

[0055] In the above-mentioned solution, the stack structure includes a plurality of sub-stack structures stacked along the second direction, and the channel structure includes a plurality of sub-channel structures stacked along the second direction, each sub-channel structure in each sub-stack structure penetrating the corresponding sub-stack structure.

[0056] In the above-mentioned solution, the stack structure includes a first sub-stack structure, a second sub-stack structure, and a third sub-stack structure stacked along the second direction, the channel structure includes a first sub-channel structure, a second sub-channel structure, and a third sub-channel structure stacked along the second direction, and the second gate isolation structure includes a first sub-gate isolation structure, a second sub-gate isolation structure, and a third sub-gate isolation structure stacked along the second direction; wherein,

[0057] the first sub-channel structure and the first sub-gate isolation structure penetrate the first sub-stack structure, the second sub-channel structure and the second sub-gate isolation structure penetrate the second sub-stack structure, and the third sub-channel structure and the third sub-gate isolation structure penetrate the third sub-stack structure.

[0058] In the above aspect, the three-dimensional memory further includes a plurality of contact structures located in the contact region and extending along the second direction; the plurality of contact structures have different depths along the second direction, and the contact structures with different depths are connected to different layers of the conductive layers.

[0059] In the above aspect, the stack structure further includes a plurality of sacrificial layers alternately stacked with the plurality of insulating layers, and the sacrificial layers and the conductive layers between two adjacent insulating layers are arranged side by side in a first plane, and the first plane is perpendicular to the second direction.

[0060] In the above aspect, the three-dimensional memory includes a three-dimensional NAND memory.

[0061] According to still another aspect of the present disclosure, a memory system is provided, including: one or more three-dimensional memories according to any one of the above aspects; and

[0062] a memory controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0063] The three-dimensional memory and the manufacturing method thereof, and the memory system provided by the embodiments of the present disclosure have the following beneficial effects. The manufacturing method of the three-dimensional memory includes: providing a semiconductor layer; the semiconductor layer includes a first region and a second region arranged along a first direction, and the first direction is perpendicular to a thickness direction of the semiconductor layer; forming a stack structure of a plurality of insulating layers and a plurality of sacrificial layers alternately stacked on the semiconductor layer; forming a plurality of channel structures penetrating through the stack structure on the first region; forming a first gate slit penetrating through the stack structure and extending along the first direction on the second region; removing part of the sacrificial layers on the second region through the first gate slit; forming a second gate slit penetrating through the stack structure and extending along the first direction on the first region, and the first gate slit and the second gate slit are in communication; and removing the sacrificial layers on the first region through the second gate slit. In the embodiments of the present disclosure, the first gate slit and the second gate slit are formed separately, so as to achieve the purpose of separately removing the sacrificial layers on the first region and part of the sacrificial layers on the second region. Since the first gate slit and the second gate slit are formed separately, the mutual influence when the sacrificial layers on the first region and part of the sacrificial layers on the second region are removed can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0064] Figure 1 A top view of a three-dimensional memory provided in the embodiments of the present disclosure Figure 1 ;

[0065] Figures 2-4A cross-sectional structure schematic diagram of a manufacturing process of a three-dimensional memory provided in an embodiment of the present disclosure;

[0066] Figure 5 A top view structure schematic diagram of a three-dimensional memory provided in an embodiment of the present disclosure Figure 2 ;

[0067] Figure 6a A three-dimensional structure schematic diagram of a three-dimensional memory provided in an embodiment of the present disclosure;

[0068] Figure 6b A top view structure schematic diagram of a three-dimensional memory provided in an embodiment of the present disclosure Figure 3 ;

[0069] Figure 7 A flowchart schematic diagram of a manufacturing method of a three-dimensional memory provided in an embodiment of the present disclosure;

[0070] Figures 8-25 A cross-sectional structure schematic diagram of a manufacturing process of another three-dimensional memory provided in an embodiment of the present disclosure;

[0071] Figure 26 A schematic diagram of an exemplary system having a memory system in an embodiment of the present disclosure;

[0072] Figure 27 A schematic diagram of an exemplary memory card having a memory system in an embodiment of the present disclosure;

[0073] Figure 28 A schematic diagram of an exemplary solid state drive having a memory system in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0074] In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further described in detail below with reference to the drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present disclosure and to enable the scope of the present disclosure to be fully conveyed to those skilled in the art.

[0075] The present disclosure will be described in more detail in the following paragraphs with reference to the drawings. The advantages and features of the present disclosure will be more clearly understood from the following description and claims. It should be noted that the drawings are very simplified and use non-precise proportions, only to facilitate, clearly assist the purpose of illustrating the embodiments of the present disclosure.

[0076] It will be understood that the terms "on," "over," and "above" in the disclosure are to be interpreted in the broadest context possible so that "on" not only means "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes being "on" something with intervening features or layers therebetween.

[0077] Further, spatially relative terms, such as "on," "over," "above," "up," "upper," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0078] In embodiments of the disclosure, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Further, the substrate can comprise a variety of semiconductor materials, such as silicon, silicon germanium, germanium, arsenic, phosphorous, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0079] In embodiments of the disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of an underlying or overlying structure, or can have a scope less than the scope of the underlying or overlying structure. Further, a layer can be a region of a continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A layer can include multiple sub-layers. For example, an interconnect layer can include one or more conductor and contact sub-layers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sub-layers.

[0080] In embodiments of the disclosure, the terms "first," "second," and the like, are used to distinguish between similar objects, not necessarily by their order or priority.

[0081] Embodiments of the present disclosure provide a method for manufacturing a three-dimensional memory, the method comprising: Figure 1 and Figure 2As shown, a semiconductor layer 101 is provided, and a stacked structure 104 is formed on the semiconductor layer 101. The stacked structure 104 includes an insulating layer 102 and a sacrificial layer 103 alternately stacked. The semiconductor layer 101 includes a first region 101-1, a third region 101-3, and a second region 101-2 arranged sequentially in the Y-axis direction. A plurality of channel structures 105 are provided on the stacked structure 104 in the first region 101-1, and a plurality of dummy channel structures 105 are provided on the stacked structure 104 in the third region 101-3. A contact hole 125 is provided on the stacked structure 104. A gate gap is formed in the stacked structure 104 extending from the stacked structure 104 on the first region 101-1 to the stacked structure 104 on the second region 101-2. The gate gaps on the first region 101-1, the third region 101-3, and the second region 101-2 have equal dimensions in the X-axis direction. Polysilicon is filled in the gate gap, and the gate gap filled with polysilicon constitutes a gate gap structure 131. Silicon oxide is formed on the stacked structure 104 to cover the polysilicon in the gate gap. Figure 3 As shown, a patterned first mask layer 133 is formed on silicon oxide using photolithography. The silicon oxide on the polysilicon in the second region 101-2 is removed through the first mask layer 133, forming a first groove 132, thus exposing the polysilicon in the second region 101-2. Figure 4 As shown, a wet etching solution is passed through the first groove 132 to remove the polysilicon on the second region 101-2, and the polysilicon in the gate gap 134 on the second region is also removed. Next, a portion of the sacrificial layer 103 on the second region 101-2 is removed using the gate gap 134 on the second region 101-2 to form a filled region. Sacrificial material is filled in both the filled region and the gate gap on the second region. A patterned second mask layer is then formed on silicon oxide using a photolithography process. The silicon oxide on the polysilicon in the first region 101-1 is removed through the second mask layer to form a second groove, exposing the polysilicon in the first region 101-1. Next, a wet etching solution is passed through the second groove to remove the polysilicon in the first region 101-1. The sacrificial layer 103 on the first region 101-1 is then removed using the gate gap on the first region 101-1.

[0082] It should be noted that, Figure 2 The left side of the middle dashed line shows that in Figure 1 A partial cross-sectional view of position AA'. Figure 2 The right side of the dashed line shows the... Figure 1 A partial cross-sectional view of the BB' position.

[0083] Figure 5After removing part of the sacrificial layer 103 and filling it with conductive material 126, the final three-dimensional memory is formed along a cross-sectional view of a certain sacrificial layer 103. Figure 5 As can be seen from the present embodiment, only a portion of the sacrificial layer 103 on both sides of the gate gap along the X-axis direction on the second region 101-2 is removed, and a portion of the sacrificial layer 103 on the second region 101-2 is not removed. After the removal of the portion of the sacrificial layer 103 on the second region 101-2 and the sacrificial layer 103 on the first region 101-1, a first filling region and a second filling region are formed, respectively. Conductive material 126 is filled in both the first filling region and the second filling region. Conductive material 126 is formed on the sidewalls and bottom walls of the contact hole, and insulating material 127 is formed in the contact hole 125 filled with conductive material 126. The conductive material 126 in the contact hole surrounds the insulating material. After the contact hole 125 is filled with conductive material 126 and insulating material 127, a contact structure 129 is formed. Insulating material is also filled in the gate gap to form a gate isolation structure 128 (e.g., Figure 5 (As shown in the dashed box), the sacrificial layers on both sides of the gate isolation structure 128 along the X-axis direction are partially removed and replaced with conductive material 126, thereby allowing the conductive material 126 in the contact hole 125 to connect with the conductive material 126 in the first filling region (around the gate isolation structure). Here, the conductive material 126 replaced by the sacrificial layer constitutes the conductive layer in the final product, and the conductive layer and the insulating layer are stacked alternately. Furthermore, as... Figure 2 As shown, a first insulating layer 135 is formed on a portion of the sidewall of the contact hole 125. The first insulating layer 135 does not cover the bottommost sacrificial layer 103 through which the contact hole 125 penetrates. The first insulating layer 135 ensures that only one conductive layer is led out from the contact structure. This example only illustrates the case where a single conductive layer is led out from the contact structure. The leading out of other conductive layers is similar to the above description. The contact structures corresponding to different conductive layers have different depths in the Z-axis direction. Figure 6b A top view of a three-dimensional memory structure is shown. Figure 6b It can be seen that the third region 101-3 can contain two parts, which are respectively set on both sides of the second region 101-2. The first region 101-1 can also contain two parts, which are respectively set on both sides of the second region 101-2.

[0084] Research has found that, in the methods provided in the above embodiments, such as Figure 6a as well as Figure 6bAs shown, on the one hand, since the polysilicon in the gate gap on the second region 101-2 is filled, a large amount of acid is used when removing the polysilicon on the second region 101-2. Furthermore, the acid has no directionality. When removing the polysilicon on the second region 101-2, the acid will travel along the open gate gap into the stacked structure 104 on the first region 101-1, causing some of the polysilicon in the gate gap on the first region 101-1 to be removed. Ultimately, this results in insufficient removal of the sacrificial layer 103 on the first region 101-1, causing bit line failure. On the other hand... The method provided in the above embodiments requires two photolithography and two etching processes to expose the polysilicon on the first region 101-1 and the second region 101-2 respectively. The process involves many steps and is costly. Furthermore, with the trend of memory miniaturization, the size of the third region 101-3 in the Y-axis direction is getting smaller and smaller. This means that when removing the polysilicon on the second region 101-2, the polysilicon on the third region 101-3 is insufficient, resulting in the partial removal of the polysilicon on the first region 101-1.

[0085] In addition, in multi-stack structures, the etching of vias often employs multiple etching methods, while the etching of gate gaps often employs a single etching method. However, as the number of NAND layers increases, the single etching process for gate gaps encounters a bottleneck, with severe tilting issues. How to form vias and gate gaps with a large depth-to-width ratio in multi-stack structures, while reducing process difficulty and saving process steps, based on the separate removal of the sacrificial layer on the first region and part of the sacrificial layer on the second region, has become an urgent problem to be solved.

[0086] In view of this, in order to solve the above problems, this disclosure provides another method for manufacturing a three-dimensional memory. Figure 7 This is a schematic flowchart illustrating a method for fabricating a three-dimensional memory provided in an embodiment of this disclosure. Figure 7 As shown, the method for fabricating a three-dimensional memory provided in this embodiment includes the following steps:

[0087] S100: Provide a semiconductor layer; the semiconductor layer includes a first region and a second region arranged along a first direction, the first direction being perpendicular to the thickness direction of the semiconductor layer;

[0088] S200: A stacked structure of multiple insulating layers and multiple sacrificial layers alternately stacked is formed on the semiconductor layer;

[0089] S300: A plurality of channel structures penetrating the stacked structure are formed in the first region;

[0090] S400: A first gate slot is formed in the second region, penetrating the stacked structure and extending along the first direction;

[0091] S500: Remove a portion of the sacrificial layer on the second region through the first gate gap;

[0092] S600: A second gate slot is formed in the first region, penetrating the stacked structure and extending along the first direction, wherein the first gate slot communicates with the second gate slot;

[0093] S700: Remove the sacrificial layer on the first region through the second gate gap.

[0094] It should be understood that Figure 7 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 7 The steps shown can be adjusted in order according to actual needs. Figures 8 to 25 This is a cross-sectional schematic diagram illustrating the fabrication process of a three-dimensional memory provided in an embodiment of this disclosure. It should be noted that... Figures 8 to 25 This is a schematic diagram illustrating the complete manufacturing process of a three-dimensional memory. Unmarked parts in some of the accompanying drawings can be shared. The following section will discuss this further. Figure 7 , Figures 8 to 25 The method for manufacturing a three-dimensional memory provided in the embodiments of this disclosure will be described in detail.

[0095] In step S100, a semiconductor layer is mainly provided, which includes a first region and a second region arranged side by side along a first direction.

[0096] In some specific examples, the semiconductor layer 101 may include a substrate, which may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0097] In step S200, the main task is to form a stacked structure.

[0098] In some specific examples, the insulating layer 102 in the stacked structure may also be referred to as the dielectric layer. The material of the insulating layer 102 includes, but is not limited to, one or more of silicon oxide layers and silicon carbide layers. The material of the sacrificial layer 103 in the stacked structure includes, but is not limited to, one or more of silicon nitride layers and silicon oxide nitride layers. In some specific examples, both the insulating layer 102 and the sacrificial layer 103 can be formed by processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The insulating layer 102 and the sacrificial layer 103 may have the same thickness or different thicknesses. In some specific embodiments, the insulating layer 102 may be formed of silicon oxide (SiO2); the sacrificial layer 103 may be formed of silicon nitride (SiN), thereby forming a nitride-oxide (NO) stacked structure.

[0099] In some embodiments, the stacking structure includes a plurality of sub-stacked structures stacked in a second direction.

[0100] The solutions proposed in this disclosure are applicable to both single-stack and multi-stack structures. The following description uses a three-stack structure as an example, but the number of stacked structures in this disclosure is not limited to this; the number of stacked structures in this disclosure may also include, but is not limited to, 2, 4, or 5.

[0101] In step S300, the main task is to form the channel structure.

[0102] In some embodiments, the channel structure includes a plurality of sub-channel structures stacked in the second direction, wherein the sub-channel structure in each sub-stacked structure extends through the sub-stacked structure; the second direction is the thickness direction of the semiconductor layer.

[0103] The following will combine Figures 8 to 13 The formation of the stacked structure and the channel structure are described in detail.

[0104] In some embodiments, forming the stacked structure and the channel structure includes:

[0105] like Figures 8 to 9 As shown, a first sub-stack structure 108 is formed on the semiconductor layer 101;

[0106] A first sub-channel hole 109 is formed in the first region 101-1, penetrating the first sub-stack structure 108, and the first sub-channel hole 109 is filled with a first sacrificial material 111;

[0107] likeFigures 10 to 11 As shown, a second sub-stack structure 112 is formed on the first sub-stack structure 108;

[0108] A second sub-channel hole 113 is formed in the first region 101-1, penetrating the second sub-stack structure 112, and a first sacrificial material 111 is filled in the second sub-channel hole 113; the second sub-channel hole 113 communicates with the first sub-channel hole 109;

[0109] like Figures 12 to 13 As shown, a third sub-stack structure 115 is formed on the second sub-stack structure 112;

[0110] A third sub-channel hole 116 is formed in the first region 101-1, penetrating the third sub-stack structure 115, and the third sub-channel hole 116 communicates with the second sub-channel hole 113;

[0111] Remove the first sacrificial material 111 from the first sub-channel hole 109 and the second sub-channel hole 113, and form a first sub-channel structure 117, a second sub-channel structure 118, and a third sub-channel structure 119 in the first sub-channel hole 109, the second sub-channel hole 113, and the third sub-channel hole 116.

[0112] Here, the first sub-stack structure 108, the second sub-stack structure 112, and the third sub-stack structure 115 together constitute the stack structure 104. The first sub-channel structure 117, the second sub-channel structure 118, and the third sub-channel structure 119 together constitute the channel structure 105.

[0113] It should be noted that, Figures 8 to 25 Each view includes two cross-sectional views separated by a dashed line. The left portion is a partial cross-sectional view along a third direction in the first region 101-1, and the right portion is a partial cross-sectional view along a third direction in the second region 101-2. Here, the third direction is perpendicular to both the first and second directions.

[0114] In some specific examples, the first direction is the Y-axis direction shown in the accompanying drawings of this disclosure; the second direction is the Z-axis direction shown in the accompanying drawings of this disclosure; and the third direction is the X-axis direction shown in the accompanying drawings of this disclosure. However, it should be noted that the descriptions of directions in the following embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0115] In some specific examples, the methods for forming the first sub-channel via 109, the second sub-channel via 113, the third sub-channel via 116, the first sub-gate slot 110, and the second sub-gate slot 114 include, but are not limited to, dry plasma etching processes.

[0116] In some specific examples, the first sacrificial material 111 includes, but is not limited to, carbon and polycrystalline silicon.

[0117] In some specific examples, the methods for filling the first sacrificial material 111 include, but are not limited to, PVD, CVD, and ALD processes.

[0118] The selection of the first sacrificial material 111 needs to consider that the first sacrificial material 111 has a certain etching selectivity relative to the materials of the insulating layer 102 and the sacrificial layer 103, so that the impact on the insulating layer 102 and the sacrificial layer 103 can be reduced when the first sacrificial material 111 is removed.

[0119] In some specific examples, the formation process of the channel structure may include: forming a channel hole that penetrates the stacked structure; after forming the channel hole, forming a barrier layer, a charge trapping layer, a tunneling layer, and a channel layer sequentially from the outside to the inside along the radial direction of the channel hole, thereby forming a memory material layer in the channel hole. The barrier layer covers the sidewall surface of the channel hole, the charge trapping layer covers the surface of the barrier layer, the tunneling layer covers the surface of the charge trapping layer, and the channel layer covers the surface of the tunneling layer, forming an oxide-nitride-oxide-polysilicon (ONOP) structure. The barrier layer is used to prevent charge from flowing out of the memory material layer; the charge trapping layer is used to trap and store charge; the tunneling layer is used to generate charge; and the channel layer serves a supporting function. In some specific examples, the memory material layer can be formed using processes such as CVD or ALD. After forming the memory material layer, a through-hole process is required at the bottom of the memory material layer to obtain the memory layer; this through-hole process can be achieved using dry etching.

[0120] In step S400, as Figure 14 As shown, the first grid gap 106 is mainly formed in the second region 101-2.

[0121] Here, the first gate gap 106 penetrates the first sub-stack structure 108, the second sub-stack structure 112, and the third sub-stack structure 115.

[0122] Regarding the formation process of the first gate slot 106, besides as Figure 14 In addition to forming the first gate gap 106 in the first sub-stack structure 108, the second sub-stack structure 112, and the third sub-stack structure 115 as shown, the first gate gap 106 can also be formed by the following method.

[0123] While forming the first sub-channel hole 109 and the first sub-gate slot 110, a first portion of the first gate slot penetrating the first sub-stacking structure 108 is formed in the second region 101-2; while filling the first sub-channel hole 109 and the first sub-gate slot 110 with first sacrificial material 111, the first portion of the first gate slot is also filled with first sacrificial material 111; while forming the second sub-channel hole 113 and the second sub-gate slot 114, a first portion of the first gate slot penetrating the second sub-stacking structure 112 is formed in the second region 101-2. The second part of the gate slot; while filling the second sub-channel hole 113 and the second sub-gate slot 114 with the first sacrificial material 111, the second part of the first gate slot is also filled with the first sacrificial material 111; after forming the first sub-channel structure 117, the second sub-channel structure 118 and the third sub-channel structure 119, a third part of the first gate slot penetrating the third sub-stacking structure 115 is formed on the second region 101-2, and the first part, the second part and the third part of the first gate slot together constitute the first gate slot 106.

[0124] Understandably, in the above scheme, on the one hand, the first gate gap in the triple-stacked structure is formed in three parts, which greatly reduces the difficulty of forming the first gate gap 106 with a large depth-to-width ratio; on the other hand, the formation of the first part of the first gate gap is combined with the formation of the first sub-channel hole 109 and the first sub-gate gap 110, and the formation of the second part of the first gate gap is combined with the formation of the second sub-channel hole 113 and the second sub-gate gap 114. That is to say, although the first gate gap 106 is formed in three parts, no additional process steps are added.

[0125] In step S500, as Figures 15 to 16 As shown, the main process involves removing a portion of the sacrificial layer 103 on the second region 101-2 through the first gate gap 106.

[0126] In some specific examples, the methods for removing part of the sacrificial layer 103 on the second region 101-2 include, but are not limited to, wet etching processes.

[0127] In some embodiments, such as Figure 15 As shown, removing part of the sacrificial layer 103 on the second region 101-2 includes:

[0128] Remove a portion of the sacrificial layer 103 on the second region 101-2 to form the first filling region 121;

[0129] like Figure 16 As shown, the method further includes:

[0130] A second sacrificial material 122 is formed in the first filling region 121 and the first grid gap 106.

[0131] In some specific examples, the second sacrificial material 122 includes, but is not limited to, carbon and polycrystalline silicon.

[0132] In some specific examples, the methods for filling the second sacrificial material 122 include, but are not limited to, PVD, CVD, and ALD processes.

[0133] Here, as Figure 15 As shown, when removing part of the sacrificial layer 103 on the second region 101-2 through the first gate gap 106, only a portion of the sacrificial layer 103 around the first gate gap 106 is removed. In subsequent processes, conductive material 126 (such as...) will be filled into the first filling region 121. Figure 5 (as shown in the image).

[0134] It is understood that in the solution provided by the above embodiments of this disclosure, in the multi-stack structure, when removing part of the sacrificial layer 103 on the second region 101-2, only the first sub-gate gap 110 and the second sub-gate gap 114 are formed on the first region 101-1, and the first sub-gate gap 110 and the second sub-gate gap 114 are filled with the first sacrificial material 111. The third sub-gate gap 120 has not yet been formed in the third sub-stack structure on the first region 101-1. Therefore, when removing part of the sacrificial layer 103 on the second region 101-2 through the second gate gap 107, the impact on the sacrificial layer 103 on the first region 101-1 can be reduced, and the purpose of separating and removing the sacrificial layer 103 on the first region 101-1 and part of the sacrificial layer 103 on the second region 101-2 can be achieved.

[0135] Regarding the specific methods for forming the second gate gap 107 and removing the sacrificial layer 103 on the first region 101-1 via the second gate gap 107, the following embodiments of this disclosure provide two specific solutions, which will be discussed in conjunction with... Figures 17-21 , Figures 22-25 Provide a detailed explanation. Figures 17-21 This is the cross-sectional view corresponding to Scheme 1. Figures 22-25 This is the cross-sectional view corresponding to Scheme 2.

[0136] In step S600, the second gate gap 107 is mainly formed on the first region 101-1.

[0137] In some embodiments, forming the second gate slot 107 that penetrates the stacked structure and extends along the first direction includes:

[0138] like Figures 8 to 9 As shown, while forming the first sub-channel hole 109, a first sub-gate slot 110 penetrating the first sub-stack structure 108 is formed in the first region 101-1;

[0139] While filling the first sub-channel hole 109 with the first sacrificial material 111, the first sub-gate gap 110 is also filled with the first sacrificial material 111.

[0140] like Figures 10 to 11 As shown, while forming the second sub-channel hole 113, a second sub-gate slot 114 penetrating the second sub-stack structure 112 is formed in the first region 101-1; the second sub-gate slot 114 communicates with the first sub-gate slot 110.

[0141] While filling the second sub-channel hole 113 with the first sacrificial material 111, the second sub-gate gap 114 is also filled with the first sacrificial material 111.

[0142] After removing part of the sacrificial layer 103 on the second region 101-2, a third sub-gate slot 120 is formed on the first region 101-1, penetrating the third sub-stack structure 115 and extending along the first direction; the third sub-gate slot 120 communicates with the second sub-gate slot 114;

[0143] The first sacrificial material 111 in the first sub-gate gap 110 and the second sub-gate gap 114 is removed, and the first sub-gate gap 110, the second sub-gate gap 114 and the third sub-gate gap 120 together constitute the second gate gap 107.

[0144] It is understood that the solution provided in the above embodiments forms and fills the first sub-channel hole 109 and the first sub-gate gap 110 simultaneously in the first sub-stacking structure 108, and forms and fills the second sub-channel hole 113 and the second sub-gate gap 114 simultaneously in the second sub-stacking structure 112. That is, the sub-channel holes are formed in the sub-stacking structure respectively, and the processes of the channel holes and the gate gaps are combined. This can save process steps and reduce the process difficulty of forming channel holes and gate gaps with large depth-to-width ratios.

[0145] In some embodiments, the method further includes:

[0146] Before forming the third sub-gate gap 120, a contact hole 125 is formed in the second region 101-2 that penetrates the stacked structure.

[0147] In some specific examples, the methods for forming the third sub-gate gap 120 include, but are not limited to, dry etching processes.

[0148] In some specific examples, the method for removing the first sacrificial material 111 from the first sub-gate slot 110 and the second sub-gate slot 114 includes, but is not limited to, wet etching processes.

[0149] In Option 1, such asFigure 17 As shown, after filling the first filling region 121 and the first gate gap 106 with the second sacrificial material 122, a third sub-gate gap 120 is formed on the first region 101-1, penetrating the third sub-stack structure 115 and extending along the first direction, and the first sacrificial material 111 in the first sub-gate gap 110 and the second sub-gate gap 114 is removed. The first sub-gate gap 110, the second sub-gate gap 114 and the third sub-gate gap 120 together constitute the second gate gap 107.

[0150] In Option 2, such as Figures 22-23 As shown, after filling the first filling region and the first gate gap with the second sacrificial material, the third sub-stack structure 115 is not formed first. Instead, a contact hole 125 penetrating the stack structure 104 is formed on the second region 101-2. After forming the contact hole 125, a third sub-gate gap 120 penetrating the third sub-stack structure 115 and extending along the first direction is formed on the first region 101-1. The first sacrificial material 111 in the first sub-gate gap 110 and the second sub-gate gap 114 is removed. The first sub-gate gap 110, the second sub-gate gap 114 and the third sub-gate gap 120 together constitute the second gate gap 107.

[0151] It should be noted that before forming the third sub-gate gap in the first region, sacrificial material will be filled into the contact hole 125. Figure 22 (Not shown in the diagram), thereby protecting the contact hole 125 from damage caused by subsequent processes forming a second gate slot in the first region. The sacrificial material here includes, but is not limited to, carbon.

[0152] like Figure 22 As shown, the bottom of the contact hole 125 has an extension portion of a first plane, which is perpendicular to the second direction. In subsequent process steps, conductive material is filled in the first filling region, the sidewalls and bottom wall of the contact hole, and the second filling region. The conductive material in the second filling region can form a gate. The conductive material in the first filling region, the conductive material in the second filling region, and the conductive material in the contact hole 125 are all coupled, thereby achieving the purpose of leading out the gate using the conductive material in the contact hole 125.

[0153] It should be noted that, Figure 22 Only one contact hole 125 is shown in the diagram. In some specific examples, multiple contact holes 125 of different depths are also included. The resulting contact structures of different depths can achieve the purpose of leading out gates from different layers. In this architecture, it is not necessary to form steps to achieve the purpose of leading out gates from different layers, thereby greatly reducing process steps and saving process costs.

[0154] In some embodiments, the semiconductor layer 101 further includes a third region; the third region is located between the first region 101-1 and the second region 101-2, and a dummy channel structure is formed in the third region that penetrates the stacked structure;

[0155] The method further includes:

[0156] While forming the second gate slot 107, a third gate slot is formed; the third gate slot extends along the first direction and penetrates the stacked structure on the third region, and the third gate slot is connected to both the first gate slot 106 and the second gate slot 107.

[0157] Here, the dummy channel structure can be formed simultaneously with the channel structure, and the dummy channel structure is similar in structure to the channel structure. The multiple channel structures formed on the first region 101-1 are used to store data, while the multiple dummy channel structures formed on the third region are not used to store data. For example, the multiple dummy channel structures formed on the third region can serve a supporting function.

[0158] In some specific examples, the first sacrificial material 111 is filled in the third gate gap at the same time as the second gate gap 107 is filled with the first sacrificial material 111.

[0159] It is understandable that the third region is located between the first region 101-1 and the second region 101-2. After the third gate gap is filled with the first sacrificial material 111, it can better block acid and improve the problem that acid enters the first region 101-1 and affects the sacrificial layer 103 on the first region 101-1 when part of the sacrificial layer 103 on the second region 101-2 is removed.

[0160] In step S700, the sacrificial layer 103 on the first region 101-1 is mainly removed through the second gate gap 107.

[0161] In some embodiments, removing the sacrificial layer 103 on the first region 101-1 includes:

[0162] Remove the sacrificial layer 103 on the first region 101-1 to form the second filling region 123;

[0163] The method further includes:

[0164] A third sacrificial material 124 is formed in the second filling region 123 and the second grid gap 107;

[0165] A contact hole 125 is formed in the second region 101-2, penetrating the stacked structure;

[0166] Remove the second sacrificial material 122 and the third sacrificial material 124.

[0167] In some specific examples, the third sacrificial material 124 includes, but is not limited to, carbon and polycrystalline silicon.

[0168] In some specific examples, the methods for filling the third sacrificial material 124 include, but are not limited to, PVD, CVD, and ALD processes.

[0169] In some specific examples, the methods for forming the contact hole 125 include, but are not limited to, dry etching processes.

[0170] In some specific examples, the methods for removing the second sacrificial material 122 and the third sacrificial material 124 include, but are not limited to, wet etching processes.

[0171] Here, the first sacrificial material 111, the second sacrificial material 122, and the third sacrificial material 124 can be the same or different.

[0172] In Option 1, such as Figures 18-21 As shown, after forming the second gate gap 107, the sacrificial layer 103 on the first region 101-1 is removed to form the second filling region 123; a third sacrificial material 124 is formed in the second filling region 123 and the second gate gap 107; a contact hole 125 penetrating the stacked structure is formed on the second region 101-2; and the second sacrificial material 122 and the third sacrificial material 124 are removed.

[0173] Understandably, in Scheme 1, the contact hole 125 is formed after the sacrificial layer 103 on the first region 101-1 is removed. This reduces the impact of acid on the remaining sacrificial layer 103 on the second region 101-2 when the sacrificial layer 103 on the first region 101-1 is removed, as acid may pass through the contact hole 125.

[0174] In some embodiments, removing the sacrificial layer 103 on the first region 101-1 includes:

[0175] Remove the sacrificial layer 103 on the first region 101-1 to form the second filling region 123;

[0176] The method further includes:

[0177] After removing the sacrificial layer 103 on the first region 101-1, the second sacrificial material 122 in the first filling region 121 and the first gate gap 106 is removed.

[0178] In Option 2, such as Figures 24-25As shown, after the second gate gap 107 is formed, the sacrificial layer 103 on the first region 101-1 is removed to form the second filling region 123; next, the second sacrificial material 122 in the first filling region 121 and the first gate gap 106 is removed.

[0179] In some specific examples, after the contact hole 125 is formed, a sacrificial material can be formed in the contact hole 125, and then the sacrificial layer 103 on the first region 101-1 can be removed through the second gate gap 107. This can reduce the impact on the remaining sacrificial layer 103 on the second region 101-2 when the sacrificial layer 103 on the first region 101-1 is removed.

[0180] Understandably, in Scheme 2, since the contact hole 125 is formed before the third sub-gate gap 120 is formed, after removing the sacrificial layer 103 on the first region 101-1 to form the second filling region 123, it is not necessary to fill the second filling region 123 and the second gate gap 107 with sacrificial material again. Compared with Scheme 1, Scheme 2 can reduce the process of filling the second filling region 123 and the second gate gap 107 with the third sacrificial material 124 and reduce the process of removing the third sacrificial material 124, which can save process raw materials, save process steps, and thus save process costs.

[0181] In some specific examples, the method further includes forming a contact structure, the process of forming the contact structure including: forming a conductive material on the sidewalls and bottom wall of the contact hole 125, and forming an insulating material in the contact hole 125 in which the conductive material is formed, thereby realizing the lead-out of the gate.

[0182] In some specific examples, the conductive material includes, but is not limited to, tungsten metal.

[0183] In some embodiments, the method further includes:

[0184] After the second sacrificial material 122 is removed, conductive material is formed in the first filling region 121 and the second filling region 123;

[0185] Insulating material is filled into the first gate gap 106 and the second gate gap 107.

[0186] In some specific examples, the insulating material includes, but is not limited to, silicon oxide and silicon nitride.

[0187] In some specific examples, the conductive material filled in the second filling region 123 can be used to form a gate.

[0188] In some specific examples, the methods for filling conductive materials include, but are not limited to, PVC, CVD, and ALD.

[0189] Here, the first gate gap 106 and the second gate gap 107 together form a gate isolation structure after being filled with insulating material.

[0190] This disclosure provides a method for fabricating a three-dimensional memory, comprising: providing a semiconductor layer 101; the semiconductor layer 101 including a first region 101-1 and a second region 101-2 arranged along a first direction, the first direction being perpendicular to the thickness direction of the semiconductor layer 101; forming a stacked structure on the semiconductor layer 101 in which a plurality of insulating layers 102 and a plurality of sacrificial layers 103 are alternately stacked; forming a plurality of channel structures penetrating the stacked structure on the first region 101-1; forming a first gate gap 106 on the second region 101-2 penetrating the stacked structure and extending along the first direction; removing a portion of the sacrificial layer 103 on the second region 101-2 through the first gate gap 106; forming a second gate gap 107 on the first region 101-1 penetrating the stacked structure and extending along the first direction, the first gate gap 106 communicating with the second gate gap 107; and removing the sacrificial layer 103 on the first region 101-1 through the second gate gap 107. In this embodiment of the present disclosure, the first gate gap 106 and the second gate gap 107 are formed separately, thereby achieving the purpose of separately removing the sacrificial layer 103 on the first region 101-1 and part of the sacrificial layer 103 on the second region 101-2. Since the first gate gap 106 and the second gate gap 107 are formed separately, the mutual influence when separately removing the sacrificial layer 103 on the first region 101-1 and part of the sacrificial layer 103 on the second region 101-2 can be reduced.

[0191] According to another aspect of this disclosure, embodiments of this disclosure also provide a three-dimensional memory formed using a manufacturing method as described in any of the embodiments above.

[0192] According to another aspect of this disclosure, another three-dimensional memory is provided, the three-dimensional memory comprising:

[0193] A stacked structure; the stacked structure includes alternating layers of insulating and conductive layers, the stacked structure includes an array region and a contact region arranged along a first direction, the first direction being perpendicular to a second direction, and the second direction being the direction in which the insulating layer and the conductive layer are stacked;

[0194] A channel structure is located in the array region;

[0195] A first gate isolation structure is located in the contact region, penetrates the stacked structure, and extends along the first direction;

[0196] A second gate isolation structure is located in the array region, penetrates the stacked structure and extends along the first direction, the second gate isolation structure is connected to the first gate isolation structure, and the material of the first gate isolation structure is the same as or different from that of the second gate isolation structure.

[0197] In some embodiments, the stacked structure includes a plurality of sub-stacked structures stacked along the second direction, and the channel structure includes a plurality of sub-channel structures stacked along the second direction, wherein a sub-channel structure in each sub-stacked structure penetrates the corresponding sub-stacked structure.

[0198] In some embodiments, the stacked structure includes a first sub-stacked structure, a second sub-stacked structure, and a third sub-stacked structure stacked along the second direction; the channel structure includes a first sub-channel structure, a second sub-channel structure, and a third sub-channel structure stacked along the second direction; and the second gate isolation structure includes a first sub-gate isolation structure, a second sub-gate isolation structure, and a third sub-gate isolation structure stacked along the second direction.

[0199] The first sub-channel structure and the first sub-gate isolation structure penetrate the first sub-stack structure, the second sub-channel structure and the second sub-gate isolation structure penetrate the second sub-stack structure, and the third sub-channel structure and the third sub-gate isolation structure penetrate the third sub-stack structure.

[0200] In some embodiments, the three-dimensional memory further includes a plurality of contact structures located in the contact area and extending along the second direction; the plurality of contact structures have different depths along the second direction, and contact structures at different depths connect to different conductive layers.

[0201] In some embodiments, the stacked structure further includes a sacrificial layer, which is alternately stacked with the insulating layer, and the sacrificial layer and the conductive layer between two adjacent insulating layers are arranged side by side in a first plane, which is perpendicular to the second direction.

[0202] In some embodiments, the three-dimensional memory includes a three-dimensional NAND-type memory.

[0203] The three-dimensional memory provided in the above embodiments has been described in detail in the method section, and will not be repeated here.

[0204] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory system, including:

[0205] One or more three-dimensional memories as described in the above embodiments; and

[0206] A memory controller, which is coupled to and controls the three-dimensional memory.

[0207] In some specific examples, the memory system includes a memory card or a solid-state drive.

[0208] Figure 26 A block diagram of an exemplary system 200 having three-dimensional memory according to some aspects of this disclosure is shown. System 200 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 26 As shown, system 200 may include host 208 and memory system 202, the memory system 202 having one or more three-dimensional memories 204 and a memory controller 206. Host 208 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Host 208 may be configured to send data to or receive data from three-dimensional memories 204.

[0209] According to some embodiments, memory controller 206 is coupled to 3D memory 204 and host 208 and is configured to control 3D memory 204. Memory controller 206 can manage data stored in 3D memory 204 and communicate with host 208. In some embodiments, memory controller 206 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 206 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0210] The memory controller 206 can be configured to control the operation of the 3D memory 204, such as read, erase, and program operations. The memory controller 206 can also be configured to manage various functions related to data stored or to be stored in the 3D memory 204, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 206 is also configured to process error correction codes (ECC) regarding data read from or written to the 3D memory 204. The memory controller 206 can also perform any other suitable functions, such as formatting the 3D memory 204. The memory controller 206 can communicate with external devices (e.g., host 208) according to specific communication protocols. For example, the memory controller 206 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0211] The memory controller 206 and one or more three-dimensional memories 204 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 202 can be implemented and packaged into different types of end electronic products. Figure 27 In one example shown, the memory controller 206 and a single 3D memory 204 can be integrated into the memory card 302. The memory card 302 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 302 may also include a connection between the memory card 302 and a host computer (e.g., Figure 26 The host 208) is coupled to the memory card connector 304. In such a... Figure 28 In another example shown, the memory controller 206 and multiple 3D memories 204 can be integrated into the SSD 306. The SSD 306 may also include components for connecting the SSD 306 to a host computer (e.g., Figure 26 The SSD connector 308 is coupled to the host 208 in the memory card 302. In some embodiments, the storage capacity and / or operating speed of the SSD 306 is greater than that of the memory card 302.

[0212] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0213] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0214] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that, include: A semiconductor layer is provided; the semiconductor layer includes a first region and a second region arranged along a first direction, the first direction being perpendicular to the thickness direction of the semiconductor layer; A stacked structure of alternating insulating layers and sacrificial layers is formed on the semiconductor layer; Multiple channel structures penetrating the stacked structure are formed in the first region; A first gate slot is formed in the second region, penetrating the stacked structure and extending along the first direction; Part of the sacrificial layer on the second region is removed through the first gate gap; A second gate slot is formed in the first region, penetrating the stacked structure and extending along the first direction, and the first gate slot communicates with the second gate slot; The sacrificial layer on the first region is removed through the second gate gap.

2. The manufacturing method according to claim 1, characterized in that, The stacked structure includes a plurality of sub-stacked structures stacked in a second direction, and the channel structure includes a plurality of sub-channel structures stacked in the second direction, wherein a sub-channel structure in each sub-stacked structure extends through the sub-stacked structure; the second direction is the thickness direction of the semiconductor layer.

3. The manufacturing method according to claim 1, characterized in that, Forming the stacked structure and the channel structure includes: A first sub-stack structure is formed on the semiconductor layer; A first sub-channel hole is formed in the first region, penetrating the first sub-stack structure, and the first sub-channel hole is filled with a first sacrificial material; A second sub-stack structure is formed on the first sub-stack structure; A second sub-channel hole is formed in the first region, penetrating the second sub-stack structure, and a first sacrificial material is filled in the second sub-channel hole; the second sub-channel hole communicates with the first sub-channel hole; A third sub-stack structure is formed on the second sub-stack structure; A third sub-channel hole is formed in the first region, penetrating the third sub-stack structure, and the third sub-channel hole communicates with the second sub-channel hole; Remove the first sacrificial material from the first sub-channel hole and the second sub-channel hole, and form the first sub-channel structure, the second sub-channel structure, and the third sub-channel structure in the first sub-channel hole, the second sub-channel hole, and the third sub-channel hole.

4. The manufacturing method according to claim 3, characterized in that, The formation of the second gate slot, which penetrates the stacked structure and extends along the first direction, includes: While forming the first sub-channel hole, a first sub-gate slot penetrating the first sub-stack structure is formed in the first region; While filling the first sub-channel hole with the first sacrificial material, the first sub-gate gap is also filled with the first sacrificial material; While forming the second sub-channel hole, a second sub-gate slot is formed in the first region, penetrating the second sub-stack structure; the second sub-gate slot communicates with the first sub-gate slot; While filling the second sub-channel hole with the first sacrificial material, the second sub-gate gap is also filled with the first sacrificial material; After removing part of the sacrificial layer on the second region, a third sub-gate slot is formed on the first region, penetrating the third sub-stack structure and extending along the first direction; the third sub-gate slot communicates with the second sub-gate slot; The first sacrificial material in the first sub-gate slot and the second sub-gate slot is removed, and the first sub-gate slot, the second sub-gate slot, and the third sub-gate slot together constitute the second gate slot.

5. The manufacturing method according to claim 4, characterized in that, The removal of a portion of the sacrificial layer on the second region includes: Remove a portion of the sacrificial layer from the second region to form the first filling region; The method further includes: A second sacrificial material is formed in the first filling region and the first grid gap.

6. The manufacturing method according to claim 5, characterized in that, Removing the sacrificial layer on the first region includes: Remove the sacrificial layer on the first region to form the second filling region; The method further includes: A third sacrificial material is formed in the second filling region and the second grid gap; A contact hole is formed in the second region, penetrating the stacked structure; Remove the second and third sacrificial materials.

7. The manufacturing method according to claim 5, characterized in that, Removing the sacrificial layer on the first region includes: Remove the sacrificial layer on the first region to form the second filling region; The method further includes: Before forming the third sub-gate gap, a contact hole penetrating the stacked structure is formed in the second region; After removing the sacrificial layer on the first region, the second sacrificial material in the first filling region and the first grid gap is removed.

8. The manufacturing method according to claim 6 or 7, characterized in that, The method further includes: After the second sacrificial material is removed, a conductive material is formed in both the first filling region and the second filling region; Insulating material is filled into the first and second grid gaps.

9. The manufacturing method according to claim 1, characterized in that, The semiconductor layer further includes a third region; the third region is located between the first region and the second region, and a dummy channel structure is formed in the third region that penetrates the stacked structure. The method further includes: While forming the second gate gap, a third gate gap is formed; the third gate gap extends along the first direction and penetrates the stacked structure on the third region, and the third gate gap is connected to both the first gate gap and the second gate gap.

10. A three-dimensional memory, characterized in that, The three-dimensional memory adopts the method described in claim 1. Formed by any one of the manufacturing methods described in item 9.

11. A three-dimensional memory, characterized in that, include: Layered structure; The stacked structure includes alternating layers of insulating and conductive layers, and includes an array region and a contact region arranged along a first direction, the first direction being perpendicular to a second direction, the second direction being the direction in which the insulating and conductive layers are stacked. A channel structure is located in the array region; A first gate isolation structure is located in the contact region, penetrates the stacked structure, and extends along the first direction; A second gate isolation structure is located in the array region, penetrates the stacked structure and extends along the first direction, the second gate isolation structure is connected to the first gate isolation structure, and the material of the first gate isolation structure is the same as or different from that of the second gate isolation structure; wherein, the first gate isolation structure and the second gate isolation structure are arranged along the first direction; A contact structure is located in the contact area and extends along the second direction; the contact structure includes an insulating core extending along the second direction and a conductive body surrounding the insulating core; the bottom of the conductive body has an extension portion on a first plane perpendicular to the second direction.

12. The three-dimensional memory according to claim 11, characterized in that, The stacked structure includes a plurality of sub-stacked structures stacked along the second direction, and the channel structure includes a plurality of sub-channel structures stacked along the second direction, wherein a sub-channel structure in each sub-stacked structure penetrates the corresponding sub-stacked structure.

13. The three-dimensional memory according to claim 11, characterized in that, The stacked structure includes a first sub-stacked structure, a second sub-stacked structure, and a third sub-stacked structure stacked along the second direction; the channel structure includes a first sub-channel structure, a second sub-channel structure, and a third sub-channel structure stacked along the second direction; and the second gate isolation structure includes a first sub-gate isolation structure, a second sub-gate isolation structure, and a third sub-gate isolation structure stacked along the second direction. The first sub-channel structure and the first sub-gate isolation structure penetrate the first sub-stack structure, the second sub-channel structure and the second sub-gate isolation structure penetrate the second sub-stack structure, and the third sub-channel structure and the third sub-gate isolation structure penetrate the third sub-stack structure.

14. The three-dimensional memory according to claim 11, characterized in that, The three-dimensional memory also includes multiple contact structures, which are located in the contact area and extend along the second direction; the multiple contact structures have different depths along the second direction, and the contact structures at different depths are connected to different conductive layers.

15. The three-dimensional memory according to claim 11, characterized in that, The stacked structure further includes a sacrificial layer, which is alternately stacked with the insulating layer, and the sacrificial layer and the conductive layer between two adjacent insulating layers are arranged side by side in a first plane, which is perpendicular to the second direction.

16. The three-dimensional memory according to claim 11, characterized in that, The three-dimensional memory includes a three-dimensional NAND type memory.

17. A memory system, characterized in that, include: One or more as claimed in claim 10 The three-dimensional memory described in any one of the 16 claims; as well as A memory controller, which is coupled to and controls the three-dimensional memory.

Images