An improved digital filter processing circuit
By using an improved digital filtering circuit, combined with finite state machine and group overlap processing with bubble sort, the measurement error problem of AD acquisition data was solved, achieving high-precision data processing and smooth waveform restoration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING MXTRONICS CORP
- Filing Date
- 2022-09-29
- Publication Date
- 2026-07-24
Smart Images
Figure CN115603748B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an improved digital filtering circuit. Background Technology
[0002] During signal transmission, spatial noise interference can cause significant measurement errors and large variances in the data acquired by an analog-to-digital converter (ADC). Simply using a simple summation and averaging method is insufficient to eliminate these errors, thus failing to guarantee the overall system's measurement accuracy. With the widespread application of high-precision ADC circuits, these issues have become increasingly critical, necessitating effective data processing methods. Summary of the Invention
[0003] The technical problem solved by this invention is to address the shortcomings of existing AD measurement methods by providing an improved digital filtering processing circuit. This circuit enables data processing of AD-acquired data, employs a grouped overlapping processing mechanism for preprocessing, performs bubble sort on the processed data, and finally outputs the median. This effectively improves the measurement accuracy of AD-acquired data and enhances the overall performance of the AD measurement system.
[0004] The technical solution of this invention is:
[0005] An improved digital filtering circuit is used to process data acquired by an analog-to-digital converter (A / D converter), comprising: an A / D data acquisition module, an A / D data processing core module, and an A / D data storage module;
[0006] The AD data acquisition module uses finite state machine technology to output control signals according to the timing relationship of the AD devices, control the AD devices, and write the acquired AD data into the AD data storage module using the finite state machine.
[0007] The AD data processing core module processes the AD acquisition data collected by the AD data acquisition module and stored in the AD data storage module, and outputs the processing results.
[0008] The AD data storage module temporarily stores the AD acquired data according to the control signals of the AD data acquisition module and the AD data processing core module.
[0009] Furthermore, the digital filtering circuit is implemented based on an FPGA.
[0010] Furthermore, the AD data processing core module employs a grouped overlapping processing mechanism to preprocess the stored data.
[0011] Furthermore, the preprocessing of stored data using a grouped overlapping processing mechanism means that the AD data processing core module groups the data stored in the AD data storage module and reads data from different addresses in a fixed number of overlapping steps for further processing by the subsequent bubble sort algorithm.
[0012] Furthermore, the AD data processing core module reads the corresponding address data sequentially and incrementally from the AD data storage module, reading addresses A0-A in groups. m-1 A n —A m+n-1 A 2n —A m+2n-1 A 3n —A m+3n -1, ..., and so on, storing a fixed number of m data entries; where the parameter m represents the fixed number of data entries output by the group overlap processing mechanism, and n represents the number of data entries read in each subsequent read, except for the first read.
[0013] Furthermore, the quantitative relationship between m and n is n <m<2n。
[0014] Furthermore, the core AD data processing module uses the bubble sort method to process the data after grouping overlap.
[0015] Furthermore, the AD data processing core module reads data from the AD data storage module at addresses B0 and B1, specifically data at addresses D0 and D1 respectively.
[0016] If D0 > D1, then write D0 and D1 back to B0 and B1 respectively;
[0017] If D0 ≤ D1, then write D0 and D1 back to B1 and B0 respectively, that is, swap the stored data at these two addresses; then, read the data D1 and D2 from B1 and B2.
[0018] If D1 > D2, then write D1 and D2 back to B1 and B2 respectively;
[0019] If D1≤D2, then write D1 and D2 back to B2 and B1 respectively;
[0020] This process is repeated to sort the entire sequence of collected data.
[0021] Furthermore, assuming there are a total of N collected data points, the entire collected data sequence can be sorted after N*(N-1) / 2 comparisons.
[0022] Furthermore, after sorting is complete, read A. N / 2 Or A (N+1) / 2 Data D was obtained N / 2 Or D (N+1) / 2This is the median of the sorted sequence. This data is output as the final result of the data processing.
[0023] Compared with the prior art, the present invention has the following advantages:
[0024] (1) Based on the signal characteristics and AD sampling rate, the present invention selects an appropriate value of m and adopts the technology described in the present invention to effectively filter out noise spikes in the signal transmission process. Compared with the prior art, due to the adoption of the sampling data grouping and overlapping processing mechanism, the difference between adjacent data after processing is reduced, the restored waveform is smoother, and the waveform restoration degree is high.
[0025] (2) When the variance of the AD acquisition measurement values is large, this invention applies a sorting and median-based processing method to obtain the AD acquisition digital value that is closest to the actual value. The logic circuit adopts a pipeline structure, resulting in small processing delays and not affecting the data processing capability of the entire measurement system.
[0026] (3) The circuit of the present invention is based on the built-in memory of the FPGA. When processing the AD acquisition data, the measurement data can be read from the memory, compared and processed, and then written back to the memory. As long as the memory capacity is sufficient, this scheme can improve the final processing accuracy by configuring the cache capacity parameter without changing the logic circuit design.
[0027] (4) To improve the reliability of the logic circuit, the readability of the hardware description language, and the scalability of the entire module, this invention adopts a finite state machine implementation as the main structure of the circuit. With this implementation, the hardware description code is clear and easy to read, and the scalability is greatly enhanced.
[0028] (5) This invention balances FPGA resource consumption and processing speed, selecting bubble sort as the main data sorting algorithm. The sorting module's main clock frequency is 50MHz, and calculations show that the processing time will not affect the data acquisition module. Attached Figure Description
[0029] Figure 1 This is a schematic diagram of the logic circuit module of the present invention;
[0030] Figure 2 A comparison of the grouping value ranges between existing technologies and the present invention;
[0031] Figure 3 A schematic diagram of AD data grouping overlap processing;
[0032] Figure 4 This is a schematic diagram of AD data bubbling processing. Detailed Implementation
[0033] The invention will now be further described with reference to the accompanying drawings.
[0034] like Figure 1 As shown, the present invention proposes an improved digital filtering processing circuit, which is implemented based on FPGA. The circuit includes: an AD data acquisition module 11, an AD data processing core module 12, and an AD data storage module 13.
[0035] This logic circuit is mainly used for data processing of the acquired AD digital signals. The AD data acquisition module 11 acquires the converted AD digital signals and uses a finite state machine to write the acquired AD digital signals into the FPGA's internal RAM memory. The AD data processing core module 12 then processes the data and finally outputs the resulting numerical value.
[0036] The AD data acquisition module 11 uses finite state machine technology to output control signals according to the timing relationship of the AD devices, control the AD devices, and write the acquired AD data into the AD data storage module 13 using the finite state machine.
[0037] The AD data processing core module 12 preprocesses the stored data based on the AD acquisition data acquired by the AD data acquisition module 11 and stored in the AD data storage module 13, and outputs the processing results.
[0038] The AD data storage module 13 temporarily stores the AD acquired data according to the control signals of the AD data acquisition module 11 and the AD data processing core module 12.
[0039] Figure 2 The diagram shows a comparison of the grouping value ranges of the prior art and the present invention. The left side illustrates the grouping value ranges of the sampled data in the prior art, where each group value is relatively independent. The right side shows the grouping value ranges of the data in the present invention, where each group value partially overlaps, i.e., overlapping grouping data processing.
[0040] Therefore, the preprocessing of stored data using the grouped overlapping processing mechanism means that the AD data processing core module groups the data stored in the AD data storage module and reads data from different addresses in a fixed number of overlapping steps for further processing by the subsequent bubble sort algorithm.
[0041] Further as Figure 3 As shown, the logic circuit of this invention is based on FPGA, balancing area and performance. The AD data processing core module uses a grouped overlapping processing mechanism to process the data acquired and stored by the AD. The AD data processing module reads A0-A1 from the AD data storage module respectively. m-1 A n—A m+n-1 A 2n —A m+2n-1 A 3n —A m+3n -1, ..., and so on, the data at the address are read, a fixed number of m data are stored, and the output is processed by bubbling.
[0042] Where parameter m represents the fixed number of data points output by the group overlap processing mechanism, and n represents the number of data points read in each subsequent read, excluding the first read. The quantitative relationship between m and n is as follows: <m<2n。
[0043] Assume m = 15, n = 10, such as Figure 3 As shown, the first group reads addresses A0-A 14 The 15 read data points are output to the subsequent bubble sorting process, and the second group is read from address A. 15 —A 24 The 10 read data points are added to the last 5 data points read in the first group to form a new set of 15 data points, which are then output to the subsequent bubble sorting process. The third group reads data from address A. 25 —A 34 The 10 read data points are added to the last 5 data points read in the second group to form a new set of 15 data points, which are then output to the subsequent bubble sorting process. This process is repeated for each subsequent data point read. The address ranges corresponding to the data read in the three previous steps are A0-A10. 14 A 10 —A 24 A 20 —A 34 This is consistent with the formula listed in the above-mentioned group overlap processing mechanism. Therefore, this method has a certain degree of universality.
[0044] like Figure 4 As shown, the bubble sort method in the core module of AD data processing processes the data after overlapping grouping. The AD data processing module reads data from addresses B0 and B1 in the AD data storage module, specifically data D0 and D1 respectively. If D0 > D1, D0 and D1 are written back to B0 and B1 respectively; if D0 ≤ D1, D0 and D1 are written back to B1 and B0 respectively, effectively swapping the stored data at these two addresses. Then, it reads data D1 and D2 from B1 and B2. If D1 > D2, D1 and D2 are written back to B1 and B2 respectively; if D1 ≤ D2, D1 and D2 are written back to B2 and B1 respectively.
[0045] Similarly, assuming there are N data points collected, the entire data sequence can be sorted after N*(N-1) / 2 comparisons.
[0046] After sorting is complete, read A. N / 2 Or A(N+1) / 2 Data D was obtained N / 2 Or D (N+1) / 2 This is the median of the sorted sequence. Output this data as the final result of the data processing.
[0047] Example
[0048] The RAM in the AD data storage module 13 of this invention is a 1K×16-bit FPGA internal block RAM. The storage module 13 temporarily stores the data acquired by the AD data acquisition module 11. The 1K capacity can be changed by modifying parameters. Theoretically, the more data acquired, the higher the accuracy after processing, but at the same time, the processing time will also increase, reducing the performance of the entire data processing module.
[0049] The main clock frequency is 50MHz with a period of 20ns. One data read plus comparison time is approximately 10 clock cycles, or 200ns. Assuming N data samples are processed, the entire comparison process takes approximately 100*N*(N-1)ns.
[0050] The parts of this invention not described in detail are common knowledge to those skilled in the art.
Claims
1. An improved digital filtering processing circuit for processing data acquired by an analog-to-digital converter (A / D converter), characterized in that... include: AD data acquisition module (11), AD data processing core module (12), AD data storage module (13). The AD data acquisition module (11) uses finite state machine technology to output control signals according to the timing relationship of AD devices, control AD devices, and write the acquired AD data into the AD data storage module (13) using finite state machine. The AD data processing core module (12) processes the AD acquisition data collected by the AD data acquisition module (11) and stored in the AD data storage module (13), and outputs the processing results. The AD data storage module (13) temporarily stores the AD acquired data according to the control signals of the AD data acquisition module (11) and the AD data processing core module (12); The AD data processing core module employs a grouping and overlapping processing mechanism to preprocess the stored data. This preprocessing involves grouping the data stored in the AD data storage module and reading data from different addresses in a fixed-number overlapping manner for further processing by the bubble sort algorithm. The AD data processing core module sequentially and incrementally reads data from the AD data storage module at addresses A0-A1, grouping them together. m-1 A n —A m+n-1 A 2n —A m+2n-1 A 3n —A m+3n-1 ... and so on, storing a fixed number of m data entries; where the parameter m represents the fixed number of data entries output by the group overlap processing mechanism, and n represents the number of data entries read in each subsequent read, except for the first read.
2. The improved digital filtering circuit according to claim 1, characterized in that: The digital filtering circuit is implemented based on an FPGA.
3. The improved digital filtering circuit according to claim 1, characterized in that: The quantitative relationship between m and n is n <m<2n。 4. The improved digital filtering circuit according to claim 1, characterized in that: The core module of AD data processing uses the bubble sort method to process data with overlapping groups.
5. An improved digital filtering circuit according to claim 4, characterized in that: The AD data processing core module reads data from addresses B0 and B1 from the AD data storage module, specifically data D0 and D1. If D0 > D1, then write D0 and D1 back to B0 and B1 respectively; If D0≤D1, then write D0 and D1 back to B1 and B0 respectively, that is, swap the stored data at these two addresses; Next, read the data D1 and D2 from B1 and B2; If D1 > D2, then write D1 and D2 back to B1 and B2 respectively; If D1≤D2, then write D1 and D2 back to B2 and B1 respectively; This process is repeated to sort the entire sequence of collected data.
6. An improved digital filtering circuit according to claim 5, characterized in that: Assuming there are N data points collected, the entire data sequence can be sorted after N*(N-1) / 2 comparisons.
7. An improved digital filtering circuit according to claim 6, characterized in that: After sorting is complete, read A. N / 2 Or A (N+1) / 2 Data D was obtained N / 2 Or D (N+1) / 2 This is the median of the sorted sequence. This data is output as the final result of the data processing.