Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate includes: a storage capacitor disposed on a base substrate and located in each pixel, the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the second electrode are located in the same layer, the second capacitor electrode and the gate are located in the same layer, and the first capacitor electrode at least includes an electrode body; and a tip structure, the tip structure and the first capacitor electrode are located in the same layer, and the tip structure includes a first tip substructure and a second tip substructure. In any pixel, the first tip substructure is connected to the side of the electrode body facing the first data line, the second tip substructure is connected to the side of the first data line facing the electrode body, the end of the first tip substructure facing the first data line is formed as a first tip, and the end of the second tip substructure facing the electrode body is formed as a second tip, and the first tip and the second tip are arranged oppositely and spaced apart.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] An electronic paper display device is a new display device that combines the advantages of both a display and paper. Its display effect is close to that of paper, and it has the advantages of flexible display, light weight, erasability, and low power consumption.

[0003] At present, electronic paper display products in the industry are shipped by coating a protective film after the array substrate process is completed. However, in actual production, it is found that huge static electricity is generated during the removal of the protective film, which may damage pixels and cause white spot defects.

[0004] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the invention

[0005] In order to solve at least one aspect of the above problems, embodiments of the present disclosure provide a display substrate and a display device.

[0006] In one aspect, a display substrate is provided, the display substrate comprising:

[0007] substrate substrate;

[0008] A plurality of gate lines and a plurality of data lines are arranged on the base substrate, each of the gate lines extends in a row direction, each of the data lines extends in a column direction, and the plurality of gate lines and the plurality of data lines are arranged to cross each other to surround and form a plurality of pixels;

[0009] At least one thin film transistor disposed on the substrate and located in each pixel, each thin film transistor comprising a gate, a first electrode and a second electrode, the first electrode being one of a source electrode and a drain electrode, and the second electrode being the other of the source electrode and the drain electrode;

[0010] A storage capacitor disposed on the base substrate and located in each pixel, the storage capacitor comprising a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the second capacitor electrode are disposed opposite to each other, the first capacitor electrode and the second electrode are located in the same layer, and the first capacitor electrode at least comprises an electrode body; and

[0011] a tip structure, the tip structure and the first capacitor electrode are located in the same layer, the tip structure includes a first tip substructure and a second tip substructure,

[0012] Among the data lines and gate lines surrounding any pixel, a data line electrically connected to the thin film transistor in the pixel is a first data line;

[0013] In any pixel, the first tip substructure is connected to the side of the electrode body facing the first data line, the second tip substructure is connected to the side of the first data line facing the electrode body, the end of the first tip substructure facing the first data line is formed as a first tip, and the end of the second tip substructure facing the electrode body is formed as a second tip, and the first tip and the second tip are arranged opposite to each other and spaced apart in the row direction.

[0014] According to some exemplary embodiments, the first capacitor electrode also includes a first protrusion, which is located between the electrode body and the first tip sub-structure; and the first protrusion protrudes toward the first data line of the pixel relative to the electrode body, and the first tip sub-structure is connected to the end of the first protrusion facing the first data line.

[0015] According to some exemplary embodiments, an orthographic projection of a capacitor body of the first capacitor electrode on the substrate falls within an orthographic projection of the second capacitor electrode on the substrate.

[0016] According to some exemplary embodiments, the first tip substructure has a first side close to the thin film transistor and a second side away from the thin film transistor, the first side of the first tip substructure and the second side of the first tip substructure converge toward the first data line and intersect at the first tip; and / or, the second tip substructure has a first side close to the thin film transistor and a second side away from the thin film transistor, the first side of the second tip substructure and the second side of the second tip substructure converge toward the electrode body and intersect at the second tip.

[0017] According to some exemplary embodiments, a distance between the first tip and the second tip along the row direction is between 1 and 10 micrometers.

[0018] According to some exemplary embodiments, the first tip substructure includes a first tip body portion, which is located between the first tip and the first protrusion, the first tip body portion having a first side close to the thin film transistor and a second side away from the thin film transistor, and the first side of the first tip body portion is parallel to the second side of the first tip body portion; and / or, the second tip substructure includes a second tip body portion, which is located between the second tip and the first data line, the second tip body portion having a first side close to the thin film transistor and a second side away from the thin film transistor, and the first side of the second tip body portion is parallel to the second side of the second tip body portion.

[0019] According to some exemplary embodiments, the distance between the first side surface of the first tip body portion and the second side surface of the first tip body portion along the column direction is between 3 and 10 microns; and / or, the distance between the first side surface of the second tip body portion and the second side surface of the second tip body portion along the column direction is between 3 and 10 microns.

[0020] According to some exemplary embodiments, among the data lines and gate lines surrounding any pixel, a gate line electrically connected to the thin film transistor in the pixel is a first gate line, another data line spaced apart from the first data line is a second data line, and another gate line spaced apart from the first gate line is a second gate line; and the second capacitor electrode has a first side facing the first gate line, the electrode body has a first side facing the first gate line, and the first side of the second capacitor electrode is closer to the first gate line than the first side of the electrode body; and / or, the second capacitor electrode has a second side facing the second gate line, the electrode body has a second side facing the second gate line, and the second side of the second capacitor electrode is closer to the second gate line than the second side of the electrode body; and / or, the second capacitor electrode has a third side facing the second data line, the electrode body has a third side facing the second data line, and the third side of the second capacitor electrode is closer to the second data line than the third side of the electrode body; and / or, the second capacitor electrode has a fourth side facing the first data line, the electrode body has a fourth side facing the first data line, and the fourth side of the second capacitor electrode is closer to the first data line than the fourth side of the electrode body.

[0021] According to some exemplary embodiments, the distance along the column direction between the orthographic projection of the first side of the second capacitor electrode on the substrate and the orthographic projection of the first side of the electrode body on the substrate is greater than 3 microns; and / or, the distance along the column direction between the orthographic projection of the second side of the second capacitor electrode on the substrate and the orthographic projection of the second side of the electrode body on the substrate is greater than 3 microns; and / or, the distance along the row direction between the orthographic projection of the third side of the second capacitor electrode on the substrate and the orthographic projection of the third side of the electrode body on the substrate is greater than 3 microns; and / or, the distance along the row direction between the orthographic projection of the fourth side of the second capacitor electrode on the substrate and the orthographic projection of the fourth side of the electrode body on the substrate is greater than 3 microns.

[0022] According to some exemplary embodiments, the display substrate further includes a pixel electrode disposed on the base substrate and located in each pixel, wherein the pixel electrode is electrically connected to the first capacitor electrode through at least one via hole, and an orthographic projection of the at least one via hole on the base substrate falls within an orthographic projection of the first protrusion on the base substrate.

[0023] According to some exemplary embodiments, the display substrate includes a plurality of the tip structures, which are spaced apart in the column direction; and in each of the tip structures, a first tip of the first tip substructure and a second tip of the second tip substructure are oppositely and spaced apart in the row direction.

[0024] According to some exemplary embodiments, the display substrate further includes a passivation layer, which is located between a layer where the pixel electrode is located and a layer where the first capacitor electrode is located; and at least a portion of the passivation layer is located in a gap between the first tip and the second tip.

[0025] According to some exemplary embodiments, the display substrate further includes a gate insulating layer, the gate insulating layer being located between a layer where the second capacitor electrode is located and a layer where the first capacitor electrode is located; and a dielectric constant of the gate insulating layer is greater than a dielectric constant of the passivation layer.

[0026] According to some exemplary embodiments, the at least one thin film transistor includes a first thin film transistor and a second thin film transistor; the first capacitor electrode includes a second protrusion, the second protrusion and the first protrusion are located on the same side of the electrode body, the second protrusion is electrically connected to the first electrode of the first thin film transistor, the second electrode of the first thin film transistor is electrically connected to the first electrode of the second thin film transistor, and the second electrode of the second thin film transistor is electrically connected to the first data line; and the display substrate also includes a common electrode line, the common electrode line extends along the row direction, and the common electrode line is electrically connected to the second capacitor electrode.

[0027] According to some exemplary embodiments, the second capacitor electrode and the gate are located in the same layer.

[0028] In another aspect, a display device is provided, wherein the display device includes the display substrate as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Other objects and advantages of the present disclosure will be apparent from the following description of the present disclosure with reference to the accompanying drawings and will help to have a comprehensive understanding of the present disclosure.

[0030] Figure 1 1 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure, wherein a plurality of (for example, 4) pixels included in the display substrate are schematically shown.

[0031] Figure 2 for Figure 1 A schematic plan view of a pixel included in a display substrate.

[0032] Figure 3 According to some exemplary embodiments of the present disclosure, the display substrate Figure 2 A cross-sectional view taken along line AA'.

[0033] Figure 4 According to some exemplary embodiments of the present disclosure, the display substrate Figure 2 A cross-sectional view taken along line BB'.

[0034] Figure 5 According to some exemplary embodiments of the present disclosure, the display substrate Figure 2 A cross-sectional view taken along line CC'.

[0035] Figure 6 According to some exemplary embodiments of the present disclosure, the display substrate Figure 2 A cross-sectional view taken along line DD'.

[0036] Figure 7is a cross-sectional view of a display device according to some exemplary embodiments of the present disclosure.

[0037] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0038] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of various exemplary embodiments. However, it is apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid making various exemplary embodiments unnecessarily obscure. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0039] In the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of the individual elements are not necessarily limited to the size and relative size shown in the drawings. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0040] When an element is described as being "on" another element, "connected to" another element or "coupled to" another element, the element may be directly on the other element, directly connected to the other element or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent" or "on..." versus "directly on...", etc. In addition, the term "connection" may refer to a physical connection, an electrical connection, a communication connection and / or a fluid connection. In addition, the X-axis, the Y-axis and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items.

[0041] It should be understood that, although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, a first element may be named a second element, and similarly, a second element may be named a first element.

[0042] Herein, unless otherwise specified, the expression "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, photoresist stripping, etc. The expression "one-time patterning process" means a process of forming patterned layers, components, members, etc. using one mask.

[0043] It should be noted that the expression "same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single composition process. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0044] It should be noted that, in order to clearly show the stacking relationship between various elements, parts, components or patterns, in the drawings of this article, unless otherwise specified, elements, parts, components or patterns located on the same layer are generally shown using the same cross-sectional lines.

[0045] It should be noted that, since the source and drain of a thin film transistor can be generally used interchangeably, in this article, the expressions "first electrode" and "second electrode" of the thin film transistor are used. It should be understood that the "first electrode" of the thin film transistor can refer to one of the source and drain of the thin film transistor, and the "second electrode" of the thin film transistor can refer to the other of the source and drain of the thin film transistor.

[0046] In this document, unless otherwise specified, the expressions "continuously arranged" and "continuously extending" mean that two regions, parts or components are continuously and uninterruptedly extended, connected or arranged, that is, the two regions, parts or components form an integral structure without a break between them.

[0047] An embodiment of the present disclosure provides a display substrate, which includes: a base substrate; a plurality of gate lines and a plurality of data lines arranged on the base substrate, each of the gate lines extending in a row direction, each of the data lines extending in a column direction, the plurality of gate lines and the plurality of data lines being arranged crosswise to surround and form a plurality of pixels; at least one thin film transistor arranged on the base substrate and located in each pixel, each thin film transistor including a gate, a first electrode and a second electrode, the first electrode being one of a source and a drain, and the second electrode being the other of the source and the drain; a storage capacitor arranged on the base substrate and located in each pixel, the storage capacitor including a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the second capacitor electrode being arranged opposite to each other, the first capacitor electrode and the second capacitor electrode being located in the same layer, the first capacitor electrode and the second capacitor electrode being located in the same layer. The second capacitor electrode is located in the same layer as the gate electrode, the first capacitor electrode at least includes an electrode body; and a tip structure, the tip structure is located in the same layer as the first capacitor electrode, the tip structure includes a first tip substructure and a second tip substructure, wherein, among the data lines and gate lines surrounding any pixel, a data line electrically connected to the thin film transistor in the pixel is the first data line; in any pixel, the first tip substructure is connected to the side of the electrode body facing the first data line, the second tip substructure is connected to the side of the first data line facing the electrode body, the end of the first tip substructure facing the first data line is formed as a first tip, the end of the second tip substructure facing the electrode body is formed as a second tip, and the first tip and the second tip are arranged oppositely and spaced in the row direction. In the embodiment of the present disclosure, by designing a tip structure in the layer where the upper electrode of the storage capacitor is located, static electricity can be induced to be released from the tip structure, avoiding static electricity from breaking through the gate insulating layer and damaging the lower electrode of the storage capacitor, thereby avoiding affecting the normal display of the pixel.

[0048] Figure 1 1 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure, wherein a plurality of (for example, 4) pixels included in the display substrate are schematically shown. Figure 2 for Figure 1 A schematic plan view of a pixel included in a display substrate. Figure 3 According to some exemplary embodiments of the present disclosure, the display substrate Figure 2 A cross-sectional view taken along line AA'. Figure 4 According to some exemplary embodiments of the present disclosure, the display substrate Figure 2 A cross-sectional view taken along line BB'. Figure 5 According to some exemplary embodiments of the present disclosure, the display substrate Figure 2 A cross-sectional view taken along line CC'. Figure 6According to some exemplary embodiments of the present disclosure, the display substrate Figure 2 A cross-sectional view taken along line DD'. Figure 7 is a cross-sectional view of a display device according to some exemplary embodiments of the present disclosure.

[0049] For example, the display substrate may be a display substrate of an electronic paper display device, or may be an array substrate of the electronic paper display device.

[0050] Combined with reference Figures 1 to 6 , the display substrate may include a plurality of pixels P. Figure 1 In the figure, several (for example, 4) pixels P are shown by way of example. It should be understood that the display substrate may include more pixels P. Specifically, the display substrate includes: a base substrate 1; and a plurality of gate lines (or scan lines) GL, a plurality of data lines (or source lines) DL, and a plurality of common electrode lines CL arranged on the base substrate 1. The plurality of gate lines GL extend in parallel along the row direction X, the plurality of data lines DL extend in parallel along the column direction Y, and the plurality of common electrode lines CL extend in parallel along the row direction X, and each common electrode line CL is located between two adjacent gate lines GL. The plurality of gate lines GL and the plurality of data lines DL are arranged crosswise to surround and form a plurality of pixels P.

[0051] The display substrate may include at least one thin film transistor located in one pixel P. For example, in some exemplary embodiments, the at least one thin film transistor may include two thin film transistors. For the convenience of description, the two thin film transistors are respectively referred to as a first thin film transistor T1 and a second thin film transistor T2. The first thin film transistor T1 is farther away from the data line DL than the second thin film transistor T2. Figure 1 and Figure 2 In one pixel, the first thin film transistor T1 is located on the left side of the second thin film transistor T2.

[0052] The first thin film transistor T1 includes a first source electrode T1S, a first gate electrode T1G and a first drain electrode T1D, and the second thin film transistor T2 includes a second source electrode T2S, a second gate electrode T2G and a second drain electrode T2D. The first drain electrode T1D of the first thin film transistor T1 is electrically connected to the pixel electrode. The first source electrode T1S of the first thin film transistor T1 and the second drain electrode T2D of the second thin film transistor T2 are an integral structure. The gate line GL is electrically connected to the first gate electrode T1G of the first thin film transistor T1 and the second gate electrode T2G of the second thin film transistor T2, for example, the gate line GL, the first gate electrode T1G and the second gate electrode T2G are an integral structure, that is, they are a continuously extending integral structure. The second source electrode T2S of the second thin film transistor T2 is electrically connected to the data line DL.

[0053] It should be understood that the source and drain of the thin film transistor can be interchangeable. For example, the first source of the first thin film transistor can be electrically connected to the pixel electrode, and the second drain of the second thin film transistor can be electrically connected to the data line.

[0054] Electronic ink is controlled by two thin film transistors connected in series to achieve display. The two thin film transistors connected in series can reduce leakage current and improve display quality.

[0055] Continue to refer to Figures 1 to 6 The display substrate may include a plurality of film layers arranged on a base substrate 1, for example, the plurality of film layers include at least a first conductive layer 2, a gate insulating layer 3, an active layer 4, a second conductive layer 5, a passivation layer 6 and a pixel conductive layer 7.

[0056] The display substrate may include a storage capacitor Cst disposed on the base substrate 1 and located in each pixel P. The storage capacitor Cst may include a first capacitor electrode 10 and a second capacitor electrode 20 . The first capacitor electrode 10 and the second capacitor electrode 20 are disposed opposite to each other.

[0057] The first gate T1G of the first thin film transistor T1 , the second gate T2G of the second thin film transistor T2 , the gate line GL, the common electrode line CL, and the second capacitor electrode 20 may be located in the first conductive layer 2 .

[0058] The gate insulating layer 3 is located on a side of the first conductive layer 2 away from the base substrate 1 .

[0059] The active layer 4 is located on a side of the gate insulating layer 3 away from the substrate 1. The active layer 4 may include semiconductor materials, such as amorphous silicon, polycrystalline silicon, or metal oxide.

[0060] The second conductive layer 5 is located on a side of the active layer 4 away from the substrate 1 . The first source T1S and the first drain T1D of the first thin film transistor T1, the second source T2S and the second drain T2D of the second thin film transistor T2, the data line DL, and the first capacitor electrode 10 may be located in the second conductive layer 5 .

[0061] The passivation layer 6 is located on a side of the second conductive layer 5 away from the base substrate 1. The orthographic projection of the passivation layer 6 on the base substrate 1 covers the orthographic projection of the second conductive layer 5 on the base substrate 1. The passivation layer 6 is made of an insulating material.

[0062] The pixel conductive layer 7 is located on the side of the passivation layer 6 away from the base substrate 1. The display substrate may further include a pixel electrode 70, which is located in the pixel conductive layer 7. For example, the pixel conductive layer 7 may be made of a transparent conductive material such as ITO.

[0063] In this article, for the convenience of description, Figure 2 , among the data lines and gate lines surrounding any pixel P, for example, 2 data lines and 2 gate lines surround one pixel P, that is, among the 2 data lines and 2 gate lines surrounding any pixel P, one gate line electrically connected to the thin film transistor in the pixel P is the first gate line, one data line electrically connected to the thin film transistor in the pixel P is the first data line, another data line spaced apart from the first data line is the second data line, and another gate line spaced apart from the first gate line is the second gate line. Figure 2 In the illustrated embodiment, the gate line on the upper side is the first gate line, the gate line on the lower side is the second gate line, the data line on the right side is the first data line, and the data line on the left side is the second data line.

[0064] Combined with reference Figures 1 to 7 , the first capacitor electrode 10 may include an electrode body 101, a first protrusion 102, and a second protrusion 103. In any pixel, the electrode body 101 is located between adjacent first gate lines and second gate lines, and the electrode body 101 is located between adjacent first data lines and second data lines. The first protrusion 102 and the second protrusion 103 both protrude toward the first data line DL of the pixel relative to the electrode body 101, that is, the first protrusion 102 and the second protrusion 103 are located on the same side of the electrode body 101. For example, the orthographic projection of the electrode body 101 on the base substrate 1 may be rectangular or substantially rectangular in shape, and the first protrusion 102 and the second protrusion 103 are portions extending from the rectangular electrode body 101 toward the first data line DL. The electrode body 101, the first protrusion 102, and the second protrusion 103 are an integral structure, that is, they are a continuously extending integral structure.

[0065] The first drain electrode T1D of the first thin film transistor T1 may be electrically connected to the second protrusion 103. For example, the first drain electrode T1D of the first thin film transistor T1 and the second protrusion 103 are an integral structure, that is, they are a continuously extending integral structure. The second source electrode T2S of the second thin film transistor T2 is electrically connected to the data line DL. For example, the second source electrode T2S of the second thin film transistor T2 and the first data line DL are an integral structure, that is, they are a continuously extending integral structure.

[0066] The display substrate may further include at least one via hole 62 penetrating the passivation layer 6, each via hole 62 exposing a portion of the first capacitor electrode 10. A portion of the pixel conductive layer 7 may be filled in the via hole 62, so that the pixel electrode 70 may be electrically connected to the first capacitor electrode 10 through the at least one via hole 62. The first capacitor electrode 10 is electrically connected to the first drain electrode T1D of the first thin film transistor T1. In this way, the pixel conductive layer 70 is electrically connected to the first drain electrode T1D of the first thin film transistor T1. In this way, the signal (e.g., voltage) supplied by the data line DL may be transmitted to the pixel electrode under the control of the gate signal supplied by the gate line GL.

[0067] In the embodiment of the present disclosure, the first capacitor electrode 10 is supplied with a data signal (ie, Vdata).

[0068] Reference Figure 1 and Figure 2 , the second capacitor electrode 20 is electrically connected to the common electrode line CL, that is, the second capacitor electrode 20 is supplied with a common voltage (i.e., Vcom). The first capacitor electrode 10 and the second capacitor electrode 20 are opposite and spaced apart in the thickness direction of the base substrate 1, and a portion of the gate insulating layer 3 serving as an insulating layer is disposed between them. In this way, a storage capacitor Cst is formed.

[0069] In the embodiment of the present disclosure, the first capacitor electrode 10 is used as a capacitor plate of the storage capacitor Cst and also as a conductive connection portion between the thin film transistor and the pixel electrode. The second capacitor electrode 20 is used as another capacitor plate of the storage capacitor Cst and also as a common electrode.

[0070] Reference Figure 7 , the electronic ink layer 9 is arranged on the side of the pixel conductive layer 7 away from the base substrate 1, for example, the electronic ink layer 9 can be arranged on the opposite substrate 11. It should be understood that the opposite substrate 11 is also provided with an upper electrode. The electronic ink layer 9 may include a plurality of microcapsules, and the microcapsules include charged particles. By controlling the electric field between the pixel electrode and the upper electrode, the charged particles can be driven to move in the microcapsules. In this way, by adjusting the color of the charged particles in the microcapsules, the electronic ink can display patterns and colors.

[0071] Continue to refer to Figures 1 to 6 The display substrate may further include a tip structure 30 , wherein the tip structure 30 and the first capacitor electrode 10 are located in the same layer, that is, the tip structure 30 is located in the second conductive layer 5 .

[0072] For example, the tip structure 30 may include a first tip substructure 31 and a second tip substructure 32 .

[0073] In some embodiments of the present disclosure, the display substrate may include a plurality of the tip structures 30, and the plurality of tip structures 30 are arranged at intervals in the column direction Y. For example, a first tip substructure 31 and a second tip substructure 32 arranged opposite to each other may be referred to as a group of tip structures. The display substrate may include a plurality of groups of tip structures arranged at intervals along the column direction Y. For example, 1 to 10 groups of tip structures may be provided.

[0074] In each of the tip structures, the first tip of the first tip substructure and the second tip of the second tip substructure are arranged opposite to each other and spaced apart in the row direction.

[0075] In any pixel P, the first tip substructure 31 is connected to the end of the first protrusion 102 facing the first data line DL, and the second tip substructure 32 is connected to the side of the first data line DL facing the first protrusion 102. The end of the first tip substructure 31 facing the first data line DL is formed as a first tip 31P, and the end of the second tip substructure 32 facing the first protrusion 102 is formed as a second tip 32P. The first tip 31P and the second tip 32P are arranged opposite to each other and spaced apart in the row direction X.

[0076] For example, the first tip substructure 31, the first protrusion 102 and the electrode body 101 are an integral structure, that is, they are a continuously extending integral structure. The second tip substructure 32 and the first data line DL are an integral structure, that is, they are a continuously extending integral structure.

[0077] The inventors have discovered through research that when static charge is released onto an object, induced charge will be generated on the surface of the adjacent conductor. The induced charge is evenly distributed on the surface of the conductor. However, when the surface of the conductor has curvature (for example, it is uneven, has bends, sharp corners, etc.), the charge gathers at the location with a large radius of curvature, the charge density is higher, and the electric field formed with other objects is larger, making it easy for discharge to occur. This phenomenon is tip discharge, such as the discharge effect of a lightning rod. Moreover, as mentioned above, electronic paper display products in the industry will be shipped with a protective film coated after the array substrate process is completed. During the removal of the protective film, extremely high static electricity will be generated. For example, the static electricity at this time may be above 100 volts. The inventors have found that static electricity will enter the first conductive layer from the surface pixel conductive layer, and static electricity discharge usually occurs on the storage capacitor. For example, it usually occurs at the edge of the lower electrode of the storage capacitor located in the first conductive layer (that is, the electrode located in the first conductive layer). Due to the presence of a slope angle at the edge of the lower electrode, the curvature changes greatly, and the charge is more densely distributed at this position. In addition, when a gate insulating layer is formed at this location, the gate insulating layer here is less dense than other areas due to the slope angle, so it is more prone to electrostatic breakdown, causing the second conductive layer and the first conductive layer to be conductive at this location, causing poor display.

[0078] In the embodiment of the present disclosure, by designing a tip structure in the layer where the upper electrode of the storage capacitor is located, static electricity can be induced to be released from the tip structure, avoiding static electricity from breaking through the gate insulating layer and damaging the lower electrode of the storage capacitor, thereby avoiding affecting the normal display of the pixel. Moreover, when static electricity is released from the tip structure, it can be released to the data line through the first tip substructure and the second tip substructure. Since the data line extends a long distance in the column direction and its resistance is relatively large, the static electricity can be evenly diverted to other locations through the data line to reduce the damage caused by static electricity. . In the display substrate provided in the embodiment of the present disclosure, by designing the tip structure, the static electricity can be effectively released to avoid static electricity from damaging the pixel. In addition, the tip structure in the display substrate provided in the embodiment of the present disclosure can also achieve the purpose of static electricity prevention in the process of the array substrate.

[0079] For example, the orthographic projection of the pixel electrode 70 on the base substrate 1 may cover the orthographic projection of the second capacitor electrode 20 on the base substrate 1. The orthographic projection of the pixel electrode 70 on the base substrate 1 may cover the orthographic projection of the first protrusion 102 on the base substrate. The orthographic projection of the pixel electrode 70 on the base substrate 1 may cover the orthographic projection of the first tip substructure 31 on the base substrate 1. The orthographic projection of the pixel electrode 70 on the base substrate 1 may at least partially overlap with the orthographic projection of the second tip substructure 32 on the base substrate 1.

[0080] The orthographic projection of the pixel electrode 70 on the base substrate 1 may be spaced apart from the orthographic projection of the thin film transistor on the base substrate 1, that is, it does not overlap with the orthographic projection of the thin film transistor on the base substrate 1. Optionally, the orthographic projection of the pixel electrode 70 on the base substrate 1 may at least partially overlap with the orthographic projection of the thin film transistor on the base substrate 1.

[0081] Reference Figure 1 and Figure 2 The first tip substructure 31 has a first side surface 311 (i.e., the upper side surface in the figure) close to the thin film transistor and a second side surface 312 (i.e., the lower side surface in the figure) away from the thin film transistor. The first side surface 311 and the second side surface 312 are both inclined relative to the row direction X. The first side surface 311 of the first tip substructure and the second side surface 312 of the first tip substructure converge toward the first data line DL and intersect at the first tip 31P. For example, the angle between the first side surface 311 and the second side surface 312 at the first tip 31P can be less than 90°, for example, can be in the range of 15° to 75°.

[0082] The second tip substructure 32 has a first side surface 321 (i.e., the upper side surface in the figure) close to the thin film transistor and a second side surface 322 (i.e., the lower side surface in the figure) away from the thin film transistor. The first side surface 321 and the second side surface 322 are both inclined relative to the row direction X. The first side surface 321 of the second tip substructure and the second side surface 322 of the second tip substructure converge toward the first protrusion 102 and intersect at the second tip 32P. For example, the angle between the first side surface 321 and the second side surface 322 at the second tip 32P can be less than 90°, for example, can be in the range of 15° to 75°.

[0083] The first tip 31P and the second tip 32P are disposed opposite to each other in the row direction X, and are spaced apart by a predetermined interval in the row direction X. For example, the predetermined interval may be between 1 and 10 micrometers, or between 2 and 3 micrometers.

[0084] Reference Figure 6 At least a portion of the passivation layer 6 is located in the gap between the first tip 31P and the second tip 32P. That is, the passivation layer 6 fills the gap between the first tip 31P and the second tip 32P.

[0085] In some embodiments, the dielectric constant of the gate insulating layer 3 is greater than the dielectric constant of the passivation layer 6. For example, the dielectric constant of the gate insulating layer 3 is about 7.5, and the dielectric constant of the passivation layer 6 is about 6.5-5.5. The insulating property of the passivation layer 6 is worse than the insulating property of the gate insulating layer 3. In this way, the breakdown voltage of the passivation layer 6 is lower than the breakdown voltage of the gate insulating layer 3. In the process of static electricity discharge, static electricity is more likely to break through the passivation layer, that is, static electricity is more likely to be released by breaking through the passivation layer between the two tip sub-structures.

[0086] Continue to refer to Figure 2 , the first tip substructure 31 may include a first tip main body 313, the first tip main body 313 is located between the first tip 31P and the first protrusion 102, the first tip main body 313 has a first side surface 314 close to the thin film transistor and a second side surface 315 away from the thin film transistor, and the first side surface 314 of the first tip main body is parallel to the second side surface 315 of the first tip main body. For example, the orthographic projection of the first tip main body 313 on the substrate 1 may be rectangular or substantially rectangular. The orthographic projection of the portion including the first side surface 311, the second side surface 312 and the first tip 31P on the substrate 1 may be triangular.

[0087] The second tip substructure 32 may include a second tip body portion 323, the second tip body portion 323 is located between the second tip 32P and the first data line DL, the second tip body portion 323 has a first side surface 324 close to the thin film transistor and a second side surface 325 away from the thin film transistor, and the first side surface 324 of the second tip body portion and the second side surface 325 of the second tip body portion are parallel. For example, the orthographic projection of the second tip body portion 323 on the base substrate 1 may be in a rectangular or substantially rectangular shape. The orthographic projection of the portion including the first side surface 321, the second side surface 322 and the second tip 32P on the base substrate 1 may be in a triangular shape.

[0088] For example, the width of the first tip body portion 313 may be between 3 and 10 microns, that is, the distance between the first side surface 314 and the second side surface 315 of the first tip body portion 313 along the column direction Y is between 3 and 10 microns, for example, approximately between 4 and 7 microns. The width of the second tip body portion 323 may be between 3 and 10 microns, that is, the distance between the first side surface 324 and the second side surface 325 of the second tip body portion 323 along the column direction Y is between 3 and 10 microns, for example, approximately between 4 and 7 microns.

[0089] Reference Figures 1 to 6, the orthographic projection of the capacitor body 101 of the first capacitor electrode on the substrate 1 falls within the orthographic projection of the second capacitor electrode 20 on the substrate 1. For example, the orthographic projection of the capacitor body 101 of the first capacitor electrode on the substrate 1 may be rectangular or substantially rectangular, and the orthographic projection of the second capacitor electrode 20 on the substrate 1 may be rectangular or substantially rectangular. The area of ​​the orthographic projection of the capacitor body 101 of the first capacitor electrode on the substrate 1 is smaller than the area of ​​the orthographic projection of the second capacitor electrode 20 on the substrate 1.

[0090] In some embodiments, reference Figure 2 , on the three sides where the first gate line (corresponding to the upper side), the second gate line (corresponding to the lower side) and the second data line (corresponding to the left side) are located, the orthographic projection of the second capacitor electrode 20 on the substrate substrate 1 exceeds the orthographic projection of the first capacitor electrode 10 on the substrate substrate 1. On the side where the first data line is located (corresponding to the right side), except for the first protrusion 102 and the second protrusion 103, the orthographic projection of the second capacitor electrode 20 on the substrate substrate 1 exceeds the orthographic projection of the first capacitor electrode 10 on the substrate substrate 1. That is, in the embodiment of the present disclosure, the orthographic projection of the electrode body 101 of the first capacitor electrode 10 on the substrate substrate is rectangular or substantially rectangular, the orthographic projection of the second capacitor electrode 20 on the substrate substrate is rectangular or substantially rectangular, and the orthographic projection of the second capacitor electrode 20 on the substrate substrate covers the orthographic projection of the electrode body 101 of the first capacitor electrode 10 on the substrate substrate.

[0091] In the embodiment of the present disclosure, the lower electrode located at the gate conductive layer (i.e., the second capacitor electrode 20) is designed to have a larger area than the upper electrode located at the source and drain conductive layer (i.e., the electrode body of the first capacitor electrode). Figure 4 , the edge of the second capacitor electrode 20 of the storage capacitor Cst is parallel to the plane where the substrate 1 is located, and exceeds the edge of the first capacitor electrode 10. Therefore, at the edge of the storage capacitor Cst, that is, at the edge of the portion where the second capacitor electrode 20 overlaps with the first capacitor electrode 10, no sharp corner is formed, and in this area, the surface of the second capacitor electrode 20 facing the first capacitor electrode 10 is flat and does not have a slope angle. Therefore, a gate insulating layer with good density can be formed in this area. In this way, the gate insulating layer has good density corresponding to the portion of the storage capacitor Cst and has strong antistatic ability, which greatly reduces the probability of static electricity breaking through the gate insulating layer here.

[0092] In some embodiments, the second capacitor electrode 20 has a first side surface 201 facing the first gate line GL, the electrode body 101 has a first side surface 1011 facing the first gate line GL, and the first side surface 201 of the second capacitor electrode is closer to the first gate line GL than the first side surface 1011 of the electrode body. For example, the distance along the column direction Y between the orthographic projection of the first side surface 201 of the second capacitor electrode on the base substrate 1 and the orthographic projection of the first side surface 1011 of the electrode body on the base substrate 1 is greater than a predetermined distance.

[0093] The second capacitor electrode 20 has a second side surface 202 facing the second gate line GL, the electrode body 101 has a second side surface 1012 facing the second gate line GL, and the second side surface 202 of the second capacitor electrode is closer to the second gate line GL than the second side surface 1012 of the electrode body. For example, the distance along the column direction Y between the orthographic projection of the second side surface 202 of the second capacitor electrode on the base substrate 1 and the orthographic projection of the second side surface 1012 of the electrode body on the base substrate 1 is greater than a predetermined distance.

[0094] The second capacitor electrode 20 has a third side surface 203 facing the second data line DL, the electrode body 101 has a third side surface 1013 facing the second data line DL, and the third side surface 203 of the second capacitor electrode is closer to the second data line DL than the third side surface 1013 of the electrode body. For example, the distance along the row direction X between the orthographic projection of the third side surface 203 of the second capacitor electrode on the base substrate 1 and the orthographic projection of the third side surface 1013 of the electrode body on the base substrate 1 is greater than a predetermined distance.

[0095] The second capacitor electrode 20 has a fourth side surface 204 facing the first data line DL, the electrode body 101 has a fourth side surface 1014 facing the first data line DL, and the fourth side surface 204 of the second capacitor electrode is closer to the first data line DL than the fourth side surface 1014 of the electrode body. For example, the distance along the row direction X between the orthographic projection of the fourth side surface 204 of the second capacitor electrode on the base substrate 1 and the orthographic projection of the fourth side surface 1014 of the electrode body on the base substrate 1 is greater than a predetermined distance.

[0096] It should be noted that, in the process of forming the first capacitor electrode and the second capacitor electrode using the exposure device, there is an alignment error between the first capacitor electrode and the second capacitor electrode, and the alignment error depends on the alignment accuracy of the exposure device, for example. Moreover, in the process of forming the first capacitor electrode and the second capacitor electrode using the exposure device, there may be a certain slope angle at the edge of the second capacitor electrode, that is, its edge is not a completely vertical side surface, but an inclined surface with a certain slope. For example, in some specific examples, the alignment error between the first capacitor electrode and the second capacitor electrode is within 2.5 microns, and the slope angle area length at the edge of the second capacitor electrode is within 0.5 microns. In this way, the above-mentioned "predetermined distance" can be set to 3 microns. In this case, considering the factors of processing equipment and process, it can be ensured that the positive projection of the second capacitor electrode 20 on the substrate substrate covers the positive projection of the electrode body 101 of the first capacitor electrode 10 on the substrate substrate.

[0097] In some embodiments, the at least one via hole 62 is disposed adjacent to the tip structure 30. For example, the orthographic projection of the at least one via hole 62 on the base substrate 1 falls within the orthographic projection of the first protrusion 102 on the base substrate 1. In this way, the via hole 62 is disposed adjacent to the first tip substructure 31 of the tip structure 30.

[0098] In the embodiment of the present disclosure, static electricity can be released along the path of the pixel electrode, the via hole, the first protrusion, and the tip structure, that is, along the Figure 2 The via 62 is disposed adjacent to the tip structure 30, which can shorten the length of the static electricity release path, thereby making it easier for static electricity to be released through the path.

[0099] For example, the display substrate may include more than two via holes 62. By providing more than two via holes 62, the contact area between the pixel electrode and the first capacitor electrode can be increased, thereby reducing the contact resistance between the pixel electrode and the first capacitor electrode.

[0100] For example, two or more vias 62 are arranged at intervals along the column direction Y. Figure 2 As shown, the orthographic projection of the first protrusion 102 on the base substrate 1 is rectangular, and the size of the rectangle along the column direction Y is larger than the size along the row direction X. In this case, the plurality of vias 62 are arranged at intervals along the Y direction, which is conducive to having enough space to arrange the plurality of vias 62 .

[0101] Some exemplary embodiments of the present disclosure also provide a display device. Figure 7, the display device may include the above-mentioned display substrate. The display device may also include an electronic ink layer 9, which may be arranged on a side of the pixel conductive layer 7 away from the base substrate 1. For example, the electronic ink layer 9 may be arranged on the opposite substrate 11. For example, the electronic ink layer 9 and the opposite substrate 11 may adopt a paper film structure known in the art, which will not be described in detail here.

[0102] It should be understood that the display device according to some exemplary embodiments of the present disclosure has all the features and advantages of the above-mentioned display substrate, and these features and advantages can be referred to the above description of the display substrate, which will not be repeated here.

[0103] As used herein, the terms "substantially," "approximately," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "approximately" or "approximately" as used herein include the stated value and mean that the particular value is within an acceptable range of deviation as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0104] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, comprising: substrate substrate; A plurality of gate lines and a plurality of data lines are arranged on the base substrate, each of the gate lines extends in a row direction, each of the data lines extends in a column direction, and the plurality of gate lines and the plurality of data lines are arranged to cross each other to surround and form a plurality of pixels; At least one thin film transistor disposed on the substrate and located in each pixel, each thin film transistor comprising a gate, a first electrode and a second electrode, the first electrode being one of a source electrode and a drain electrode, and the second electrode being the other of the source electrode and the drain electrode; A storage capacitor disposed on the substrate and located in each pixel, the storage capacitor comprising a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the second capacitor electrode are disposed opposite to each other, the first capacitor electrode and the second electrode are located in the same layer, and the first capacitor electrode at least comprises an electrode body; as well as a tip structure, the tip structure and the first capacitor electrode are located in the same layer, the tip structure includes a first tip substructure and a second tip substructure, Among the data lines and gate lines surrounding any pixel, a data line electrically connected to the thin film transistor in the pixel is a first data line; In any pixel, the first tip substructure is connected to the side of the electrode body facing the first data line, the second tip substructure is connected to the side of the first data line facing the electrode body, the end of the first tip substructure facing the first data line is formed as a first tip, and the end of the second tip substructure facing the electrode body is formed as a second tip, and the first tip and the second tip are arranged opposite to each other and spaced apart in the row direction.

2. The display substrate according to claim 1, wherein: The first capacitor electrode further includes a first protrusion, the first protrusion being located between the electrode body and the first tip substructure; and The first protrusion protrudes relative to the electrode body toward a first data line of the pixel, and the first tip substructure is connected to an end of the first protrusion facing the first data line.

3. The display substrate according to claim 1 or 2, wherein: The orthographic projection of the capacitor body of the first capacitor electrode on the base substrate falls within the orthographic projection of the second capacitor electrode on the base substrate.

4. The display substrate according to claim 1 or 2, wherein: The first tip substructure has a first side surface close to the thin film transistor and a second side surface away from the thin film transistor, the first side surface of the first tip substructure and the second side surface of the first tip substructure converge toward the first data line and intersect at the first tip; and / or, The second tip substructure has a first side surface close to the thin film transistor and a second side surface away from the thin film transistor, the first side surface of the second tip substructure and the second side surface of the second tip substructure converge toward the electrode body and intersect at the second tip.

5. The display substrate according to claim 1 or 2, wherein: The distance between the first tip and the second tip along the row direction is between 1 and 10 micrometers.

6. The display substrate according to claim 2, wherein: The first tip substructure comprises a first tip main body portion, the first tip main body portion is located between the first tip and the first protrusion, the first tip main body portion has a first side surface close to the thin film transistor and a second side surface away from the thin film transistor, and the first side surface of the first tip main body portion is parallel to the second side surface of the first tip main body portion; and / or, The second tip substructure includes a second tip main body portion, which is located between the second tip and the first data line, and the second tip main body portion has a first side surface close to the thin film transistor and a second side surface away from the thin film transistor, and the first side surface of the second tip main body portion is parallel to the second side surface of the second tip main body portion.

7. The display substrate according to claim 6, wherein: The distance between the first side surface of the first tip body portion and the second side surface of the first tip body portion along the column direction is between 3 and 10 micrometers; and / or, A distance between the first side surface of the second tip body portion and the second side surface of the second tip body portion along the column direction is between 3 and 10 micrometers.

8. The display substrate according to claim 3, wherein: Among the data lines and gate lines surrounding any pixel, a gate line electrically connected to the thin film transistor in the pixel is a first gate line, another data line spaced apart from the first data line is a second data line, and another gate line spaced apart from the first gate line is a second gate line; and The second capacitor electrode has a first side facing the first gate line, the electrode body has a first side facing the first gate line, and the first side of the second capacitor electrode is closer to the first gate line than the first side of the electrode body; And / or, the second capacitor electrode has a second side facing the second gate line, the electrode body has a second side facing the second gate line, and the second side of the second capacitor electrode is closer to the second gate line than the second side of the electrode body; and / or, the second capacitor electrode has a third side facing the second data line, the electrode body has a third side facing the second data line, and the third side of the second capacitor electrode is closer to the second data line than the third side of the electrode body; and / or, the second capacitor electrode has a fourth side facing the first data line, the electrode body has a fourth side facing the first data line, and the fourth side of the second capacitor electrode is closer to the first data line than the fourth side of the electrode body.

9. The display substrate according to claim 8, wherein: The distance between the orthographic projection of the first side surface of the second capacitor electrode on the substrate and the orthographic projection of the first side surface of the electrode body on the substrate along the column direction is greater than 3 micrometers; and / or, The distance between the orthographic projection of the second side surface of the second capacitor electrode on the substrate and the orthographic projection of the second side surface of the electrode body on the substrate along the column direction is greater than 3 micrometers; and / or, The distance between the orthographic projection of the third side surface of the second capacitor electrode on the substrate and the orthographic projection of the third side surface of the electrode body on the substrate along the row direction is greater than 3 micrometers; and / or, A distance along the row direction between an orthographic projection of the fourth side surface of the second capacitor electrode on the substrate and an orthographic projection of the fourth side surface of the electrode body on the substrate is greater than 3 micrometers.

10. The display substrate according to claim 2, wherein: The display substrate further includes a pixel electrode disposed on the base substrate and located in each pixel. The pixel electrode is electrically connected to the first capacitor electrode through at least one via hole, and the orthographic projection of the at least one via hole on the base substrate falls within the orthographic projection of the first protrusion on the base substrate.

11. The display substrate according to claim 1 or 2, wherein: The display substrate comprises a plurality of the tip structures, and the plurality of tip structures are arranged at intervals in the column direction; as well as In each of the tip structures, the first tip of the first tip substructure and the second tip of the second tip substructure are arranged opposite to each other and spaced apart in the row direction.

12. The display substrate according to claim 10, wherein: The display substrate further comprises a passivation layer, wherein the passivation layer is located between the layer where the pixel electrode is located and the layer where the first capacitor electrode is located; as well as At least a portion of the passivation layer is located in a gap between the first tip and the second tip.

13. The display substrate according to claim 12, wherein: The display substrate further includes a gate insulating layer, wherein the gate insulating layer is located between a layer where the second capacitor electrode is located and a layer where the first capacitor electrode is located; and The dielectric constant of the gate insulating layer is greater than the dielectric constant of the passivation layer.

14. The display substrate according to claim 2, wherein: The at least one thin film transistor includes a first thin film transistor and a second thin film transistor; The first capacitor electrode comprises a second protrusion, the second protrusion and the first protrusion are located on the same side of the electrode body, the second protrusion is electrically connected to the first electrode of the first thin film transistor, the second electrode of the first thin film transistor is electrically connected to the first electrode of the second thin film transistor, and the second electrode of the second thin film transistor is electrically connected to the first data line; and The display substrate further includes a common electrode line extending along the row direction and electrically connected to the second capacitor electrode.

15. The display substrate according to claim 1, wherein: The second capacitor electrode and the gate are located in the same layer.

16. A display device, wherein: The display device includes the display substrate according to any one of claims 1 to 15.

Images