Method for managing multiple NVMe hard disks and server

Abstract

The application is suitable for the technical field of hard disk management, and provides a management method for multiple NVMe hard disks and a server. The method comprises the following steps: a programmable logic device acquires a first preset address; when the first preset address is the address of a controller, the programmable logic device sends a first feedback signal to a management control device; the programmable logic device acquires a target preset value; according to the target preset value, the programmable logic device selects the I 2 C channel between the programmable logic device and the target NVMe hard disk; the programmable logic device sends a second feedback signal to the management control device, so that the management control device controls the target NVMe hard disk to perform a data read-write operation through the I 2 C channel between the programmable logic device and the target NVMe hard disk after acquiring the second feedback signal. Thus, the management of multiple NVMe hard disks can be realized.

Description

Technical Field

[0001] This application belongs to the field of hard disk management technology, and in particular relates to a management method and server for multiple non-volatile memory express (NVMe) hard disks. Background Technology

[0002] In a server, multiple NVMe hard drives act as slave devices, connected via the same inter-integrated circuit (I2C) bus. 2 C) It connects to the baseboard management controller (BMC), enabling the BMC to manage multiple NVMe hard drives simultaneously. Due to the I / O capabilities of NVMe hard drives... 2 The address of the C interface is fixed, therefore the I / O addresses of multiple NVMe hard drives are... 2 Address conflicts can occur with the C interface. This causes conflicts when the baseboard management controller accesses multiple NVMe hard drives.

[0003] Currently, the baseboard management controller includes multiple I... 2 C interface, each I 2 Connect an NVMe hard drive to the C interface. Alternatively, configure the I / O port on the server's hard drive backplane. 2 C expansion chip, I 2 The C expansion chip can connect to the baseboard management controller via I... 2 The C bus is expanded to multiple I... 2 C interface. Each I 2 The C interface connects to an NVMe hard drive, allowing the baseboard management controller to manage multiple NVMe hard drives.

[0004] However, when there are a large number of NVMe hard drives, the I / O provided by the baseboard management controller is limited. 2 The limited number of Type-C interfaces prevents the baseboard management controller from managing multiple NVMe drives. Alternatively, I... 2 Multiple C expansion chips need to be placed on the hard drive backplane, which leads to complex wiring and increased device costs. Summary of the Invention

[0005] This application provides a management method and server for multiple NVMe hard drives, which can solve the problem of insufficient I / O capacity provided by the baseboard management controller when the number of NVMe hard drives is large. 2 The limited number of C interfaces prevents the baseboard management controller from managing multiple NVMe hard drives.

[0006] In a first aspect, embodiments of this application provide a method for managing multiple NVMe hard drives, the method comprising: a programmable logic device via I... 2 The C bus obtains the first preset address from the management controller;

[0007] When the first preset address is the address of the controller, the programmable logic device (PLC) uses I... 2 The C bus sends the first feedback signal to the management controller;

[0008] Programmable logic devices via I 2 The C bus obtains the target preset value from the management controller. The target preset value is sent by the management controller to the I bus after obtaining the first feedback signal. 2 Transmitted via C bus;

[0009] The programmable logic device selects the I / O gate between the programmable logic device and the target NVMe hard drive according to the target preset value. 2 C-channel, the target NVMe hard drive is any one of multiple NVMe hard drives that needs to be accessed;

[0010] Programmable logic devices via I 2 The C bus sends a second feedback signal to the management controller, so that after receiving the second feedback signal, the management controller, through the I / O communication between the programmable logic device and the target NVMe hard drive... 2 The C channel controls the target NVMe hard drive to perform data read and write operations.

[0011] In one possible implementation of the first aspect, the method specifically includes:

[0012] The controller in a programmable logic device communicates with I 2 The C bus obtains the first preset address from the management controller;

[0013] When the first preset address is the controller's address, the controller uses I... 2 The C bus sends the first feedback signal to the management controller;

[0014] The controller uses I 2 The C-bus obtains the target preset value from the management controller;

[0015] The controller transmits the target preset value to the registers in the programmable logic device;

[0016] The register selects the I / O gate between the programmable logic device and the target NVMe hard drive based on the target preset value. 2 Channel C;

[0017] The register notifies the controller to select the I / O between the programmable logic device and the target NVMe hard drive.2 Channel C;

[0018] The controller uses I 2 The C bus sends a second feedback signal to the management controller.

[0019] In one possible implementation of the first aspect, the method further includes:

[0020] Programmable logic devices obtain the first control signal from a central processing unit or multiple NVMe hard drives;

[0021] The programmable logic device performs hot-swapping and LED control on each NVMe hard drive according to the first control signal.

[0022] This application embodiment utilizes the programming function of a programmable logic device to realize the programming of the I / O pins of the programmable logic device. 2 The C interface is expanded to include multiple I... 2 The C-channel, because the programmable logic device and the management control device communicate via I... 2 The C-bus connection can be viewed as a way to manage and control the I-channels of the device. 2 The C interface is expanded to include multiple I... 2 C channel, each I 2 This technology connects a C-channel drive to one of multiple NVMe drives, solving the problem that management controllers cannot manage multiple NVMe drives, and thus saving I / O resources on the management controller. 2 The C interface offers advantages such as simpler resources, easier wiring, and lower cost.

[0023] Secondly, embodiments of this application provide a programmable logic device for executing the management method of multiple NVMe hard drives in the first aspect or any possible implementation of the first aspect.

[0024] In one possible implementation of the second aspect, the programmable logic device includes: a controller and registers;

[0025] Among them, the management control device and the controller are connected through the I 2 The C-bus is connected, and the controller is connected to the register. The register controls the connection between the programmable logic device and each of the multiple NVMe hard drives to form an I-channel. 2 Channel C.

[0026] Thirdly, embodiments of this application provide a server, including: a management and control device disposed on a motherboard, and a plurality of NVMe hard drives disposed on a backplane, and a programmable logic device in the second aspect or any possible implementation of the second aspect;

[0027] Among them, the management and control device and the programmable logic device are connected through I 2 The C-bus connection connects the programmable logic device to each of the multiple NVMe hard drives, forming an I-channel network. 2 Channel C;

[0028] The management controller, after acquiring the second feedback signal, uses a programmable logic device to communicate with the target NVMe hard drive via I / O. 2 The C channel controls the target NVMe hard drive to perform data read and write operations.

[0029] In one possible implementation of the third aspect, a management controller is specifically used to send a second preset address to the target NVMe hard drive;

[0030] The target NVMe hard drive is used to send a third feedback signal to the management controller when the second preset address is the address of the target NVMe hard drive after receiving the second preset address.

[0031] The management controller is also used to send a second control signal to the target NVMe hard drive after receiving the third feedback signal;

[0032] The target NVMe hard drive is also used to perform data read and write operations according to the second control signal after receiving the second control signal.

[0033] In one possible implementation of the third aspect, the server also includes: a central processing unit located on the motherboard;

[0034] The central processing unit is used to send the first control signal to the programmable logic device;

[0035] The programmable logic device is also used to perform hot-swapping and LED control on each of the multiple NVMe hard drives according to the first control signal after the first control signal is acquired.

[0036] Fourthly, embodiments of this application provide a management device including a memory and a processor. The memory stores instructions; the processor executes the instructions stored in the memory, causing the device to perform a management method for multiple NVMe hard drives as described in the first aspect or any possible implementation thereof.

[0037] Fifthly, embodiments of this application provide a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform a management method for multiple NVMe hard drives as described in the first aspect or any possible implementation thereof.

[0038] In a sixth aspect, embodiments of this application provide a computer program product containing instructions that, when executed on a device, cause the device to perform a management method for multiple NVMe hard drives in the first aspect or any possible implementation thereof.

[0039] It is understood that the beneficial effects of the second to sixth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic block diagram of a server structure provided in an embodiment of this application;

[0042] Figure 2 This is a schematic block diagram of a server structure provided in an embodiment of this application;

[0043] Figure 3 This is a schematic diagram illustrating the principle of the slave device address provided in an embodiment of this application;

[0044] Figure 4a This is a schematic diagram illustrating a write operation of a programmable logic device in a server to perform a target preset value, provided in an embodiment of this application.

[0045] Figure 4b This is a schematic diagram illustrating a read operation of a programmable logic device in a server executing a target preset value, provided in an embodiment of this application.

[0046] Figure 5 This is a signaling interaction diagram of a method for managing multiple NVMe hard drives provided in an embodiment of this application;

[0047] Figure 6 This is a signaling interaction diagram of a method for managing multiple NVMe hard drives provided in an embodiment of this application;

[0048] Figure 7 This is a schematic block diagram of a server structure provided in an embodiment of this application;

[0049] Figure 8 This is a schematic block diagram of a server structure provided in an embodiment of this application;

[0050] Explanation of reference numerals in the attached figures:

[0051] 100 - Server; 101 - Motherboard; 102 - Management and control devices; 103 - Backplane; 104 - Programmable logic devices; 105 - NVMe hard drives; 105a - Target NVMe hard drives; 106 - Controller; 107 - Registers; 108 - Central processing unit; 109 - Management module; 110 - Other slave devices. Detailed Implementation

[0052] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0053] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0054] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0055] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0056] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0057] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0058] Please see Figure 1 , Figure 1 A schematic block diagram of a server structure provided in an embodiment of this application is shown. Figure 1 As shown, the server 100 of this application may include: a management and control device 102 disposed on a motherboard 101, a programmable logic device 104 (PLD) and multiple NVMe hard disks 105 disposed on a backplane 103.

[0059] The motherboard 101 is used to control and manage the hardware devices in the server 100. These hardware devices may include: memory, hard disk, power supply, etc.

[0060] The backplane 103 is used to ensure normal communication between the motherboard 101 and hardware devices. The backplane 103 may include memory boards, hard drive backplanes, power supply backplanes, etc.

[0061] The motherboard 101 is connected to hardware devices via the backplane 103. For example, the motherboard 101 can be connected to the NVMe hard drive 105 via the hard drive backplane, so that the user can directly replace the damaged NVMe hard drive 105 without shutting down the server 100.

[0062] The NVMe SSD 105 is a hard drive that uses the NVMe protocol specification. The NVMe SSD 105 implements the interface protocol through the PCIe bus, which adopts the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe).

[0063] The NVMe protocol specification, or Non-volatile Memory Host Controller Interface Specification, is a logical device interface specification. Similar to the Serial ATA Advanced Host Controller Interface (AHCI), the NVMe protocol is a bus transmission protocol specification based on a logical device interface. Using the NVMe protocol specification, non-volatile memory media attached via the PCIe bus can be accessed.

[0064] The management controller 102 can act as a host device to access multiple NVMe hard drives 105, such as reading data from the multiple NVMe hard drives 105, writing data to the multiple NVMe hard drives 105, and controlling the multiple NVMe hard drives 105 to erase data. The management controller 102 may include a baseboard management controller, etc.

[0065] Multiple NVMe hard drives 105 are used for storing data. These multiple NVMe hard drives 105 may include: NVMe hard drive 1, NVMe hard drive 2, ..., NVMe hard drive M. Where M is an integer greater than or equal to 1.

[0066] Programmable logic device 104 is used to implement out-of-band management of multiple NVMe hard drives 105 through programming. Programmable logic device 104 may include complex programmable logical device (CPLD), field-programmable gate array (FPGA), and generic array logic (GAL), etc.

[0067] Since the programmable logic device 104 has abundant programmable I / O and programmable logic resources, it can also be programmed to implement other logic functions besides out-of-band management of multiple NVMe hard drives 105, such as hot-swap management.

[0068] Among them, the management and control device 102 and the programmable logic device 104 are connected via I / O. 2 C bus connection. I 2 The C bus is used to enable bidirectional communication between the management controller 102 and the programmable logic device 104.

[0069] I 2 The C bus is a bidirectional binary synchronous serial bus. 2The C-bus can connect one master device and one slave device, one master device and multiple slave devices, or multiple masters and multiple slave devices. The master device can access the corresponding slave device via the address specified in the instruction. The master and slave devices communicate via I / O. 2 The C bus can be used for data transmission.

[0070] I of the management controller 102 2 C interface and I 2 C bus connection, I 2 The C bus also connects to the I / O pins of the programmable logic device 104. 2 C interface connection.

[0071] Among them, the I of the programmable logic device 104 2 The C interface connects to the I / O pins of each of the multiple NVMe hard drives 105. 2 The C interfaces are connected to form an I... 2 Channel C.

[0072] NVMe SSD 105 2 The C interface, i.e., the out-of-band signal of the NVMe hard drive 105, is accessed through the I / O pins of the NVMe hard drive 105. 2 The C interface enables the management controller 102 to perform operations such as accessing the NVMe hard drive 105, configuring the parameters of the NVMe hard drive 105, monitoring the NVMe hard drive 105, and upgrading the NVMe hard drive 105.

[0073] Programmable logic device 104 and I 2 C bus connected to I 2 I connects the C interface to the programmable logic device 104 and multiple NVMe hard drives 105. 2 The C interface is connected.

[0074] The programmable logic device 104 can be programmed to control its I / O pins. 2 C interface, extended to multiple I 2 C channel, each I 2 The C channel can be used with a 105 I / O port on an NVMe hard drive. 2 C interface connection.

[0075] Multiple I 2 Channel C includes: I 2 Channel C 1, I 2 Channel C2, ..., I 2 C channels N. Where N is an integer greater than or equal to 1. Usually, M ≤ N.

[0076] For example, Figure 1 middle, I 2C-channel 1 connects to NVMe hard drive 1. 2 C interface, I 2 C-channel 2 connects to NVMe hard drive 2. 2 C interface, ..., I 2 C-channel M connects to NVMe hard drive M. 2 C interface.

[0077] Considering multiple I 2 The C channels all use the I / O of the programmable logic device 104. 2 The C interface enables the programmable logic device 104 to connect to multiple NVMe hard drives 105. If multiple I / O ports are selected simultaneously... 2 C channel, then the programmable logic device 104 will use the I channel of the programmable logic device 104. 2 The C interface communicates with multiple NVMe hard drives 105 simultaneously, causing address conflicts among the multiple NVMe hard drives 105. The address of the NVMe hard drive 105 is its I / O address. 2 The address of the C interface. Typically, the address of an NVMe hard drive (105) is set by the manufacturer.

[0078] Therefore, the programmable logic device 104 and the multiple NVMe hard drives 105 can only select one I at a time. 2 C channel. Where, I 2 The C channel has two states: strobed and unstrobed.

[0079] Before the management controller 102 accesses any one of the multiple NVMe hard drives 105, the programmable logic device 104 can allocate multiple I / O disks. 2 All C channels are set to an unselected state. When the management controller 102 accesses any one of the multiple NVMe hard drives 105, the programmable logic device 104 can select the I channel connected to that NVMe hard drive 105. 2 Channel C.

[0080] Alternatively, before the management controller 102 accesses any one of the multiple NVMe hard drives 105, the programmable logic device 104 can randomly select multiple I / O drives. 2 Any I in channel C 2 C-channel. When the management controller 102 accesses any one of the multiple NVMe hard drives 105, the programmable logic device 104 can selectively activate the I-channel connected to that NVMe hard drive 105. 2 Channel C.

[0081] Based on the above description, in the server of this application embodiment, the management control device does not need to provide multiple I / O pins. 2 The C interface is connected to the I / O ports of multiple NVMe hard drives. 2 The C interface connection saves on I / O ports for management and control devices. 2 The C interface resources enable out-of-band signal management for multiple NVMe drives. No additional I / O ports are needed on the backplane. 2 C expansion chip (I) 2 C expander) will not take up backplane wiring space, wiring is simple and the cost is low.

[0082] I 2 C expansion chip, used to integrate a main I 2 The C bus is expanded to include multiple slave I... 2 C bus, and can manage multiple extended slave I buses via instructions. 2 C bus and main I 2 Connection relationship of C bus.

[0083] Although the management controller 102 can be accessed via I 2 The bus switching function of the C expansion chip enables access to multiple NVMe hard drives 105. However, the number of NVMe hard drives 105 that the management controller 102 can manage is limited. If the number of NVMe hard drives 105 is to be increased, multiple I / O pins need to be added to the backplane 103. 2 The C expansion chip will seriously occupy the wiring space of the backplane 103, the wiring is complicated, and the chip material cost and material management cost are both high.

[0084] Below, in conjunction with Figure 2 Here is an example illustrating one implementation of the programmable logic device 104 in server 100.

[0085] Please see Figure 2 , Figure 2 A schematic block diagram of a server structure provided in an embodiment of this application is shown. Figure 2 As shown, the programmable logic device 104 of this application may include a controller 106 and a register 107.

[0086] Controller 106 is used to pre-store its own address via programming. Controller 106 is also used to receive a first preset address from management controller 102. The first preset address is the address of controller 106 that management controller 102 needs to communicate with.

[0087] The controller 106 is also used to determine whether the first preset address is the same as the stored address of the controller 106, so that the management controller 102 can communicate with the programmable logic device 104 in a timely manner.

[0088] In this context, both the first preset address and the address of the controller 106 are considered as slave device addresses. The slave device address is the address pre-negotiated between the management controller 102 and each slave device. Each slave device is connected via I / O... 2 The C-bus is connected to the management and control device 102. Therefore, the programmable logic device 104 can be considered as a slave device.

[0089] like Figure 3 As shown, the address of the device is represented by 8 bits.

[0090] The values ​​of the first to fourth bits remain fixed. For example, the first bit is 1, the second bit is 1, the third bit is 1, and the fourth bit is 0.

[0091] Bits 5 through 7, i.e., A2A1A0, can represent the address of the slave device. Among them, A2 can be 0 or 1, A1 can be 0 or 1, and A0 can be 0 or 1.

[0092] The eighth bit, i.e., the read flag R (read) / write flag W (write), indicates a read or write operation.

[0093] When the eighth bit is 1, it indicates a read (R) operation. When the eighth bit is 0, it indicates a write (W) operation.

[0094] Based on the above description, the address of a slave device can be represented by bits 5 to 7, A2A1A0. Therefore, these three bits A2A1A0 can represent the addresses of eight slave devices.

[0095] Therefore, the address of any one of the eight slave devices can be used as the address of the controller 106.

[0096] Register 107 is used to pre-store a value in register 107 via programming. The value stored in register 107 can be changed, and the value of each register 107 is used to indicate an I / O operation between the programmable logic device 104 and a corresponding NVMe hard drive 105 among the plurality of NVMe hard drives 105. 2 Channel C.

[0097] Register 107 is also used to receive a target preset value from the management controller 102. This target preset value is an I / O value between the programmable logic device 104 and an NVMe hard drive 105 that the management controller 102 needs to access. 2The value of register 107 corresponding to channel C. The target preset value, and the I / O between the programmable logic device 104 and the management controller 102 needing to access an NVMe hard drive 105. 2 The C channel corresponds to these two.

[0098] Register 107 is also used to determine whether the target preset value is the same as the value stored in register 107, so that register 107 controls... Figure 2 The switch in the middle is closed, thereby controlling the I / O between the programmable logic device 104 and the target NVMe hard disk 105a. 2 C-channel strobing. The target NVMe hard drive 105a is any NVMe hard drive 105 that the management controller 102 needs to access from among multiple NVMe hard drives 105. The target preset value is the I / O value between the programmable logic device 104 and the target NVMe hard drive 105a. 2 The value of register 107 corresponding to channel C.

[0099] It should be understood that Figure 2 The switch in the code serves only as an identifier, indicating that register 107 can control the I / O between programmable logic device 104 and target NVMe hard disk 105a. 2 Channel C is selected. However, in practical applications, there is no switch entity in the programmable logic device 104, and this identifier has no other substantial meaning.

[0100] The management controller 102 can control the programmable logic device 104 to perform data read and write operations, thereby obtaining the value of register 107 from the programmable logic device 104. Alternatively, the management controller 102 and the programmable logic device 104 can negotiate the value of register 107 in advance.

[0101] Below, in conjunction with Figures 4a-4b This section describes in detail the process by which the management and control device 102 controls the programmable logic device 104 to perform data read and write operations on the value of the register 107.

[0102] like Figure 4a and Figure 4b As shown, the management controller 102 sends a 20-bit signal to the programmable logic device 104, enabling the programmable logic device 104 to perform data read and write operations on the value of register 107.

[0103] The first bit S represents I. 2 The start signal (START condition) of the C bus.

[0104] Bits 2 through 9 represent the slave address; see the above text for details. Figure 3 The description will not be repeated here.

[0105] The tenth bit is A, indicating that there is a feedback signal (acknowledge from slave) used to indicate that the first preset address is the same as the address of the controller 106.

[0106] Bits 11 to 18, i.e., B7-B0, represent the value of the 8-bit register 107.

[0107] The twentieth bit P represents I. 2 The stop signal (STOP condition) of the C bus.

[0108] against Figure 4a Specifically, the nineteenth bit is A, indicating that there is a feedback signal indicating that the target preset value is the same as the value of one of the multiple registers 107. For Figure 4b In this case, the nineteenth bit is NA, indicating that the aforementioned feedback signal does not exist. At this time, Figure 4b Bits 11 through 18 in the register can be used as the last byte read by the management controller 102 from register 107.

[0109] Based on the above description, the value of register 107 can be represented by bits 11 to 18, B7-B0. Therefore, these eight bits B7-B0 can represent 256 values ​​of register 107, i.e., 0-255. These 256 values ​​of register 107 can be used to represent 255 I / O operations. 2 256 states of channel C.

[0110] One of the 256 states is represented by the value of register 107 (e.g., 0xFF, which is 255), representing 255 I's. 2 Channel C is in an unselected state. The remaining 255 states are represented by the values ​​of the remaining 255 registers 107 (e.g., 0-254). Each value in register 107 represents 255 I... 2 The corresponding I in channel C 2 Channel C is set to the strobe state, as shown in Table 1 below.

[0111] Table 1

[0112]

[0113] Because of an I 2 The C channel can connect to one NVMe hard drive 105, therefore, the 255 strobed I channels in Table 1 2The C channel can connect up to 255 NVMe hard drives, meaning that the maximum value of N and M is 255.

[0114] thereby, Figure 4b In this process, the management controller 102 can perform data read operations by controlling the programmable logic device 104 to obtain the values ​​of multiple registers 107 stored in the programmable logic device 104.

[0115] Figure 4a In this process, the management and control device 102 can control the programmable logic device 104 to perform data write operations and transmit the target preset value to the programmable logic device 104.

[0116] Among them, the management control device 102 and the controller 106 are connected via I 2 C bus connection.

[0117] The controller 106 is communicatively connected to the register 107, and the register 107 controls the programmable logic device 104 to be connected to each of the multiple NVMe hard drives 105 to form an I / O block. 2 Channel C.

[0118] Register 107 can be programmed to change the I / O pins of programmable logic device 104. 2 C interface, extended to multiple I 2 For specific connection methods of the C channel, please refer to the programmable logic device 104. The I / O channel of the programmable logic device 104 can be programmed. 2 The C interface is expanded to include multiple I... 2 The description of the C channel will not be repeated here.

[0119] Below, in conjunction with Figure 5 This section explains the implementation process of a management method for multiple NVMe hard drives.

[0120] Please see Figure 5 , Figure 5 This diagram illustrates the signaling interaction of a management method for multiple NVMe hard drives provided in an embodiment of this application.

[0121] like Figure 5 As shown, the management method for multiple NVMe hard drives in this application may include:

[0122] S1010, Management and Control Device to I 2 The C bus sends the first preset address.

[0123] S1011, Programmable Logic Device from I 2 The C bus obtains the first preset address.

[0124] In some embodiments, such as Figure 4a As shown, in the management controller 102 to I 2 After the C bus sends the first preset address and write flag, the controller 106 can access the I bus from the I bus. 2 The C bus acquires the first preset address and write flag.

[0125] S1020. When the programmable logic device determines that the first preset address is the address of the controller, it sends an instruction to I... 2 The C bus sends the first feedback signal.

[0126] S1021, Management and control device from I 2 The C bus acquires the first feedback signal.

[0127] The first feedback signal is used to notify the management controller 102 that the address of the controller 106 is the same as the first preset address.

[0128] In some embodiments, the controller 106 may determine whether the first preset address is the address of the controller 106. If the first preset address is the address of the controller 106, the controller 106 may send an instruction to I... 2 The C bus sends the first feedback signal.

[0129] S1030, Management and Control Device to I 2 The target preset value is sent via the C bus.

[0130] S1031, Programmable Logic Device from I 2 The target preset value is obtained from the C bus.

[0131] Based on the first feedback signal, the management controller 102 can determine that the programmable logic device 104 is communicable. Thus, as... Figure 4a As shown, the management controller 102 can send to I 2 The C-bus transmits a first preset address, a write flag, and a target preset value. Based on the first preset address and the write flag, the programmable logic device 104 determines that it is a slave device that the management control device 102 needs to communicate with. Based on the acquired target preset value, the programmable logic device 104 selects the I-channel corresponding to the target preset value. 2 Channel C.

[0132] In some embodiments, when the management controller 102 sends to I 2 After the C bus sends the first preset address, write flag, and target preset value, the controller 106 sends the I... 2The controller obtains a first preset address, a write flag, and a target preset value from the C-bus. After determining that the first preset address is the address of the controller 106, the controller 106 transmits the target preset value to the register 107. Therefore, the register 107 can select the I-channel corresponding to the target preset value based on the obtained target preset value. 2 Channel C.

[0133] S104. The programmable logic device selects the I / O gate between the programmable logic device and the target NVMe hard drive according to the target preset value. 2 Channel C.

[0134] In some embodiments, when controller 106 from I 2 After the C-bus acquires the target preset value, the controller 106 transmits the target preset value to the register 107. The register 107, based on the target preset value, selects the I / O gate between the programmable logic device 104 and the target NVMe hard drive 105a. 2 Channel C.

[0135] S1050, Programmable Logic Device to I 2 The C bus sends a second feedback signal.

[0136] S1051, Management and control device from I 2 The C bus acquires the second feedback signal.

[0137] The second feedback signal is used to notify the management controller 102 of the I / O connection between the programmable logic device 104 and the target NVMe hard disk 105a. 2 Channel C has been selected.

[0138] In some embodiments, register 107 is used to select the programmable logic device 104 and the target NVMe hard disk 105a. 2 After the C channel, register 107 can notify controller 106 of the I / O communication between register 107 and the target NVMe hard drive 105a. 2 Channel C is selected. Controller 106 can send signals to I... 2 The C bus sends a second feedback signal. Thus, the management controller 102 can receive the signal from the I bus. 2 The C bus receives the second feedback signal.

[0139] Thus, the management controller 102 can be controlled via I 2 The I / O connection between the C-bus and the programmable logic device 104 and the target NVMe hard drive 105a 2 The C channel is used to access the target NVMe hard drive 105a.

[0140] It should be understood that before executing S1010, the management controller 102 may also send a request to I.2 C bus sends I 2 The start signal of the C bus, thereby triggering I 2 The C bus transitions from an idle state to an occupied state.

[0141] After executing S1051, the management controller 102 can also send to I 2 C bus sends I 2 The C bus stop signal triggers I. 2 The C bus transitions from an occupied state to an idle state.

[0142] S106, the management control device communicates via I 2 The C-bus and the I / O between the programmable logic device and the target NVMe hard drive 2 The C channel controls the target NVMe hard drive to perform data read and write operations.

[0143] After the management controller 102 receives the second feedback signal, the management controller 102 can communicate via I... 2 The I / O connection between the C-bus and the programmable logic device 104 and the target NVMe hard drive 105a 2 The C channel controls the target NVMe hard drive 105a to perform data read and write operations.

[0144] When the management controller 102 needs to access multiple NVMe hard drives 105, the access process of the management controller 102 to each NVMe hard drive 105 can be referred to the operations in S1010-S106 above.

[0145] Furthermore, the management controller 102 can change the target preset value via instructions, and the changed target preset value can be regarded as the new target preset value. 2 The C channel allows the management controller 102 to access the I-channel. 2 C bus and the corresponding I of the new target preset value 2 Channel C accesses the I corresponding to the new target preset value. 2 An NVMe hard drive 105 is connected via a C-channel. This allows the management controller 102 to access multiple NVMe hard drives 105.

[0146] The server and method of this application, through the management controller I... 2 C interface and I 2 C bus connection, I 2 C-bus and programmable logic devices 2 C interface connection, I / O of programmable logic devices 2 The C interface can be programmatically extended to multiple I...2 The C channel can be viewed as the I channel for managing control devices. 2 The C interface is expanded to include multiple I... 2 C channel, each I 2 The C-channel connects to one of multiple NVMe hard drives. Furthermore, the management controller selects only one I / O drive at a time from the multiple NVMe hard drives. 2 The C-channel allows for the management of multiple NVMe hard drives by a single controller, simplifying wiring, reducing costs, and preventing multiple NVMe hard drives from sharing the same I / O port. 2 The address conflict problem caused by the C interface can also save I / O power for management and control devices. 2 Resources for the C interface.

[0147] Below, in conjunction with Figure 6 This explains the specific process by which the management controller 102 performs data read and write operations on the target NVMe hard drive 105a in S106.

[0148] Please see Figure 6 , Figure 6 This diagram illustrates the signaling interaction of a management method for multiple NVMe hard drives provided in an embodiment of this application. Figure 6 As shown, the management method for multiple NVMe hard drives in this application may include:

[0149] S201, Management and control device to I 2 C bus sends I 2 The start signal of the C bus.

[0150] S201 is an optional step.

[0151] Among them, I 2 The C bus includes a data line (SDA) and a clock line (SCL).

[0152] I 2 The start signal of the C bus: the clock line is at a high level, and the data line transitions from a high level to a low level.

[0153] In idle state, I 2 The clock line of the C bus is at a high level, and the data line is also at a high level.

[0154] Management controller 102 to I 2 The C bus sends a start signal, i.e., a low-level signal. At this time, I 2 The data lines of the C bus transition from a high level to a low level. Therefore, I... 2 The C bus transitions from an idle state to an occupied state.

[0155] It should be understood that if I 2 If the C bus is in an occupied state, the management controller 102 does not need to send a command to the I bus. 2 The C bus sends a start signal.

[0156] S202, Management and control device to I 2 The C bus sends the second preset address.

[0157] S203, The target NVMe hard drive is connected to the target NVMe hard drive via a programmable logic device (I / O). 2 C channel, from I 2 The C bus obtains the second preset address.

[0158] In some embodiments, when the management controller 102 sends to I 2 After the C bus sends the second preset address, the controller 106 can access the I... 2 The second preset address is obtained via the C bus. The controller 106 transmits the second preset address to register 107. The target NVMe hard drive 105a communicates with the programmable logic device 104 via I / O. 2 Channel C can obtain the second preset address from register 107.

[0159] The second preset address is the address of the target NVMe hard drive 105a that the management controller 102 needs to access.

[0160] S204. When the target NVMe hard disk determines that the second preset address is the address of the target NVMe hard disk, it uses the I / O communication between the programmable logic device and the target NVMe hard disk. 2 C channel, to I 2 The C bus sends a third feedback signal.

[0161] S205, Management and control device from I 2 The C bus acquires the third feedback signal.

[0162] In some embodiments, the target NVMe hard disk 105a may determine whether the second preset address is the address of the target NVMe hard disk 105a.

[0163] When the second preset address is the address of the target NVMe hard disk 105a, the target NVMe hard disk 105a can communicate with the programmable logic device 104 via I / O. 2 Channel C sends a third feedback signal to register 107. Register 107 transmits the third feedback signal to controller 106, and controller 106 sends the third feedback signal to I. 2 C bus.

[0164] The third feedback signal is used to notify the management controller 102 that the address of the target NVMe hard drive 105a is the same as the second preset address. This allows the management controller 102 to determine that the target NVMe hard drive 105a is accessible.

[0165] S206, Management and control device to I 2 The C bus sends a second control signal.

[0166] In some embodiments, after receiving the third feedback signal, the management controller 102 can send a signal to I... 2 The C bus sends a second control signal.

[0167] When the second control signal instructs the target NVMe hard disk 105a to perform a data read operation, the target NVMe hard disk 105a transmits the data stored in the target NVMe hard disk 105a to the management controller 102.

[0168] When the second control signal instructs the target NVMe hard disk 105a to perform a data write operation, the target NVMe hard disk 105a receives the instructions and / or data in the second control signal sent by the management controller 102.

[0169] S207, The target NVMe hard drive is connected to the target NVMe hard drive via a programmable logic device (I / O). 2 C channel, from I 2 The second control signal is obtained from the C bus.

[0170] In some embodiments, when the management controller 102 sends to I 2 After the C bus sends the second control signal, the controller 106 can receive the signal from the I bus. 2 The second control signal is obtained from the C bus, and the controller 106 can transmit the second control signal to the register 107. The target NVMe hard drive 105a can communicate with the programmable logic device 104 via I / O. 2 Channel C obtains the second control signal from register 107.

[0171] S208, The target NVMe hard drive performs data read and write operations according to the second control signal.

[0172] S209. After the target NVMe hard drive completes the data read / write operation, it sends a data to I... 2 The C bus sends a fourth feedback signal.

[0173] S210, Management and Control Device from I 2 The C bus acquires the fourth feedback signal.

[0174] The fourth feedback signal is used to notify the management controller 102 that the target NVMe hard drive 105a has completed the data read / write operation.

[0175] In some embodiments, after performing data read / write operations, the target NVMe hard drive 105a can communicate with the programmable logic device 104 via I / O. 2 Channel C sends a fourth feedback signal to register 107. Register 107 transmits the fourth feedback signal to controller 106, and controller 106 sends the fourth feedback signal to I. 2 C bus. Management and control devices can be accessed from I... 2 The C bus acquires the fourth feedback signal.

[0176] This allows the management controller 102 to know that the target NVMe hard drive 105a has completed data read / write operations.

[0177] S211, Management and control device to I 2 C bus sends I 2 The stop signal for the C bus.

[0178] In some embodiments, after receiving the fourth feedback signal, the management controller 102 can send a signal to I... 2 The C bus sends a stop signal.

[0179] S211 is an optional step.

[0180] I 2 The stop signal for the C bus is when the clock line is at a high level and the data line transitions from a low level to a high level.

[0181] Management controller 102 to I 2 The C bus sends a stop signal, i.e., a high-level signal. At this time, I 2 The data lines of the C bus transition from a low level to a high level. Therefore, I... 2 The C bus transitions from an occupied state to an idle state.

[0182] It should be understood that if I 2 If the C bus is in an idle state or still needs to be occupied, the management controller 102 will not send a signal to I. 2 The C bus sends a stop signal.

[0183] The above S201-S211 is the complete process of the management controller 102 controlling the target NVMe hard disk 105a, that is, any one of the multiple NVMe hard disks 105 to perform data read and write operations.

[0184] Below, in conjunction with Figure 7 Here is an example illustrating another implementation of server 100.

[0185] Please see Figure 7 , Figure 7 A schematic block diagram of a server structure provided in an embodiment of this application is shown. Figure 7 As shown, in Figure 2 Based on the structure of the server 100 shown, the server 100 of this application further includes: a central processing unit (CPU) 108 disposed on the motherboard 101; a programmable logic device 104; and a management module 109.

[0186] Among them, the central processing unit 108 can be accessed via I 2 The C-bus or external communication device SG-IO board is connected to the management module 109.

[0187] The central processing unit 108 and the NVMe hard drive 105 send a first control signal to the management module 109, enabling the management module 109 to control the NVMe hard drive 105 to perform hot-swapping and to control the display status of the corresponding LED light of the NVMe hard drive 105. Thus, the management module 109 can perform hot-swapping and LED control for each NVMe hard drive 105 according to the first control signal.

[0188] In summary, the programmable logic device 104 can realize I / O control over the management and control device 102. 2 The C interface provides extended functionality. Additionally, the programmable logic device 104 can enable hot-swapping and LED management of multiple NVMe hard drives 105.

[0189] It should be understood that in server 100, the above-mentioned implementation of the management controller 102 I 2 The programmable logic device 104, which includes the C interface expansion function, hot-plugging, and LED management functions, can be the same programmable logic device or different programmable logic devices.

[0190] In addition, the programmable logic device 104 can be a programmable logic device that already exists in the backplane 103, or it can be a newly added programmable logic device in the backplane 103.

[0191] In some embodiments, the management controller 102 communicates via I 2 The C-bus connects to the programmable logic device 104, while the central processing unit 108 connects via I... 2 The C bus connects to the programmable logic device 104.

[0192] Typically, only one master device and one slave device can occupy I at any given time. 2 C bus.

[0193] When multiple NVMe hard drives 105 need to perform data read / write operations, the management controller 102 and the programmable logic device 104 connected to the multiple NVMe hard drives 105 occupy I / O space. 2 The C bus performs data read and write operations on multiple NVMe hard drives 105.

[0194] When multiple NVMe hard drives 105 require hot-swapping control, the central processing unit 108 and the programmable logic device 104 connected to the multiple NVMe hard drives 105 occupy I / O space. 2 The C bus enables hot-swapping control of multiple NVMe hard drives 105.

[0195] Below, in conjunction with Figure 8 Here is an example illustrating another implementation of server 100.

[0196] Please see Figure 8 , Figure 8 A schematic block diagram of a server structure provided in an embodiment of this application is shown. Figure 8 As shown, in Figure 6 Based on the structure of the server 100 shown, the server 100 of this application also includes other slave devices 110 disposed on the backplane 103.

[0197] Other slave devices 110 may include devices other than programmable logic device 104, such as other programmable logic devices or memory.

[0198] The addresses of other slave devices 110 are different from the addresses of controller 106.

[0199] Management controller 102 via I 2 The C-bus connects to other slave devices 110. The management controller 102 connects via I-bus. 2 The C bus simultaneously connects programmable logic device 104 and other slave devices 110.

[0200] This application also provides a management device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps in the various method embodiments described above.

[0201] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0202] This application provides a computer program product that, when run on a mobile terminal, enables the mobile device to implement the steps described in the above-described method embodiments.

[0203] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0204] It should be noted that the information interaction and execution process between the above-mentioned devices / modules are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0205] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the above device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0206] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0207] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0208] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0209] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0210] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for managing multiple NVMe hard drives, characterized in that, The method includes: The programmable logic device obtains its first preset address from the management controller via the I²C bus; When the first preset address is the address of the controller, the programmable logic device sends a first feedback signal to the management controller via the I²C bus; The programmable logic device obtains a target preset value from the management and control device through the I²C bus. The target preset value is sent to the I²C bus by the management and control device after obtaining the first feedback signal. The programmable logic device selects the I²C channel between itself and the target NVMe hard drive according to the target preset value. The target NVMe hard drive is any one of a plurality of NVMe hard drives that needs to be accessed. The programmable logic device sends a second feedback signal to the management and control device through the I²C bus, so that after the management and control device receives the second feedback signal, it controls the target NVMe hard drive to perform data read and write operations through the I²C channel between the programmable logic device and the target NVMe hard drive. The I²C interface of the management and control device is connected to the I²C bus, and the I²C bus is also connected to the I²C interface of the programmable logic device; the I²C interface of the programmable logic device and the I²C interface of each of the multiple NVMe hard drives are connected to form an I²C channel. The programmable logic device is used to implement out-of-band management of multiple NVMe hard drives through programming, and the method specifically includes: The controller in the programmable logic device obtains the first preset address from the management control device via the I²C bus; When the first preset address is the address of the controller, the controller sends the first feedback signal to the management controller via the I²C bus; The controller obtains the target preset value from the management controller via the I²C bus; The controller transmits the target preset value to the registers in the programmable logic device; The register selects the I²C channel between the programmable logic device and the target NVMe hard drive according to the target preset value; The register notifies the controller to select the I²C channel between the programmable logic device and the target NVMe hard drive; The controller sends the second feedback signal to the management controller via the I²C bus, enabling the management controller to access the target NVMe hard drive via the I²C bus and the I²C channel between the programmable logic device and the target NVMe hard drive.

2. The method as described in claim 1, characterized in that, The method further includes: The programmable logic device obtains a first control signal from a central processing unit or multiple NVMe hard drives; The programmable logic device performs hot-swapping and LED control on each NVMe hard drive according to the first control signal.

3. A programmable logic device, characterized in that, Used to perform the management method for multiple NVMe hard drives as described in claim 1 or 2.

4. The programmable logic device as described in claim 3, characterized in that, The programmable logic device includes: a controller and registers; The management control device is connected to the controller via the I²C bus, the controller is connected to the register, and the register controls the connection between the programmable logic device and each of the multiple NVMe hard drives to form an I²C channel.

5. A server, characterized in that, include: The management and control device is mounted on the motherboard, and the multiple NVMe hard drives and the programmable logic device as described in claim 3 or 4 are mounted on the backplane; The management and control device is connected to the programmable logic device via an I²C bus, and the programmable logic device is connected to each of the multiple NVMe hard drives to form an I²C channel. The management and control device is used to control the target NVMe hard drive to perform data read and write operations through the I²C channel between the programmable logic device and the target NVMe hard drive after acquiring the second feedback signal.

6. The server as described in claim 5, characterized in that, The management control device is specifically used to send a second preset address to the target NVMe hard drive; The target NVMe hard drive is configured to send a third feedback signal to the management controller when the second preset address is the address of the target NVMe hard drive after receiving the second preset address. The management controller is also used to send a second control signal to the target NVMe hard drive after receiving the third feedback signal; The target NVMe hard drive is also used to perform data read and write operations according to the second control signal after receiving the second control signal.

7. The server as described in claim 5, characterized in that, The server also includes a central processing unit mounted on the motherboard; The central processing unit is used to send a first control signal to the programmable logic device; The programmable logic device is further configured to, upon receiving the first control signal, perform hot-swapping and LED control on each of the plurality of NVMe hard drives according to the first control signal.

8. A management device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in claim 1 or 2.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in claim 1 or 2.

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