Display panel and display device

Abstract

The present invention discloses a display panel and a display device, belonging to the field of display technology. The display panel includes a plurality of sub-pixels. The plurality of sub-pixels are arranged in a first direction to form sub-pixel columns. There are two data lines between two adjacent sub-pixel columns. Each sub-pixel column corresponds to two data lines, namely a first data line and a second data line respectively. Some sub-pixels in the same sub-pixel column are connected to the first data line, and the remaining sub-pixels in the same sub-pixel column are connected to the second data line. The non-display area of the display panel includes a multiplexing circuit. The multiplexing unit of the multiplexing circuit includes a signal input terminal, a plurality of signal output terminals, a plurality of shunt control terminals, and a plurality of switching transistors. The display device includes the above-mentioned display panel. The present invention can take into account both high refresh frequency and high resolution, and can also meet the charging time, improving the display quality.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and more particularly, to a display panel and a display device. Background Art

[0002] As a current-driven light-emitting device, an Organic Light Emitting Diode (OLED) has been widely used in display devices such as mobile phones and tablet computers due to its self-luminous, fast response, wide viewing angle, and the ability to be fabricated on flexible substrates.

[0003] The refresh rate and resolution of a display panel are key indicators for measuring the quality of the display panel. With the continuous improvement of user requirements, high refresh rates and high resolutions have become an industry trend. As the refresh rate and resolution increase, the pixel charging time of the display panel will be shortened, which will lead to insufficient charging time for the pixels, making it impossible for each pixel to be fully charged, and the display effect cannot be guaranteed at low gray levels, affecting the display effect of the display device, such as the problem of poor display uniformity is likely to occur.

[0004] Therefore, it is a technical problem that needs to be urgently solved by those skilled in the art to provide a display panel and a display device that can take into account high refresh rates and high resolutions, and can also meet the charging time and improve the display quality. Summary of the Invention

[0005] In view of this, the present invention provides a display panel and a display device to solve the problem in the prior art that for a display device with a high refresh rate, the charging time is easily insufficient, resulting in a poor display effect.

[0006] The present invention discloses a display panel, including: a plurality of sub-pixels, the plurality of sub-pixels are arranged in a first direction to form sub-pixel columns, and the plurality of sub-pixel columns are arranged in a second direction; wherein, the first direction and the second direction intersect; there are two data lines between adjacent two sub-pixel columns, and two data lines correspond to the same sub-pixel column, and are respectively a first data line and a second data line; a part of the sub-pixels in the same sub-pixel column are connected to the first data line, and the remaining part of the sub-pixels in the same sub-pixel column are connected to the second data line; the display panel includes a non-display area, the non-display area includes a multiplexing circuit, and the multiplexing circuit includes a plurality of multiplexing units; the multiplexing unit includes a signal input terminal, a plurality of signal output terminals, a plurality of shunt control terminals, and a plurality of switching transistors, the gate of the switching transistor is connected to the shunt control terminal, the first pole of the switching transistor is connected to the signal input terminal, and the second pole of the switching transistor is connected to the signal output terminal; the signal input terminal is connected to a data voltage signal, and the signal output terminal is electrically connected to the data line in a one-to-one correspondence.

[0007] Based on the same inventive concept, the present invention also discloses a display device, which includes the above-mentioned display panel.

[0008] Compared with the prior art, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

[0009] In the display panel of the present invention, a multiplexing circuit cooperates with two data lines to charge the sub-pixels of a sub-pixel column simultaneously, which is beneficial to improving the charging time. When a sub-pixel of the same sub-pixel column is controlled by a clock control signal of a multiplexing unit, the switching transistor corresponding to the clock control signal is turned on, and the data voltage signal is charged into one data line (such as the first data line). The first data line provides the data voltage signal to the corresponding sub-pixel that has been driven to be turned on by the scan driving circuit in the sub-pixel column, and then the corresponding sub-pixel is driven to display. When the corresponding sub-pixel that has been driven to be turned on by the scan driving circuit is displaying (that is, after the switching transistor corresponding to a clock control signal of the multiplexing unit is turned off), another clock control signal of the multiplexing unit controls the corresponding switching transistor to be turned on, and a data voltage signal is also being charged correspondingly on the other data line (such as the second data line) corresponding to the sub-pixel column. However, at this time, since the other sub-pixels in the same sub-pixel column corresponding to the second data line have not been turned on by the scan driving circuit (the scan driving circuit controls the scan lines to be driven to be turned on row by row), although a data voltage signal is being charged on the second data line of the sub-pixel column at this time, no driving current is generated in some of the sub-pixels connected to the second data line, and they will not emit light and display. It is equivalent to that at this time, under the control of another clock control signal of the multiplexing unit, only the second data line is pre-charged. Thus, through the cooperation of the multiplexing circuit, pre-charging of the second data line corresponding to some of the sub-pixels in the same sub-pixel column is achieved. Furthermore, the actual charging time of the sub-pixels in the sub-pixel column can be increased. It can be applicable to display panels with high refresh rates and high resolutions, and at the same time, by pre-charging the data voltage signal to the second data line, the charging time required for charging the sub-pixels can be satisfied, which is beneficial to improving the display quality. Through the design of the multiplexing circuit in the non-display area of the present invention, while meeting the narrow border requirement of the display panel, through the design of matching two data lines for one sub-pixel column, the actual charging time of the sub-pixels in the display panel can also be improved, which is beneficial to ensuring the display quality of high-resolution and high-refresh-rate display panels.

[0010] Of course, it is not necessary for any product implementing the present invention to specifically achieve all the above-mentioned technical effects simultaneously.

[0011] Through the following detailed description of the exemplary embodiments of the present invention with reference to the accompanying drawings, other features and advantages of the present invention will become clear. Description of the Drawings

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0013] Figure 1 It is a schematic plan view of a display panel provided by an embodiment of the present invention;

[0014] Figure 2 is Figure 1 A partial enlarged schematic view of the connection between the multiplexing circuit and the data line in;

[0015] Figure 3 It is another schematic plan view of a display panel provided by an embodiment of the present invention;

[0016] Figure 4 It is another schematic plan view of a display panel provided by an embodiment of the present invention;

[0017] Figure 5 It is another schematic plan view of a display panel provided by an embodiment of the present invention;

[0018] Figure 6 is Figure 5 A partial enlarged schematic view of the connection between the multiplexing circuit and the data line in;

[0019] Figure 7 It is another schematic plan view of a display panel provided by an embodiment of the present invention;

[0020] Figure 8 is Figure 7 A partial enlarged schematic view in;

[0021] Figure 9 It is another schematic plan view of a display panel provided by an embodiment of the present invention;

[0022] Figure 10 is Figure 9 A partial enlarged schematic view in;

[0023] Figure 11 It is another schematic plan view of a display panel provided by an embodiment of the present invention;

[0024] Figure 12 is Figure 11 A partial enlarged schematic view in;

[0025] Figure 13 It is another schematic plan view of a display panel provided by an embodiment of the present invention;

[0026] Figure 14 is Figure 13Schematic diagram of a partial enlarged structure where a multiplexing circuit is connected to a data line;

[0027] Figure 15 It is another schematic diagram of the planar structure of the display panel provided by an embodiment of the present invention;

[0028] Figure 16 It is Figure 15 the schematic diagram of the partial enlarged structure in;

[0029] Figure 17 It is another schematic diagram of the planar structure of the display panel provided by an embodiment of the present invention;

[0030] Figure 18 It is Figure 17 the schematic diagram of the partial enlarged structure in;

[0031] Figure 19 It is the schematic diagram of the planar structure of the display device provided by an embodiment of the present invention. Detailed implementation manners

[0032] Now, various exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that: Unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention.

[0033] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present invention or its application or use.

[0034] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be regarded as part of the specification.

[0035] In all the examples shown and discussed herein, any specific values should be construed as merely exemplary and not as limitations. Therefore, other examples of the exemplary embodiments may have different values.

[0036] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0037] Please refer to Figure 1 and Figure 2 , Figure 1 which is a schematic diagram of the planar structure of the display panel provided by an embodiment of the present invention, Figure 2 is Figure 1Schematic diagram of a partial enlarged structure of a multiplexing circuit connected to a data line. The display panel 000 provided in this embodiment includes: a plurality of sub-pixels P, the plurality of sub-pixels P are arranged in a sub-pixel column PL along a first direction Y, and the plurality of sub-pixel columns PL are arranged along a second direction X; wherein, the first direction Y and the second direction X intersect;

[0038] There are two data lines S between two adjacent sub-pixel columns PL. The same sub-pixel column PL corresponds to two data lines S, which are the first data line S1 and the second data line S2 respectively; some sub-pixels P of the same sub-pixel column PL are connected to the first data line S1, and the remaining sub-pixels P of the same sub-pixel column PL are connected to the second data line S2;

[0039] The display panel 000 includes a non-display area NA. The non-display area NA includes a multiplexing circuit 10. The multiplexing circuit 10 includes a plurality of multiplexing units 101;

[0040] The multiplexing unit 101 includes a signal input terminal 101A, a plurality of signal output terminals 101B, a plurality of shunt control terminals 101C, and a plurality of switching transistors 101T. The gate of the switching transistor 101T is connected to the shunt control terminal 101C, the first pole of the switching transistor 101T is connected to the signal input terminal 101A, and the second pole of the switching transistor 101T is connected to the signal output terminal 101B; the signal input terminal 101A is connected to the data voltage signal Vdata, and the signal output terminal 101B is electrically connected to the data line S in one-to-one correspondence.

[0041] Specifically, the display panel 000 provided in this embodiment may be an organic light-emitting diode display panel. The display panel 000 includes a plurality of sub-pixels P. Optionally, the sub-pixels P in this embodiment may be arranged in an array. Or in some other alternative embodiments, the plurality of sub-pixels P included in the display panel 000 may also be arranged in other ways such as a diamond arrangement or a windmill arrangement. This embodiment does not make specific limitations in this regard. During specific implementation, the arrangement structure of the sub-pixels P can be set according to the actual requirements of the display panel 000. The plurality of sub-pixels P in this embodiment are arranged in a sub-pixel column PL along the first direction Y, and the plurality of sub-pixel columns PL are arranged along the second direction X. Optionally, the sub-pixel P may include a pixel circuit and an organic light-emitting diode (not shown in the figure). The organic light-emitting diode is a current-driven element, and the pixel circuit is used to provide a driving current for the organic light-emitting diode in the corresponding sub-pixel P to control its light emission. The data line S in the display panel 000 is generally connected to a data driving circuit (not shown in the figure) in the border area, and is used to provide a data voltage signal Vdata for the pixel circuits of the respective sub-pixels P. In this embodiment, it is set that in the display panel 000, two data lines S are included between two adjacent sub-pixel columns PL. The plurality of sub-pixels P in the same sub-pixel column PL are connected to two data lines S, and the two data lines S to which the sub-pixels P in the same sub-pixel column PL are electrically connected are respectively named the first data line S1 and the second data line S2. Some of the sub-pixels P in the same sub-pixel column PL are connected to the first data line S1, and the remaining sub-pixels P in the same sub-pixel column PL are connected to the second data line S2. Optionally, half of the sub-pixels P in the same sub-pixel column PL can be connected to the first data line S1, and the remaining half of the sub-pixels P in the same sub-pixel column PL can be connected to the second data line S2, which is beneficial to ensuring the uniformity of the data voltage signal Vdata charged into the same sub-pixel column PL by each data line S.

[0042] In this embodiment, the non-display area NA of the display panel 000 is also provided with a multiplexing circuit 10, which is used to provide a data voltage signal Vdata to each data line S. The multiplexing circuit 10 includes a plurality of multiplexing units 101, and the multiplexing unit 101 is a demultiplexer, which is used to decompose a signal into multiple signal channels. Optionally, each multiplexing unit 101 includes a signal input terminal 101A, a plurality of signal output terminals 101B, a plurality of branch control terminals 101C, and a plurality of switching transistors 101T. The number of branch control terminals 101C, the number of signal output terminals 101B, and the number of switching transistors 101T included in each multiplexing unit 101 can be equal. The gate of the switching transistor 101T is connected to the branch control terminal 101C, and the on or off state of the switching transistor 101T is controlled by the clock control signal input through the branch control terminal 101C. For example, if the switching transistor 101T is a P-type transistor, the clock control signal is input to the gate of the switching transistor 101T with a low-level signal (such as a negative voltage), and the switching transistor 101T is in the on state. If the switching transistor 101T is an N-type transistor, the clock control signal is input to the gate of the switching transistor 101T with a high-level signal (such as a positive voltage), and the switching transistor 101T is in the on state. In this embodiment, the type of the switching transistor 101T is not specifically limited, and only the P-type transistor is used as an example in the figure for illustration. The first poles of the plurality of switching transistors 101T in the same multiplexing unit 101 of this embodiment are all connected to a signal input terminal 101A. When the corresponding switching transistor 101T is in the on state under the control of the clock control signal, conduction transmission can occur between the signal input terminal 101A connected to the first pole of the switching transistor 101T and the signal output terminal 101B connected to the second pole. Since the signal input terminal 101A of this embodiment is connected to the data voltage signal Vdata (optionally, the data voltage signal Vdata can be provided by a driving chip bonded in the non-display area NA, which is not shown in the figure), and the signal output terminals 101B are electrically connected to the data lines S one by one. Therefore, when the switching transistor 101T is turned on, the data voltage signal Vdata provided by one signal input terminal 101A included in each multiplexing unit 101 can be transmitted to the multiple data lines S connected to the corresponding signal output terminals 101B, and then the data driving signal is provided to the sub-pixel P through the data line S, realizing the light-emitting display effect of the sub-pixel P.Since one signal input terminal 101A of each multiplexing unit 101 corresponds to multiple signal output terminals 101B through multiple switching transistors 101T, the data voltage signal Vdata of one signal input terminal 101A can be decomposed into multiple signal channels and transmitted to multiple data lines S simultaneously or at different times. This helps reduce the number of data signal transmission lines connected to the signal input terminal 101A in the non-display area NA, thereby facilitating the reduction of the layout space of the non-display area NA, narrowing the border of the display panel 000, and achieving a narrow border design.

[0043] In this embodiment, while charging the sub-pixels P in the same sub-pixel column PL with the data voltage signal Vdata through two data lines S, the non-display area NA of the display panel 000 is also provided with a multiplexing circuit 10. The multiplexing circuit 10 cooperates with the two data lines S to charge the sub-pixels P in a sub-pixel column PL at the same time, which is beneficial to improving the charging time. When a sub-pixel P in the same sub-pixel column PL is controlled by a clock control signal CKH1 of a multiplexing unit 101, the switching transistor 101T corresponding to the clock control signal CKH1 is turned on, and the data voltage signal Vdata is charged into one data line S (such as the first data line S1). The first data line S1 provides the data voltage signal Vdata to the corresponding sub-pixel P in the sub-pixel column PL that has been driven and turned on by the scan driving circuit, and then the corresponding sub-pixel P is driven to display. When the corresponding sub-pixel P that has been driven and turned on by the scan driving circuit is displaying (that is, after the switching transistor 101T corresponding to the control of a clock control signal CKH1 of the multiplexing unit 101 is turned off), another clock control signal CKH2 of the multiplexing unit 101 controls the corresponding switching transistor 101T to be turned on, and the data voltage signal Vdata is also being charged correspondingly on the other data line S (such as the second data line S2) corresponding to the sub-pixel column PL. However, at this time, since other sub-pixels P in the same sub-pixel column PL corresponding to the second data line S2 have not been turned on by the scan driving circuit (the scan driving circuit controls the scan lines to be driven and turned on row by row), although the data voltage signal Vdata is being charged on the second data line S2 of the sub-pixel column PL at this time, no driving current is generated in some of the sub-pixels P connected to the second data line S2, and they will not emit light and display. It is equivalent to that at this time, under the control of another clock control signal CKH2 of the multiplexing unit 101, only the second data line S2 is pre-charged. Thus, through the cooperation of the multiplexing circuit 10, the pre-charging of the second data line S2 corresponding to some of the sub-pixels P in the same sub-pixel column PL is realized. Furthermore, the actual charging time of the sub-pixels P in the sub-pixel column PL can be increased. It can be applied to the display panel 000 with a high refresh rate and high resolution, and at the same time, the charging time required to charge the sub-pixels P can be satisfied by pre-charging the data voltage signal Vdata on the second data line S2, which is beneficial to improving the display quality. And through the design of the multiplexing circuit 10 in the non-display area NA in this embodiment, while meeting the narrow border requirement of the display panel 000, by cooperating with the design of two data lines S corresponding to a sub-pixel column PL, the actual charging time of the sub-pixels P in the display panel 000 can also be increased, which is beneficial to ensuring the display quality of the high-resolution and high-refresh-rate display panel 000.

[0044] It can be understood that the number of signal output terminals 101B corresponding to one signal input terminal 101A of each multiplexing unit 101 in this embodiment is only based on the example that one signal input terminal 101A of each multiplexing unit 101 corresponds to two signal output terminals 101B. In specific implementation, the more the number of signal output terminals 101B corresponding to one signal input terminal 101A of each multiplexing unit 101 is, the more the frame size can be reduced, and a narrower frame design can be achieved. Figure 2 In the figure, only an example is taken in which a signal input terminal 101A of each multiplexing unit 101 is connected to two data lines S corresponding to the same sub-pixel column PL through two switching transistors 101T corresponding to two signal output terminals 101B. For example, if the two switching transistors 101T are 101T1 and 101T2 respectively, then the shunt control terminals 101C connected to the gates of the three switching transistors 101T are 101C1 and 101C2 respectively, the shunt control terminal 101C1 is connected to the clock control signal CKH1, and the shunt control terminal 101C2 is connected to the clock control signal CKH2. In specific implementation, the number of signal output terminals 101B corresponding to a signal input terminal 101A of each multiplexing unit 101 can be more, and this embodiment does not make any specific limitation on this.

[0045] It should be noted that the display panel 000 provided in this embodiment can be an organic light emitting diode display panel. The figure of this embodiment only illustrates the structure of the display panel for example. In specific implementation, the structure of the display panel 000 includes but is not limited to this, and may also include other structures that can realize the display function. For details, please refer to the structure of the organic light emitting diode display panel in the relevant technology for understanding, and this embodiment will not be elaborated here.

[0046] Optionally, as shown in Table 1, the actual charging time is calculated by selecting display panels with different resolutions and different refresh rates. The results are shown in Table 1 below:

[0047]

[0048] As can be seen from Table 1, for a display panel with a refresh rate of 120 Hz and a resolution of 1080×2400 (which means there are 1080 sub-pixels in the second direction X of the horizontal direction of the display panel and 2400 sub-pixels in the first direction Y of the vertical direction), when using the design of charging one sub-pixel column corresponding to one data line (i.e., SDL, Single Data Line) in combination with a non-multiplexing circuit (no demux), the time of 1H (1H represents the ratio of the time of one frame of the display panel to the number of rows of all sub-pixel rows in the display panel, and the interval time between the scan driving signal of the pixel circuit in the current sub-pixel row and the scan driving signal of the pixel circuit in the next sub-pixel row is 1H) is 3.4 μs, and the actual charging time is 2.3 μs; among them, for a display panel with a refresh rate of 120 Hz, the time of one frame is 1 / 120 s, that is, 8333 μs, and for a display panel with a resolution of 1080×2400, the number of rows of all sub-pixel rows is 2400 rows, so 1H is the ratio of 8333 μs to 2400 rows, which is approximately 3.4 μs.

[0049] For a display panel with a refresh rate of 120 Hz and a resolution of 1236×2676, when using the design of charging one sub-pixel column corresponding to one data line (i.e., SDL) in combination with a non-multiplexing circuit (no demux), the time of 1H is 3.0 μs, and the actual charging time is only 1.9 μs, indicating that for display panels with the same refresh rate, the higher the resolution, the more likely the charging time is insufficient;

[0050] For a display panel with a refresh rate of 144 Hz and a resolution of 1080×2400, when using the design of charging one sub-pixel column corresponding to one data line (i.e., SDL) in combination with a non-multiplexing circuit (no demux), the time of 1H is 2.8 μs, and the actual charging time is only 1.7 μs, indicating that for display panels with the same resolution, the higher the refresh rate, the more likely the charging time is insufficient;

[0051] For a display panel with a refresh rate of 144 Hz and a resolution of 1236×2676, when using the design of charging one sub-pixel column corresponding to one data line (i.e., SDL) in combination with a non-multiplexing circuit (no demux), the time of 1H is 2.5 μs, and the actual charging time is only 1.4 μs, indicating that for display panels with the same refresh rate, the higher the resolution, the more likely the charging time is insufficient;

[0052] For a display panel with a refresh rate of 165 Hz and a resolution of 1080×2400, when using the design of charging one data line corresponding to one sub-pixel column (SDL) in combination with a non-multiplexing circuit (without demux), the time of 1H is 2.5 μs, and the actual charging time is only 1.4 μs or 1.2 μs; while when using the design of charging two data lines corresponding to one sub-pixel column (DDL, Dual Data Line) in combination with a multiplexing circuit (with demux, such as the 1:2 demux shown in this embodiment Figure 2 When the design of the 1:2 demux is used, the time of 1H is also 2.5 μs, and the actual charging time can be increased to at least 2.5 μs, increasing from 1.2 μs to 2.5 μs. It can be proved that the combined design of using the multiplexing circuit 10 and one sub-pixel column PL corresponding to two data lines S in this case can greatly improve the actual charging time of the sub-pixel P in the display panel 000, and thus can be applied to the display panel 000 with a high refresh rate.

[0053] For a display panel with a refresh rate of 165 Hz and a resolution of 1220×2712, when using the design of charging one data line corresponding to one sub-pixel column (SDL) in combination with a non-multiplexing circuit (without demux), the time of 1H is 2.2 μs, and the actual charging time is only 1.1 μs or 0.9 μs; while when using the design of charging two data lines corresponding to one sub-pixel column (DDL) in combination with a multiplexing circuit (with demux, such as the 1:2 demux shown in this embodiment Figure 2 When the design of the 1:2 demux is used, the time of 1H is also 2.2 μs, and the actual charging time can be increased to at least 2.2 μs, increasing from 0.9 μs to 2.2 μs. It can be proved that the combined design of using the multiplexing circuit 10 and one sub-pixel column PL corresponding to two data lines S in this case can greatly improve the actual charging time of the sub-pixel P in the display panel 000, and thus can be applied to the display panel 000 with a high resolution.

[0054] In some alternative embodiments, please refer to Figure 2 and Figure 3 , Figure 3 FIG. is another schematic plan view of the display panel provided by the embodiment of the present invention. In this embodiment, for the same sub-pixel column PL, along the first direction Y, the A-th sub-pixel P is connected to the first data line S1, and the (A + 1)-th sub-pixel P is connected to the second data line S2; where A is a positive integer.

[0055] This embodiment explains that the same sub-pixel column PL is correspondingly connected to two data lines S. That is, when charging data voltage signals into multiple sub-pixels P of the same sub-pixel column PL through two data lines S, along the first direction Y, the A-th sub-pixel P of the same sub-pixel column PL can be connected to the first data line S1, and the (A + 1)-th sub-pixel P can be connected to the second data line S2. For example, along the first direction Y, odd-numbered sub-pixels P are connected to the first data line S1, and even-numbered sub-pixels P are connected to the second data line S2; or odd-numbered sub-pixels P are connected to the second data line S2, and even-numbered sub-pixels P are connected to the first data line S1. Thus, the number of sub-pixels P connected to each of the two data lines S corresponding to the same sub-pixel column PL can be made substantially equal, ensuring charging uniformity. At the same time, the impedance of the two data lines S corresponding to the same sub-pixel column PL for transmitting signals to two adjacent sub-pixels P in the first direction Y can be made substantially the same, as much as possible ensuring that the display of two adjacent sub-pixels P in the first direction Y is as uniform as possible, which is conducive to improving the display quality.

[0056] It can be understood that in this embodiment, only an example where multiple sub-pixels P are arranged in an array is illustrated. In some other alternative embodiments, multiple sub-pixels P can also be arranged in other ways, such as Figure 4 shown Figure 4 is another schematic plan view of the display panel provided by the embodiment of the present invention. Figure 4 The arrangement of multiple sub-pixels P in the display panel 000 schematically shown therein can be understood as a diamond arrangement or a quasi-diamond arrangement. At this time, the connection structure of the first data line S1 and the second data line S2 can also refer to the way in the above embodiment. That is, for any structure with different sub-pixel arrangement ways, the design structure of the above embodiment can be adopted to achieve the effect of improving the display quality, and this embodiment will not be elaborated here.

[0057] In some alternative embodiments, please continue to refer to Figures 1 - 4 In this embodiment, the multiplexing unit 101 includes a signal input terminal 101A, M signal output terminals 101B, M branch control terminals 101C, and M switching transistors 101T; where M ≥ 2 and M is an integer.

[0058] This embodiment explains that a multiplexing circuit 10 is set in the non-display area NA, and the multiplexing circuit 10 includes a plurality of multiplexing units 101. The multiplexing unit 101 can decompose a signal into at least two signal channels. That is, the multiplexing unit 101 includes a signal input terminal 101A and M signal output terminals 101B, M branch control terminals 101C, and M switch transistors 101T; wherein M≥2. The signal input terminal 101A of this embodiment is connected to the data voltage signal Vdata (optionally, the data voltage signal Vdata can be provided by a driver chip bound in the non-display area NA, which is not shown in the figure), and the signal output terminal 101B is electrically connected to the data line S one by one. Therefore, when the switch transistor 101T is turned on, the data voltage signal Vdata provided by a signal input terminal 101A included in each multiplexing unit 101 can be transmitted to at least two data lines S connected to the corresponding at least two signal output terminals 101B. Optionally, the data voltage signal Vdata provided by a signal input terminal 101A included in each multiplexing unit 101 can be transmitted to two data lines S corresponding to the same sub-pixel column PL (such as Figure 1 As shown), a data driving signal is provided to the sub-pixel P through the data line S to realize the luminous display effect of the sub-pixel P. Since one signal input terminal 101A of each multiplexing unit 101 corresponds to at least two signal output terminals 101B through at least two switch transistors 101T, the data voltage signal Vdata of one signal input terminal 101A can be decomposed into at least two signal channels, and transmitted to at least two data lines S in the display area AA simultaneously or in a time-sharing manner, which is conducive to further reducing the number of data signal transmission lines connected to the signal input terminal 101A in the non-display area NA, and further reducing the frame of the display panel 000. While realizing a narrower frame design, it can also cooperate with the design of one sub-pixel column PL corresponding to two data lines S to improve the actual charging time of the sub-pixel P in the display panel 000, and ensure the display quality of the high-resolution and high-refresh-rate display panel 000 as much as possible.

[0059] It should be noted that the drawings in this embodiment only illustrate the example in which the multiplexing unit 101 includes a signal input terminal 101A and two signal output terminals 101B, two branch control terminals 101C, and two switch transistors 101T, that is, the multiplexing unit 101 decomposes a signal into at least two signal channels. In specific implementation, the multiplexing unit 101 can also be configured to decompose a signal into a structure of more signal channels, which is not elaborated in this embodiment.

[0060] In some optional embodiments, please refer to Figure 5 and Figure 6 , Figure 5It is another schematic plan view of the display panel provided by the embodiment of the present invention. Figure 6 It is Figure 5 A partial enlarged schematic structural view of the multiplexing circuit connected to the data line in Figure 5 . In this embodiment, the multiplexing unit 101 includes a signal input terminal 101A, four signal output terminals 101B, four branch control terminals 101C, and four switching transistors 101T.

[0061] The gates of the four switching transistors 101T are respectively connected to the four branch control terminals 101C. The first poles of the four switching transistors 101T are all connected to the signal input terminal 101A. The second poles of the four switching transistors 101T are respectively connected to the four signal output terminals 101B.

[0062] The signal input terminal 101A is connected to the data voltage signal Vdata. The four signal output terminals 101B are respectively and electrically connected to the four data lines S corresponding to the two sub-pixel columns PL one by one.

[0063] Optionally, two adjacent sub-pixel columns PL include a first sub-pixel column PL1 and a second sub-pixel column PL2.

[0064] In one multiplexing unit 101, the four signal output terminals 101B include a first signal output terminal 101B1, a second signal output terminal 101B2, a third signal output terminal 101B3, and a fourth signal output terminal 101B4. The four switching transistors 101T include a first switching transistor 101T1, a second switching transistor 101T2, a third switching transistor 101T3, and a fourth switching transistor 101T4. The four branch control terminals 101C include a first branch control terminal 101C1, a second branch control terminal 101C2, a third branch control terminal 101C3, and a fourth branch control terminal 101C4.

[0065] The gate of the first switching transistor 101T1 is connected to the first branch control terminal 101C1. The second pole of the first switching transistor 101T1 is connected to the first signal output terminal 101B1.

[0066] The gate of the second switching transistor 101T2 is connected to the second branch control terminal 101C2. The second pole of the second switching transistor 101T2 is connected to the second signal output terminal 101B2.

[0067] The gate of the third switching transistor 101T3 is connected to the third branch control terminal 101C3. The second pole of the third switching transistor 101T3 is connected to the third signal output terminal 101B3.

[0068] The gate of the fourth switching transistor 101T4 is connected to the fourth branch control terminal 101C4. The second pole of the fourth switching transistor 101T4 is connected to the fourth signal output terminal 101B4.

[0069] The first data line S1 of the first sub-pixel column PL1 is connected to the first signal output terminal 101B1, the second data line S2 of the first sub-pixel column PL1 is connected to the second signal output terminal 101B2, the first data line S1 of the second sub-pixel column PL2 is connected to the third signal output terminal 101B3, and the second data line S2 of the second sub-pixel column PL2 is connected to the fourth signal output terminal 101B.

[0070] In this embodiment, it is explained that in the multiplexing circuit 10 provided in the non-display area NA of the display panel 000, the multiplexing unit 101 can decompose one signal into 4 signal channels. That is, the multiplexing unit 101 includes a signal input terminal 101A, M signal output terminals 101B, M shunt control terminals 101C, and M switching transistors 101T; where M = 4. The signal input terminal 101A of this embodiment is connected to the data voltage signal Vdata (optionally, the data voltage signal Vdata can be provided by a driving chip bonded in the non-display area NA, not shown in the figure). The signal output terminals 101B are electrically connected to the data lines S one by one. Therefore, when the switching transistor 101T is turned on, the data voltage signal Vdata provided by one signal input terminal 101A included in each multiplexing unit 101 can be transmitted to the four data lines S connected to the corresponding 4 signal output terminals 101B. Optionally, the data voltage signal Vdata provided by one signal input terminal 101A included in each multiplexing unit 101 can be transmitted to the four data lines S corresponding to two adjacent sub-pixel columns PL (as Figure 5 shown).

[0071] In this embodiment, while charging the sub-pixel P in the same sub-pixel column PL with the data voltage signal Vdata through two data lines S, the non-display area NA of the display panel 000 is also provided with a multiplexing circuit 10. The multiplexing circuit 10 cooperates with four data lines S to charge the sub-pixels P in two adjacent sub-pixel columns PL simultaneously, which is beneficial to improving the charging time. When a sub-pixel P in the first sub-pixel column PL1 is controlled by a clock control signal CKH1 of a multiplexing unit 101, the switching transistor 101T corresponding to the clock control signal CKH1 is turned on, and the data voltage signal Vdata is charged into a data line S (such as the first data line S1). The first data line S1 provides the data voltage signal Vdata to the corresponding sub-pixel P in the first sub-pixel column PL1 that has been driven and turned on by the scan driving circuit, and then the corresponding sub-pixel P is driven to display. When the corresponding sub-pixel P that has been driven and turned on by the scan driving circuit is displaying (i.e., after the switching transistor 101T corresponding to a clock control signal CKH1 of the multiplexing unit 101 is turned off), another clock control signal CKH2 of the multiplexing unit 101 controls the corresponding switching transistor 101T to be turned on, and the data voltage signal Vdata is also being charged into another data line S (such as the second data line S2) corresponding to the first sub-pixel column PL1. However, at this time, since the other sub-pixels P in the first sub-pixel column PL1 corresponding to the second data line S2 have not been turned on by the scan driving circuit yet (the scan driving circuit controls the scan lines to drive and turn on row by row), although the data voltage signal Vdata is being charged into the second data line S2 of the first sub-pixel column PL1 at this time, no driving current is generated in some of the sub-pixels P connected to the second data line S2, and they will not emit light and display. It is equivalent to that at this time, under the control of another clock control signal CKH2 of the multiplexing unit 101, only the second data line S2 is pre-charged. Similarly, when another sub-pixel P in the first sub-pixel column PL1 is controlled by another clock control signal CKH2 of a multiplexing unit 101, the switching transistor 101T corresponding to the clock control signal CKH2 is turned on, and the data voltage signal Vdata is charged into another data line S (such as the second data line S2). The second data line S2 provides the pre-charged and newly charged data voltage signals Vdata together to the other corresponding sub-pixels P in the first sub-pixel column PL1 that have been driven and turned on by the scan driving circuit, and then the other sub-pixels P in the first sub-pixel column PL1 are driven to display.When other sub-pixels P corresponding to the first sub-pixel column PL1 that have been driven to turn on by the scan driving circuit are displaying (i.e., after the switching transistor 101T corresponding to another clock control signal CKH2 of the multiplexing unit 101 is turned off), another clock control signal CKH3 of the multiplexing unit 101 controls the corresponding switching transistor 101T to turn on, and a data voltage signal Vdata is also being charged correspondingly on a data line S (such as the first data line S1) corresponding to the second sub-pixel column PL2. However, at this time, since other sub-pixels P in the second sub-pixel column PL2 corresponding to this first data line S1 have not been driven to turn on by the scan driving circuit (the scan driving circuit controls the scan lines to drive and turn on row by row), although the data voltage signal Vdata is being charged on the first data line S1 of the second sub-pixel column PL2 at this time, no driving current is generated in some sub-pixels P of the second sub-pixel column PL2 corresponding to the connection of this first data line S1, and they will not emit light for display. It is equivalent to that at this time, under the control of another clock control signal CKH3 of the multiplexing unit 101, only the first data line S1 of the second sub-pixel column PL2 is pre-charged. Similarly, when a sub-pixel P in the second sub-pixel column PL1 is controlled by another clock control signal CKH3 of a multiplexing unit 101, the switching transistor 101T corresponding to this clock control signal CKH3 is turned on, and the data voltage signal Vdata is charged into a data line S (such as the first data line S1). This first data line S1 provides the pre-charged and newly charged data voltage signal Vdata together to the corresponding sub-pixel P in the second sub-pixel column PL2 that has been driven to turn on by the scan driving circuit, then some sub-pixels P corresponding to the second sub-pixel column PL2 are driven to display. When some sub-pixels P corresponding to the second sub-pixel column PL2 that have been driven to turn on by the scan driving circuit are displaying (i.e., after the switching transistor 101T corresponding to another clock control signal CKH3 of the multiplexing unit 101 is turned off), another clock control signal CKH4 of the multiplexing unit 101 controls the corresponding switching transistor 101T to turn on, and a data voltage signal Vdata is also being charged correspondingly on another data line S (such as the second data line S2) corresponding to the second sub-pixel column PL2. However, at this time, since other sub-pixels P in the second sub-pixel column PL2 corresponding to this second data line S2 have not been driven to turn on by the scan driving circuit (the scan driving circuit controls the scan lines to drive and turn on row by row), although the data voltage signal Vdata is being charged on the second data line S2 of the second sub-pixel column PL2 at this time, no driving current is generated in some sub-pixels P of the second sub-pixel column PL2 corresponding to the connection of this second data line S2, and they will not emit light for display. It is equivalent to that at this time, under the control of another clock control signal CKH4 of the multiplexing unit 101, only the second data line S2 of the second sub-pixel column PL2 is pre-charged.And so on, when charging the data voltage signal to each corresponding sub-pixel P through each data line S, it is equivalent to charging the voltage signals that have been pre-charged to the data line S in the previous stage and are charged in real time through the conduction of the multiplexing unit 101. Therefore, through the cooperation of the multiplexing circuit 10 in this embodiment, pre-charging of some data lines S corresponding to some sub-pixels P in two adjacent sub-pixel columns PL is achieved, and thus the actual charging time of the sub-pixels P in the sub-pixel column PL can be increased. When applicable to the display panel 000 with a high refresh rate and high resolution, at the same time, the charging time required to charge the sub-pixels P can be satisfied by pre-charging some data lines S2 with the data voltage signal Vdata, which is beneficial to improving the display quality.

[0072] Optionally, for a display panel with a refresh rate of 144 Hz and a resolution of 1236×2676, when a design of one data line for charging one sub-pixel column (SDL) is used in combination with a design without a multiplexing circuit (without demux), the time of 1H is 2.5 μs, and the actual charging time is only 1.4 μs. However, when a design of two data lines for charging one sub-pixel column (DDL) in this embodiment is used in combination with a multiplexing circuit (with demux, such as the 1:4 demux shown in this embodiment Figure 5 and Figure 6 ), the time of 1H is also 2.2 μs, and the actual charging time can be increased to at least 2.2 μs, increasing from 1.4 μs to 2.2 μs. It can be proved that the cooperative design of using the multiplexing circuit 10 and two data lines S corresponding to one sub-pixel column PL in this case can further improve the actual charging time of the sub-pixels P in the high-resolution display panel 000 and ensure the display quality.

[0073] In some alternative embodiments, please continue to refer to Figure 5 and Figure 6 . In this embodiment, the display panel 000 includes multiple first clock control signal lines 201;

[0074] Among multiple multiplexing units 101, the shunt control terminals 101C connected to the gates of the same switching transistor 101T are connected to the same first clock control signal line 201;

[0075] The number of the first clock control signal lines 201 included in the display panel 000 is equal to the number of the switching transistors 101T included in the multiplexing unit 101.

[0076] In this embodiment, it is explained that in multiple multiplexing units 101, the shunt control terminals 101C connected to the gates of the same switching transistor 101T are all connected to the same clock control signal, and this clock control signal can be provided by the same first clock control signal line 201. The first clock control signal line 201 can be connected to the bonding position of the driving chip in the peripheral area of the display panel 000, and the clock control signal is provided by the subsequently bonded driving chip. For example, for the structure of the multiplexing unit 101 including one signal input terminal 101A, four signal output terminals 101B, four shunt control terminals 101C, and four switching transistors 101T, in multiple different multiplexing units 101, the shunt control terminal 101C connected to the gate of the same first switching transistor 101T1 is connected to the same first clock control signal line 201, the shunt control terminal 101C connected to the gate of the same second switching transistor 101T2 is connected to the same first clock control signal line 201, the shunt control terminal 101C connected to the gate of the same third switching transistor 101T3 is connected to the same first clock control signal line 201, and the shunt control terminal 101C connected to the gate of the same fourth switching transistor 101T4 is connected to the same first clock control signal line 201. That is, if the multiplexing unit 101 includes four switching transistors 101T, the display panel 000 may include four first clock signal lines 201. The number of first clock control signal lines 201 included in the display panel 000 is equal to the number of switching transistors 101T included in one multiplexing unit 101, so that the shunt control terminals 101C connected to the gates of the same first switching transistor 101T1 in each different multiplexing unit 101 can all be provided with a clock control signal for driving the switching transistor 101T to conduct or cut off through the same first clock control signal line 201, so as to ensure the signal transmission stability of the multiplexing circuit 10.

[0077] In some alternative embodiments, please refer to Figure 7 and Figure 8 , Figure 7 which is another schematic plan view of the display panel provided by the embodiment of the present invention. Figure 8 It is Figure 7 a partial enlarged structural schematic view in

[0078] In this embodiment, the non-display area NA includes a plurality of first conductive pads 301;

[0079] This embodiment explains that the non-display area NA of the display panel 000 includes a plurality of first conductive pads 301. Optionally, the first conductive pads 301 can be used to transmit the driving signals provided by the driving chip to the first conductive pads 301 after the display panel 000 is subsequently bonded with the driving chip, and then transmitted to the corresponding first clock control signal lines 201 through the first conductive pads 301. In this embodiment, the same first clock control signal line 201 extends along the second direction X, and both ends of the first clock control signal line 201 are connected to the same first conductive pad 301. Optionally, both ends of the first clock control signal line 201 can be connected to the same first conductive pad 301 by wiring around the display panel 000, that is, the clock control signals are transmitted to both ends of a first clock control signal line 201 through the same first conductive pad 301, which can effectively reduce the line length of transmitting the clock control signals and reduce the load difference between the end position and the middle position of a first clock control signal line 201, which is beneficial to improving the charging uniformity.

[0080] Optionally, please refer to Figure 9 and Figure 10 , Figure 9 which is another schematic plan view of the display panel provided by the embodiment of the present invention. Figure 10 It is Figure 9 a partial enlarged structural schematic view in

[0081] This embodiment explains that the display panel 000 can also be a flexible display panel. The display panel 000 includes a bending area WA located between a first display area AA1 and a second display area AA2. The display panel 000 can form various display forms of the display panel 000 by folding at the bending area WA, such as a double-sided display effect or a display effect of only the first display area AA1 or only the second display area AA2. Optionally, the bending area WA can also be used for display, that is, the bending area WA belongs to a part of the display area. In the prior art, due to the multiple folding of the flexible display panel 000 at the bending area WA, it is easy to cause the problem of easy wire breakage at the position of the bending area WA, resulting in abnormal display. In this embodiment, the same first clock control signal line 201 is arranged to extend along the second direction X, and both ends of the first clock control signal line 201 are connected to the same first conductive pad 301. The clock control signal is transmitted to both ends of a first clock control signal line 201 through the same first conductive pad 301. Even if the first clock control signal line 201 breaks at the bending area WA due to the number of bends, it will not affect the signal transmission between the first conductive pad 301 and both ends of the first clock control signal line 201, and it can avoid the display defect caused by the wire breakage of the bending area WA after folding the bending area WA. Furthermore, when applied to a flexible display panel, it is beneficial to ensure the product yield and display effect.

[0082] Optionally, please refer to Figure 11 and Figure 12 , Figure 11 which is another schematic plan view of the display panel provided by the embodiment of the present invention. Figure 12 It is Figure 11 a partial enlarged structural schematic view in . In this embodiment, when the display panel 000 of this embodiment is in use, it can also select the display effect of only the first display area AA1 or only the second display area AA2. For example, both ends of the first clock control signal line 201 are connected to the same first conductive pad 301, and a selection switch (not shown in the figure) can be arranged on the connection path between the first conductive pad 301 and one end of the first clock control signal line 201, or both ends of a first clock control signal line 201 are connected to two different first conductive pads 301. By selecting to input the clock control signal only to one end of the first clock control signal line 201, it is possible to select to transmit the data voltage signal only to the first display area AA1 or only to the second display area AA2 of the display panel 000. Even if the first clock control signal line 201 breaks at the bending area WA due to the number of bends, it will not affect the signal transmission between a first conductive pad 301 and one end of the first clock control signal line 201. Furthermore, it is beneficial to reduce the power consumption when only a partial area of the display panel 000 needs to be displayed, and it is beneficial to save the overall power consumption of the panel.

[0083] In some alternative embodiments, please refer to Figure 13 and Figure 14 . Figure 13 is another schematic plan view of the display panel provided by the embodiments of the present invention. Figure 14 is Figure 13 a partially enlarged schematic view of the connection between the multiplexing circuit and the data line in . In this embodiment, the display panel 000 includes a first display area AA1 and a second display area AA2 arranged along the second direction X;

[0084] The display panel 000 includes a plurality of second clock control signal lines 202;

[0085] Among the plurality of multiplexing units 101, the shunt control terminals 101C connected to the gates of the same switching transistor 101T in the first display area AA1 are connected to the same second clock control signal line 202; the shunt control terminals 101C connected to the gates of the same switching transistor 101T in the second display area AA2 are connected to the same second clock control signal line 202;

[0086] The number of the second clock control signal lines 202 included in the display panel 000 is twice the number of the switching transistors 101T included in the multiplexing unit 101.

[0087] This embodiment explains that the display area of the display panel 000 may include two display regions arranged along the second direction X, namely the first display region AA1 and the second display region AA2. Among the multiple multiplexing units 101 connected to the data lines S corresponding to the first display region AA1, the shunt control terminals 101C connected to the gates of the same switching transistor 101T are all connected to the same clock control signal, and this clock control signal can be provided by the same second clock control signal line 202. The second clock control signal line 202 can be connected to the bonding position of the driving chip in the peripheral area of the display panel 000, and the driving chip provided through subsequent bonding provides this clock control signal. For example, for the structure where the multiplexing unit 101 includes a signal input terminal 101A, four signal output terminals 101B, four shunt control terminals 101C, and four switching transistors 101T, among the multiple different multiplexing units 101 corresponding to the first display region AA1, the shunt control terminal 101C connected to the gate of the same first switching transistor 101T1 is connected to the same second clock control signal line 202, the shunt control terminal 101C connected to the gate of the same second switching transistor 101T2 is connected to the same second clock control signal line 202, the shunt control terminal 101C connected to the gate of the same third switching transistor 101T3 is connected to the same second clock control signal line 202, and the shunt control terminal 101C connected to the gate of the same fourth switching transistor 101T4 is connected to the same second clock control signal line 202. And among the multiple different multiplexing units 101 corresponding to the second display region AA2, the shunt control terminal 101C connected to the gate of the same first switching transistor 101T1 is connected to the same second clock control signal line 202, the shunt control terminal 101C connected to the gate of the same second switching transistor 101T2 is connected to the same second clock control signal line 202, the shunt control terminal 101C connected to the gate of the same third switching transistor 101T3 is connected to the same second clock control signal line 202, and the shunt control terminal 101C connected to the gate of the same fourth switching transistor 101T4 is connected to the same second clock control signal line 202. That is, if the multiplexing unit 101 includes four switching transistors 101T, the display panel 000 may include eight second clock control signal lines 202. The number of second clock control signal lines 202 included in the display panel 000 is equal to twice the number of switching transistors 101T included in a multiplexing unit 101, so that the shunt control terminals 101C connected to the gates of the same first switching transistor 101T1 in each different multiplexing unit 101 corresponding to different display regions can all provide the clock control signal for driving the switching transistor 101T to conduct or cut off through the same second clock control signal line 202, so as to ensure the signal transmission stability of the multiplexing circuit 10.Moreover, it is also possible to control only the first display area AA1 to display by providing clock control signals only to the four second clock control signal lines 202 of the first display area AA1, or to control only the second display area AA2 to display by providing clock control signals only to the other four second clock control signal lines 202 of the second display area AA2. While achieving the zoned display of the display panel 000, it is also possible to independently control the display of the first display area AA1 and the second display area AA2, which is beneficial to saving the power consumption of the panel.

[0088] In some alternative embodiments, please refer to Figure 15 and Figure 16 , Figure 15 which is another schematic plan view of the display panel provided by the embodiment of the present invention. Figure 16 is Figure 15 a partial enlarged structural schematic view in

[0089] In this embodiment, the non-display area NA includes a plurality of second conductive pads 302;

[0090] The same second clock control signal line 202 extends along the second direction X, and both ends of the second clock control signal line 202 are connected to the same second conductive pad 302.

[0091] Optionally, please refer to Figure 15 , Figure 16 , 17 and Figure 18 , Figure 17 which is another schematic plan view of the display panel provided by the embodiment of the present invention. Figure 18 is Figure 17Schematic diagram of a partial enlarged structure. In this embodiment, the display panel 000 further includes a bending area WA, and the bending area WA is located between the first display area AA1 and the second display area AA2.

[0092] This embodiment explains that the display panel 000 can also be a flexible display panel. The display panel 000 includes a bending area WA located between the first display area AA1 and the second display area AA2. The display panel 000 can form various display forms of the display panel 000 by folding at the bending area WA, such as a double-sided display effect or a display effect of only the first display area AA1 or only the second display area AA2. Optionally, the bending area WA can also be used for display, that is, the bending area WA belongs to a part of the display area. In the prior art, due to the multiple folds of the flexible display panel 000 at the bending area WA, it is easy to cause the problem of easy wire breakage at the position of the bending area WA, resulting in abnormal display. In this embodiment, the same second clock control signal line 202 is arranged to extend along the second direction X, and both ends of the second clock control signal line 202 are connected to the same second conductive pad 302. The clock control signal is transmitted to both ends of a second clock control signal line 202 through the same second conductive pad 302. Even if the second clock control signal line 202 breaks at the bending area WA due to the number of bends, it will not affect the signal transmission between the second conductive pad 302 and both ends of the second clock control signal line 202, and it can avoid the display defect caused by the wire breakage in the bending area WA after folding the bending area WA. Therefore, while being applicable to a flexible display panel, it is beneficial to ensure the product yield and display effect.

[0093] And when the display panel 000 of this embodiment is in use, it can also select the display effect of only the first display area AA1 or only the second display area AA2, such as Figure 15 and Figure 16 As shown, both ends of the second clock control signal line 202 connected to the multiple multiplexing units 101 corresponding to the first display area AA1 are connected to a second conductive pad 302 (multiple second conductive pads labeled 3021 as shown in the figure), and both ends of the second clock control signal line 202 connected to the multiple multiplexing units 101 corresponding to the second display area AA2 are connected to another second conductive pad 302 (multiple second conductive pads labeled 3022 as shown in the figure). Or as Figure 17 and Figure 18As shown, one end of a second clock control signal line 202 connected to a plurality of multiplexing units 101 corresponding to the first display area AA1 is connected to a second conductive pad 302, and the other end of this second clock control signal line 202 is connected to another second conductive pad 302 (a plurality of second conductive pads labeled 3021 as shown in the figure). One end of a second clock control signal line 202 connected to a plurality of multiplexing units 101 corresponding to the second display area AA2 is connected to a second conductive pad 302, and the other end of this second clock control signal line 202 is connected to another second conductive pad 302 (a plurality of second conductive pads labeled 3022 as shown in the figure). By selecting to input a clock control signal only to four second clock control signal lines 202 corresponding to the first display area AA1, only the first display area AA1 of the display panel 000 is selected for data voltage signal transmission; or by selecting to input a clock control signal only to another four second clock control signal lines 202 corresponding to the second display area AA2, only the second display area AA2 of the display panel 000 is selected for data voltage signal transmission, thereby realizing the independent display control of the two display areas. And even if the second clock control signal line 202 breaks in the bending area WA due to the number of bends, it will not affect the signal transmission between a second conductive pad 302 and one end of the second clock control signal line 202. Furthermore, zoned display can be achieved, saving the overall power consumption of the panel.

[0094] In some alternative embodiments, please refer to Figure 19 , Figure 19 which is a schematic plan view of the display device provided by an embodiment of the present invention. The display device 111 provided in this embodiment includes the display panel 000 provided by the above embodiment of the present invention. Figure 19 This embodiment only takes a mobile phone as an example to illustrate the display device 111. It can be understood that the display device 111 provided by the embodiments of the present invention can be other display devices 111 with a display function such as a computer, a television, a vehicle-mounted display device, etc. The present invention does not make specific limitations in this regard. The display device 111 provided by the embodiments of the present invention has the beneficial effects of the display panel 000 provided by the embodiments of the present invention. For specific descriptions of the display panel 000, reference can be made to the above embodiments, and details will not be repeated in this embodiment.

[0095] As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

[0096] The display panel of the present invention charges the sub-pixels of a sub-pixel column through a multiplexing circuit in cooperation with two data lines, which is beneficial to improving the charging time. When a sub-pixel in the same sub-pixel column is controlled by a clock control signal of a multiplexing unit, the switching transistor corresponding to the clock control signal is turned on, and the data voltage signal is charged into one data line (such as the first data line). The first data line provides the data voltage signal to the corresponding sub-pixel in the sub-pixel column that has been driven and turned on by the scan driving circuit, and then the corresponding sub-pixel is driven to display. When the corresponding sub-pixel that has been driven and turned on by the scan driving circuit is displaying (that is, after the switching transistor corresponding to a clock control signal of the multiplexing unit is turned off), another clock control signal of the multiplexing unit controls the corresponding switching transistor to be turned on, and a data voltage signal is also being charged correspondingly on the other data line (such as the second data line) corresponding to the sub-pixel column. However, at this time, since the other sub-pixels in the same sub-pixel column corresponding to the second data line have not been turned on by the scan driving circuit (the scan driving circuit controls the scan lines to drive and turn on row by row), although a data voltage signal is being charged on the second data line of the sub-pixel column at this time, no driving current is generated in some of the sub-pixels connected to the second data line, and they will not emit light and display. It is equivalent to that at this time, under the control of another clock control signal of the multiplexing unit, only the second data line is pre-charged. Thus, through the cooperation of the multiplexing circuit, pre-charging of the second data line corresponding to some of the sub-pixels in the same sub-pixel column is achieved. Furthermore, the actual charging time of the sub-pixels in the sub-pixel column can be increased. It can be applied to display panels with high refresh rates and high resolutions, and at the same time, by pre-charging the data voltage signal on the second data line, the charging time required for charging the sub-pixels can be satisfied, which is beneficial to improving the display quality. Through the design of the multiplexing circuit in the non-display area, the present invention can meet the requirement of the narrow border of the display panel. At the same time, by cooperating with the design of two data lines corresponding to one sub-pixel column, the actual charging time of the sub-pixels in the display panel can also be increased, which is beneficial to ensuring the display quality of high-resolution and high-refresh-rate display panels.

[0097] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present invention. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, it includes: a plurality of sub-pixels, the plurality of sub-pixels are arranged in a first direction to form sub-pixel columns, and the plurality of sub-pixel columns are arranged in a second direction; wherein, the first direction and the second direction intersect; two data lines are included between two adjacent sub-pixel columns, and two data lines correspond to the same sub-pixel column, and are respectively a first data line and a second data line; a part of the sub-pixels in the same sub-pixel column are connected to the first data line, and the remaining part of the sub-pixels in the same sub-pixel column are connected to the second data line; the display panel includes a non-display area, the non-display area includes a multiplexing circuit, and the multiplexing circuit includes a plurality of multiplexing units; each multiplexing unit includes a signal input terminal, four signal output terminals, four shunt control terminals, and four switching transistors; the gates of the four switching transistors are respectively connected to the four shunt control terminals, the first poles of the four switching transistors are all connected to the signal input terminal, and the second poles of the four switching transistors are respectively connected to the four signal output terminals; the signal input terminal is connected to a data voltage signal, and the four signal output terminals are respectively and electrically connected to four data lines corresponding to two sub-pixel columns one by one; the display panel includes a plurality of first clock control signal lines; among the plurality of multiplexing units, the shunt control terminal to which the gate of the same switching transistor is connected is connected to the same first clock control signal line; the number of the first clock control signal lines included in the display panel is equal to the number of the switching transistors included in the multiplexing unit; the non-display area includes a plurality of first conductive pads; the same first clock control signal line extends along the second direction, and both ends of the first clock control signal line are connected to the same first conductive pad.

2. The display panel according to claim 1, characterized in that, in the same sub-pixel column, along the first direction, the A-th sub-pixel is connected to the first data line, and the (A + 1)-th sub-pixel is connected to the second data line; wherein, A is a positive integer.

3. The display panel according to claim 1, characterized in that, each multiplexing unit includes a signal input terminal and M signal output terminals, M shunt control terminals, and M switching transistors; wherein, M≥2 and M is an integer.

4. The display panel according to claim 1, characterized in that, two adjacent sub-pixel columns include a first sub-pixel column and a second sub-pixel column; in one multiplexing unit, the four signal output terminals include a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal; the four switching transistors include a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor; the four shunt control terminals include a first shunt control terminal, a second shunt control terminal, a third shunt control terminal, and a fourth shunt control terminal; The gate of the first switching transistor is connected to the first shunt control terminal, and the second pole of the first switching transistor is connected to the first signal output terminal; The gate of the second switching transistor is connected to the second shunt control terminal, and the second pole of the second switching transistor is connected to the second signal output terminal; The gate of the third switching transistor is connected to the third shunt control terminal, and the second pole of the third switching transistor is connected to the third signal output terminal; The gate of the fourth switching transistor is connected to the fourth shunt control terminal, and the second pole of the fourth switching transistor is connected to the fourth signal output terminal; The first data line of the first sub-pixel column is connected to the first signal output terminal, the second data line of the first sub-pixel column is connected to the second signal output terminal, the first data line of the second sub-pixel column is connected to the third signal output terminal, and the second data line of the second sub-pixel column is connected to the fourth signal output terminal.

5. The display panel according to claim 1, wherein, the display panel includes a first display area and a second display area arranged along the second direction; the display panel includes a plurality of second clock control signal lines; Among the plurality of multiplexing units, the shunt control terminals connected to the gates of the same switching transistor in the first display area are connected to the same second clock control signal line; the shunt control terminals connected to the gates of the same switching transistor in the second display area are connected to the same second clock control signal line; the number of the second clock control signal lines included in the display panel is twice the number of the switching transistors included in the multiplexing unit.

6. The display panel according to claim 5, wherein, the non-display area includes a plurality of second conductive pads; the same second clock control signal line extends along the second direction, and both ends of the second clock control signal line are connected to the same second conductive pad.

7. The display panel according to claim 5, wherein, the display panel includes a bending area, and the bending area is located between the first display area and the second display area.

8. A display device, comprising the display panel according to any one of claims 1-7.

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