An in-memory computing unit applied to a single-bit neural network

Abstract

The application discloses an in-memory computing unit applied to a single-bit neural network, the in-memory computing unit is composed of a storage part and a computing part, the storage part comprises tubes N1, N2, N3, N4, P1 and P2, and the computing part comprises tubes P3, P4, P5 and P6. The storage part is responsible for storing weight information, and the computing part is responsible for completing multiplication and accumulation operation of an input signal and the weight. The application has the advantages of high stability, high speed and low power consumption.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing technology, specifically to an in-memory computing unit applied to a single-bit neural network. Background Technology

[0002] Convolutional neural networks (CNNs) and deep neural networks (DNNs) have been widely applied in large-scale recognition tasks such as social networking, transportation, and healthcare. To address the issue of algorithm complexity, single-bit neural networks with binary weights, inputs, and outputs have been proposed. Traditional von Neumann architectures separate storage and computation modules, requiring frequent and large-scale data exchanges, which significantly reduces system speed and generates substantial power consumption, making them unsuitable for the requirements of artificial intelligence algorithms, including single-bit neural networks. To solve this problem, in-memory computing architectures have been proposed. SRAM-based in-memory computing architectures have achieved some success; however, in traditional in-memory computing units used in single-bit neural networks, storage nodes are directly connected via bit lines during multiplication and addition operations, potentially leading to memory data flipping and computational errors. Therefore, we propose an in-memory computing unit for single-bit neural networks to address these issues. Summary of the Invention

[0003] The purpose of this invention is to provide an in-memory computing unit for single-bit neural networks to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: an in-memory computing unit applied to a single-bit neural network, comprising a storage section composed of a 6-transistor SRAM and a computing section composed of 4 PMOS transistors. The 6-transistor SRAM includes NMOS transistors N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, PMOS transistor P1, and PMOS transistor P2; the computing section composed of 4 PMOS transistors includes PMOS transistors P3, PMOS transistor P4, PMOS transistor P5, and PMOS transistor P6.

[0005] Among them: the source of PMOS transistor P1 and the source of PMOS transistor P2 are electrically connected to the power supply; the source of NMOS transistor N3 and the source of NMOS transistor N4 are electrically connected to ground.

[0006] The drain of PMOS transistor P1 is electrically connected to the drain of NMOS transistor N3 at node Q, and the drain of PMOS transistor P2 is electrically connected to the drain of NMOS transistor N4 at node QB.

[0007] The source of NMOS transistor N1 is electrically connected to line BL, and the source of NMOS transistor N2 is electrically connected to line BLB.

[0008] The gates of NMOS transistor N1 and NMOS transistor N2 are electrically connected to line WL;

[0009] The drain of NMOS transistor N1 is electrically connected to the drain of NMOS transistor N3, and the drain of NMOS transistor N2 is electrically connected to the drain of NMOS transistor N4.

[0010] The gates of PMOS transistor P3 and PMOS transistor P6 are electrically connected to the drain of NMOS transistor N1, and the gates of PMOS transistor P4 and PMOS transistor P5 are electrically connected to the drain of NMOS transistor N2.

[0011] The source of PMOS transistor P3 is electrically connected to the source of PMOS transistor P4 at node R, and the source of PMOS transistor P5 is electrically connected to the source of PMOS transistor P6 at node RB.

[0012] The drains of PMOS transistors P3 and P5 are electrically connected to line RBL, and the drains of PMOS transistors P4 and P6 are electrically connected to line RBLB.

[0013] Line IL is electrically connected to node R, and line ILB is electrically connected to node RB.

[0014] Line WL is used to control the read / write enable of a standard 6-transistor SRAM. Lines BL and BLB are used to read and write data in the standard 6-transistor SRAM.

[0015] When node Q is high, it means that the weight stored in a standard 6-transistor SRAM cell is "1". When node Q is low, it means that the weight stored in a standard 6-transistor SRAM cell is "-1".

[0016] During multiplication and addition operations, the signals on line IL and line ILB represent the input signals, and these signals are opposite to each other. When the signal on line IL is high and the signal on line ILB is low, the input signal is "1". When the signal on line IL is low and the signal on line ILB is high, the input signal is "-1".

[0017] After the calculation is complete, the voltages of line RBL and line RBLB reflect the result of the multiplication and addition. When the voltage of line RBL is greater than the voltage of line RBLB, the result is -1. When the voltage of line RBLB is greater than the voltage of line RBL, the result is 1.

[0018] Compared with the prior art, the in-memory computing unit of the present invention, implemented according to the above technical solution, does not cause data flipping in memory when performing multiply-accumulate operations. It has the characteristics of high precision, high stability, and high speed, which can accelerate the execution of single-bit multiply-accumulate operations and improve the execution speed of single-bit neural network algorithms. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of an in-memory computing unit proposed in this invention for use in a single-bit neural network;

[0020] Figure 2 This is a schematic diagram of an in-memory computing device proposed in this invention for use in a single-bit neural network. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Example 1

[0023] like Figure 1 As shown, this invention discloses an in-memory computing unit for a single-bit neural network. The in-memory computing unit for a single-bit neural network includes a storage section consisting of a standard 6-transistor SRAM and a computing section consisting of four additional PMOS transistors.

[0024] The aforementioned standard 6-transistor SRAM storage section comprises NMOS transistors N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, PMOS transistor P1, and PMOS transistor P2, which are responsible for storage weights and read / write weights.

[0025] The additional four PMOS transistors, including PMOS transistors P3, PMOS transistor P4, PMOS transistor P5, and PMOS transistor P6, are responsible for multiplying and accumulating the external input signal with the weights.

[0026] The sources of PMOS transistors P1 and P2 are electrically connected to the power supply. The sources of NMOS transistors N3 and N4 are electrically connected to ground.

[0027] The drain of PMOS transistor P1, the gate of PMOS transistor P2, the gate of PMOS transistor P3, the gate of PMOS transistor P6, the drain of NMOS transistor N1, the drain of NMOS transistor N3, and the gate of NMOS transistor N4 are electrically connected to node Q.

[0028] The gate of PMOS transistor P1, the drain of PMOS transistor P2, the gate of PMOS transistor P4, the gate of PMOS transistor P5, the drain of NMOS transistor N2, the gate of NMOS transistor N3, and the drain of NMOS transistor N4 are electrically connected to node QB.

[0029] When node Q is high, it means the weight of the stored data is "1". When node Q is low, it means the weight of the stored data is "-1".

[0030] Line WL controls the read / write switch of the standard 6-transistor SRAM. Line WL is electrically connected to the gates of NMOS transistor N1 and NMOS transistor N2.

[0031] Lines BL and BLB are responsible for reading and writing data. Line BL is electrically connected to the source of NMOS transistor N1. Line BLB is electrically connected to the source of NMOS transistor N2.

[0032] The source of PMOS transistor P3, the source of PMOS transistor P4, and line IL are electrically connected to node R. The source of PMOS transistor P5, the source of PMOS transistor P6, and line ILB are electrically connected to node RB.

[0033] Lines RBL and RBLB are responsible for reading the results. Line RBL is electrically connected to the drain of PMOS transistor P3 and the drain of PMOS transistor P5. Line RBLB is electrically connected to the drain of PMOS transistor P4 and the drain of PMOS transistor P6.

[0034] Lines IL and ILB are responsible for the input signal. When the voltage of line IL is high and the voltage of line ILB is low, it represents an input signal of "1". When the voltage of line IL is low and the voltage of line ILB is high, it represents an input signal of "-1".

[0035] When the voltage of line IL and the voltage of line ILB are both high or both low, the calculation section is shut down and enters power-saving mode.

[0036] When the input signal is "1" and the weight is "1", PMOS transistors P4 and P5 are turned on, line RBL is pulled down, and line RBLB is pulled up. When the input signal is "1" and the weight is "-1", PMOS transistors P3 and P6 are turned on, line RBL is pulled up, and line RBLB is pulled down. When the input signal is "-1" and the weight is "1", PMOS transistors P4 and P5 are turned on, line RBL is pulled up, and line RBLB is pulled down. When the input signal is "-1" and the weight is "-1", PMOS transistors P3 and P6 are turned on, line RBL is pulled down, and line RBLB is pulled up.

[0037] After the calculation is complete, if the voltage across line RBLB is greater than the voltage across line RBL, the result is "1". If the voltage across line RBL is greater than the voltage across line RBLB, the result is "-1".

[0038] Example 2

[0039] like Figure 2 As shown, the present invention also provides an in-memory computing device suitable for single-bit neural networks. The device comprises a 3x2 array of six in-memory computing units as described in Embodiment 1 for use in single-bit neural networks, and two sensitive amplifiers.

[0040] The six embodiments described in Example 1, consisting of a 3x2 array of in-memory computing units applied to a single-bit neural network, include unit C. <1> Unit C <2> Unit C <3> Unit C <4> C <5> Unit C <6> .

[0041] In the first column, cell C <1> Unit C <3> Unit C <5> The lines BL, BLB, RBL, and RBLB correspond to line BL respectively. <1> , line BLB <1> 、Line RBL <1> , line RBLB <1> In the second column, cell C <2> Unit C <4> Unit C <6> The lines BL, BLB, RBL, and RBLB correspond to line BL respectively. <2> , line BLB <2> 、Line RBL <2> , line RBLB <2> .

[0042] In the first line, unit C <1> Unit C <2> The lines IL, ILB, and WL correspond to the line IL respectively. <1> , line ILB <1> 、line WL <1> In the second line, unit C <3> Unit C <4> The lines IL, ILB, and WL correspond to the line IL respectively. <2> , line ILB <2> 、line WL <2> In the third line, unit C <5> Unit C <6> The lines IL, ILB, and WL correspond to the line IL respectively. <3> , line ILB <3> 、line WL <3> .

[0043] Line WL <1> 、line WL <2> 、line WL <3> Control the read / write enable of the first row, second row, and third row of the array respectively.

[0044] BL (Boys' Love) <1> , line BLB <1> Used to read and write the weights of each cell in the first column of the array. (Line BL) <2> , line BLB <2> Used to read and write the weights of each cell in the second column of the array.

[0045] When performing multiplication and accumulation operations, the input signal is represented by two opposite high and low levels. When the input signal for the first row is "1", line IL... <1> High level, line ILB <1> It is low level. When the input signal of the first row is "-1", line IL <1> Low level, line ILB <1> It is high level. When the input signal of the second row is "1", line IL <2> High level, line ILB <2> It is low level. When the input signal of the second row is "-1", line IL <2> Low level, line ILB <2> It is high level. When the input signal of the third row is "1", line IL <3> High level, line ILB <3> It is low level. When the input signal of the third row is "-1", line IL <3> Low level, line ILB <3> It is a high level.

[0046] When unit C <1> When the result of the operation is "1", unit C <1> Line RBL <1> Pull down the voltage on and pull the line RBLB <1> The voltage on cell C is pulled up. <1> When the result of the operation is "-1", unit C <1> Line RBL <1> Pull up the voltage on the line RBLB <1> The voltage on cell C is pulled down. <2> When the result of the operation is "1", unit C <2> Line RBL <2> Pull down the voltage on and pull the line RBLB <2> The voltage on cell C is pulled up. <2> When the result of the operation is "-1", unit C <2> Line RBL <2> Pull up the voltage on the line RBLB <2> The voltage on cell C is pulled down. <3> When the result of the operation is "1", unit C <3> Line RBL <1> Pull down the voltage on and pull the line RBLB <1> The voltage on cell C is pulled up. <3> When the result of the operation is "-1", unit C <3> Line RBL <1> Pull up the voltage on the line RBLB <1> The voltage on cell C is pulled down. <4> When the result of the operation is "1", unit C <4> Line RBL <2> Pull down the voltage on and pull the line RBLB <2> The voltage on cell C is pulled up. <4> When the result of the operation is "-1", unit C <4> Line RBL <2> Pull up the voltage on the line RBLB <2> The voltage on cell C is pulled down. <5> When the result of the operation is "1", unit C <5> Line RBL <1> Pull down the voltage on and pull the line RBLB <1> The voltage on cell C is pulled up. <5> When the result of the operation is "-1", unit C <5> Line RBL <1> Pull up the voltage on the line RBLB <1> The voltage on cell C is pulled down. <6> When the result of the operation is "1", unit C <6> Line RBL <2> Pull down the voltage on and pull the line RBLB <2> The voltage on cell C is pulled up. <6> When the result of the operation is "-1", unit C <6> Line RBL <2> Pull up the voltage on the line RBLB <2> Pull down the voltage on it.

[0047] After the operation is completed, line RBL <1> Voltage on line RBLB <1> The magnitude of the voltage on the line represents the result of the first column's calculation. When line RBL... <1> The voltage on line RBLB is greater than the voltage on line RBLB. <1> When the voltage is applied, the result of the calculation in the first column is "-1", and when the line RBL is applied... <1> The voltage on line RBLB is less than <1> When the voltage is applied, the result of the operation in the first column is "1". After the operation is completed, line RBL... <2> Voltage on line RBLB <2> The magnitude of the voltage on the line represents the result of the second column's calculation. When line RBL <2> The voltage on line RBLB is greater than the voltage on line RBLB. <2> When the voltage is applied, the result of the calculation in the second column is "-1". When line RBL... <2> The voltage on line RBLB is less than <2> When the voltage is applied, the result of the operation in the second column is "1".

[0048] The two sensitive amplifiers mentioned above have output lines OUT and OUT respectively. <1> OUT line <2> OUT line <1> OUT line <2> The voltage on the line represents the calculation result. When the calculation result of the first column is "1", line OUT... <1> The voltage is high. When the result of the first column is "-1", line OUT... <1> The voltage is low. When the result of the second column is "1", line OUT... <1> The voltage is high. When the result of the second column is "-1", line OUT... <1> The voltage is low.

[0049] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An in-memory computing unit for a single-bit neural network, comprising a storage section consisting of a 6-transistor SRAM and a computing section consisting of 4 PMOS transistors, characterized in that: The aforementioned 6-transistor SRAM includes NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, PMOS transistor P1, and PMOS transistor P2; The computing section consisting of the four PMOS transistors includes PMOS transistors P3, PMOS transistor P4, PMOS transistor P5, and PMOS transistor P6. Among them: the source of PMOS transistor P1 and the source of PMOS transistor P2 are electrically connected to the power supply; the source of NMOS transistor N3 and the source of NMOS transistor N4 are electrically connected to ground. The drain of PMOS transistor P1 is electrically connected to the drain of NMOS transistor N3 at node Q, and the drain of PMOS transistor P2 is electrically connected to the drain of NMOS transistor N4 at node QB. The source of NMOS transistor N1 is electrically connected to line BL, and the source of NMOS transistor N2 is electrically connected to line BLB. The gates of NMOS transistor N1 and NMOS transistor N2 are electrically connected to line WL; The drain of NMOS transistor N1 is electrically connected to the drain of NMOS transistor N3, and the drain of NMOS transistor N2 is electrically connected to the drain of NMOS transistor N4. The gates of PMOS transistor P3 and PMOS transistor P6 are electrically connected to the drain of NMOS transistor N1, and the gates of PMOS transistor P4 and PMOS transistor P5 are electrically connected to the drain of NMOS transistor N2. The source of PMOS transistor P3 is electrically connected to the source of PMOS transistor P4 at node R, and the source of PMOS transistor P5 is electrically connected to the source of PMOS transistor P6 at node RB. The drains of PMOS transistors P3 and P5 are electrically connected to line RBL, and the drains of PMOS transistors P4 and P6 are electrically connected to line RBLB. Line IL is electrically connected to node R, and line ILB is electrically connected to node RB; The drain of PMOS transistor P1, the gate of PMOS transistor P2, the gate of PMOS transistor P3, the gate of PMOS transistor P6, the drain of NMOS transistor N1, the drain of NMOS transistor N3, and the gate of NMOS transistor N4 are electrically connected to node Q. The gate of PMOS transistor P1, the drain of PMOS transistor P2, the gate of PMOS transistor P4, the gate of PMOS transistor P5, the drain of NMOS transistor N2, the gate of NMOS transistor N3, and the drain of NMOS transistor N4 are electrically connected to node QB.

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