A semiconductor structure and a method of forming the same

Abstract

Embodiments of the present application disclose a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps: providing a first substrate; etching a groove on a back surface of the first substrate; forming a conductive layer in the groove; forming a first conductive column extending into the groove on the back surface of the first substrate; forming a device layer on a front surface of the first substrate, the device layer comprising a memory array and a contact structure; forming a second conductive column extending into the first substrate through the device layer; and electrically connecting the second conductive column and the first conductive column through the conductive layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink, and the interconnection density of devices continues to increase. In order to achieve high density of devices, obtain better performance and lower overall cost, technicians have developed a series of advanced packaging technologies. Among them, three-dimensional packaging technology has good electrical performance and high reliability, while being able to achieve high packaging density. It is widely used in various high-speed circuits and miniaturized systems. Through Silicon Via (TSV) technology is a new technology for interconnecting stacked chips in three-dimensional integrated circuits. Electrical interconnection between different chips is achieved by making many vertically interconnected TSV structures on silicon wafers. TSV technology can maximize the density of chip stacking in the three-dimensional direction, minimize the interconnection lines between chips, and minimize the overall size. It also greatly improves the chip speed and low power consumption performance. It is one of the most eye-catching technologies in current electronic packaging technology.

[0003] However, since the TSV structure has a large aspect ratio, any problem in the etching process, filling process, and alignment process will cause the TSV structure to fail. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a semiconductor structure and a method for forming the same in order to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of the embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a method for forming a semiconductor structure, the method comprising:

[0007] providing a first substrate;

[0008] Etching a groove on the back side of the first substrate;

[0009] forming a conductive layer in the trench;

[0010] forming a first conductive pillar extending into the trench on the back side of the first substrate;

[0011] forming a device layer on the front surface of the first substrate, wherein the device layer includes a memory array and a contact structure;

[0012] forming a second conductive pillar penetrating the device layer and extending into the first substrate;

[0013] The second conductive pillar and the first conductive pillar are electrically connected through the conductive layer.

[0014] In some embodiments, the step of forming a conductive layer in the trench includes:

[0015] depositing a first insulating layer, a first diffusion barrier layer, and a copper thin film layer in sequence in the trench;

[0016] The copper film layer located at the bottom of the trench constitutes the conductive layer.

[0017] In some embodiments, the step of forming a first conductive pillar extending into the trench on the back side of the first substrate includes:

[0018] depositing a second diffusion barrier layer in the trench, wherein the second diffusion barrier layer covers the copper thin film layer;

[0019] filling the trench with an insulating material to form an insulating filling layer, wherein the insulating filling layer covers the second diffusion barrier layer;

[0020] Etching the insulating filling layer and the second diffusion barrier layer to form a first blind hole, wherein the first blind hole exposes a portion of the conductive layer;

[0021] depositing a third diffusion barrier layer in the first blind hole, wherein the third diffusion barrier layer covers the sidewall of the first blind hole and the exposed portion of the conductive layer;

[0022] The first blind hole is filled with a first metal material, and the first metal material covers the third diffusion barrier layer.

[0023] In some embodiments, before the step of forming the first blind hole, the method further comprises:

[0024] A first photomask layer is formed on the surface of the insulating filling layer, and the insulating filling layer and the second diffusion barrier layer are etched using the patterned first photomask layer as a mask to form the first blind hole.

[0025] In some embodiments, an opening size of the groove is larger than an opening size of the first blind hole.

[0026] In some embodiments, after filling the first blind hole with the first metal material, the method further includes:

[0027] A chemical mechanical polishing process is performed on the back surface of the first substrate to make the top surface of the first conductive pillar flush with the top surface of the substrate.

[0028] In some embodiments, the step of forming a second conductive pillar penetrating the device layer and extending into the first substrate includes:

[0029] Etching to form a second blind hole penetrating the device layer and extending into the first substrate, wherein the second blind hole exposes a portion of the conductive layer;

[0030] depositing a second insulating layer in the second blind hole, and etching away the second insulating layer at the bottom of the second blind hole;

[0031] A fourth diffusion barrier layer is deposited in the second blind hole and filled with a second metal material.

[0032] In some embodiments, before the step of forming the second blind hole, the method further comprises:

[0033] A second photomask layer is formed on the surface of the device layer, and the device layer and the first substrate are etched using the patterned second photomask layer as a mask to form the second blind hole.

[0034] In some embodiments, the method further comprises:

[0035] A chemical mechanical polishing process is performed on the front surface of the first substrate to make the top surface of the device layer flush with the top surface of the second conductive pillar.

[0036] In some embodiments, the method further comprises:

[0037] forming an interconnection layer on the device layer, wherein the interconnection layer is electrically connected to the second conductive pillar;

[0038] Wherein, the interconnection layer includes interconnection vias and interconnection metal layers.

[0039] In some embodiments, the method further comprises:

[0040] Providing a bonding structure, the bonding structure comprising a second substrate and an interconnection layer formed on the second substrate; wherein the interconnection layer comprises an interconnection via and an interconnection metal layer;

[0041] The interconnect layer is bonded to the device layer.

[0042] In some embodiments, the interconnect layer is electrically connected to the second conductive pillar.

[0043] In a second aspect, an embodiment of the present application provides a semiconductor structure, comprising: a substrate; a device layer, wherein the device layer is located on a front surface of the substrate;

[0044] A through silicon via (TSV) is provided inside the substrate and penetrates the substrate and the device layer.

[0045] In some embodiments, the device layer includes a memory array and a contact structure.

[0046] In some embodiments, the through silicon via comprises:

[0047] a first conductive pillar, the first conductive pillar extending from the back side of the substrate toward the inside of the substrate;

[0048] a second conductive pillar, the second conductive pillar penetrating the device layer and extending from the front surface of the substrate toward the interior of the substrate;

[0049] A conductive layer, wherein the first conductive pillar and the second conductive pillar are electrically connected through the conductive layer.

[0050] In some embodiments, the through silicon via further includes a trench structure, wherein the trench structure extends from the back side of the substrate toward the interior of the substrate and does not penetrate the substrate.

[0051] In some embodiments, the trench structure includes: a first insulating layer, a first diffusion barrier layer, a copper film layer, a second diffusion barrier layer, and an insulating filling layer; wherein the copper film layer located at the bottom of the trench structure constitutes the conductive layer.

[0052] In some embodiments, the first conductive pillar penetrates the insulating filling layer and the second diffusion barrier layer and is electrically connected to the conductive layer.

[0053] In some embodiments, the second conductive pillar penetrates the first insulating layer and the first diffusion barrier layer and is electrically connected to the conductive layer.

[0054] In the technical solution provided in this application, a trench is first formed on the back side of a first substrate, a first conductive pillar is formed within the trench, and then, after the device layer is formed, a second conductive pillar is formed on the front side of the first substrate. The first and second conductive pillars are electrically connected through the conductive layer within the trench to form a through-silicon via structure. This increases the process window and reduces the difficulty of etching and aligning the first and second conductive pillars. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0056] Figure 1 A schematic diagram of a process for implementing a TSV structure formation method provided in an embodiment of the present application;

[0057] Figures 2a to 2n A partial cross-sectional schematic diagram of a TSV structure forming process according to an embodiment of the present application;

[0058] Figure 3 A schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0060] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0061] In addition, the accompanying drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0062] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to actual circumstances.

[0063] It should be understood that spatial relational terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relational terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "beneath" or "beneath" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0064] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0065] The present invention provides a method for forming a semiconductor structure. Figure 1 A schematic diagram of a process flow for implementing a method for forming a semiconductor structure provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method mainly includes the following steps:

[0066] Step 110: Provide a first substrate.

[0067] Step 120: Etching to form a trench on the back side of the first substrate; and forming a conductive layer in the trench.

[0068] In an embodiment of the present application, a first substrate is provided, wherein the first substrate may be a semiconductor substrate, and the semiconductor substrate may be a single-element semiconductor material substrate (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (for example, a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0069] In the embodiment of the present application, before step 120, the back side of the first substrate may be subjected to a chemical mechanical polishing (CMP) process to thin the first substrate, for example, to grind the first substrate to a thickness of 50-70 μm. In actual applications, the thickness of the first substrate may be adjusted according to actual needs.

[0070] In an embodiment of the present application, a first insulating layer, a first diffusion barrier layer, and a copper thin film layer are sequentially deposited in the groove; the copper thin film layer located at the bottom of the groove constitutes the conductive layer; a second diffusion barrier layer is deposited in the groove, and the second diffusion barrier layer covers the copper thin film layer; an insulating material is filled in the groove to form an insulating filling layer, and the insulating filling layer covers the second diffusion barrier layer.

[0071] Figures 2a to 2n This is a partial cross-sectional diagram of the formation process of the semiconductor structure of an embodiment of the present application. Figure 1 and Figures 2a to 2n A method for forming a semiconductor structure according to an embodiment of the present application is described.

[0072] In the embodiments of this application, Figure 2a As shown, a photoresist layer 202 is formed on the back side of a first substrate 201. The photoresist layer 202 is exposed and developed to obtain a patterned photoresist layer 202. The patterned photoresist layer 202 has a first opening 203. In a specific embodiment, the first opening can be a circular opening with a diameter of 10-30 μm. It should be noted that the first opening can also be an opening of other shapes, such as an elliptical opening, a square opening, etc., and this application is not limited to this.

[0073] The first substrate 201 is etched using the patterned photoresist layer 202 as a mask to form a groove 204. After the groove 204 is formed, the photoresist layer 202 is removed, and the structure formed is as shown in FIG. Figure 2b As shown. In some embodiments, after removing the patterned photoresist layer 202, the formed structure can also be cleaned to remove etching residues. In practical applications, the first substrate can be etched using a dry etching process. In a specific embodiment, the etching depth of the groove 204 can be 30-50 μm. In practical applications, the groove etching depth can be adjusted according to actual needs.

[0074] In an embodiment of the present application, the depth of the groove is equal to half the thickness of the first substrate.

[0075] A first insulating layer 205, a first diffusion barrier layer 206, and a copper thin film layer 207 are sequentially deposited within the trench. The copper thin film layer at the bottom of the trench constitutes the conductive layer 2071. In one embodiment, the thickness of the conductive layer 2071 may be 700 nm to 1000 nm. In practical applications, the thickness of the conductive layer can be adjusted according to actual needs.

[0076] In one embodiment, an atomic layer deposition (ALD) process may be used to form a first insulating layer 205 in the trench, wherein the material of the first insulating layer 205 includes but is not limited to at least one of SiO2, Si3N4, and a low dielectric constant material; a physical vapor deposition (PVD) process may be used to form a first diffusion barrier layer 206 on the first insulating layer 205, wherein the material of the first diffusion barrier layer 206 includes but is not limited to at least one of TaN, Ta, ZrN, and Cu; and an electroplating process may be used to form a copper thin film layer 207 on top of the first diffusion barrier layer 206.

[0077] In some embodiments, when forming the copper thin film layer 207, the deposition rate can be controlled by adding an accelerator and an inhibitor during the electroplating process, so that the copper thin film layer 207 is formed at the bottom and top of the trench, while only a small amount of copper thin film is deposited on the sidewalls of the trench. In one specific example, the accelerator can be polyalkylene glycol, and the inhibitor can be an organic sulfide. In some embodiments, the copper thin film layer deposited on the sidewalls of the trench can also be removed by dry etching, leaving only the copper thin film layer at the bottom and top of the trench.

[0078] After the above deposition, the structure formed is as follows Figure 2c shown.

[0079] A second diffusion barrier layer 208 is deposited in the trench, and an insulating material is filled in the trench to form an insulating filling layer 209. The structure formed is as follows: Figure 2d In some embodiments, an ALD process is used to deposit a second diffusion barrier layer, where the material of the second diffusion barrier layer includes, but is not limited to, at least one of SiN, TaN, and TiO2. A chemical vapor deposition (CVD) process is used to form an insulating fill layer within the trench, where the material of the insulating fill layer includes, but is not limited to, at least one of SiO2, Si3N4, and a low-k dielectric constant material.

[0080] Here, the trench structure includes: a first insulating layer 205 , a first diffusion barrier layer 206 , a copper film layer 207 , a second diffusion barrier layer 208 and an insulating filling layer 209 ; wherein the copper film layer at the bottom of the trench constitutes the conductive layer 2071 .

[0081] Here, the first insulating layer 205 and the insulating filling layer 209 may be made of the same material.

[0082] Step 130 : forming a first conductive pillar on the back side of the first substrate and extending into the trench.

[0083] like Figure 2e As shown, a patterned first photomask layer 210 is formed, and the patterned first photomask layer 210 has a second opening 211. In one embodiment, the second opening can be a circular opening with a diameter of 7 μm to 10 μm. It should be noted that the second opening can also be an opening of other shapes, such as an elliptical opening or a square opening, and this application is not limited thereto.

[0084] The insulating filling layer 209 and the second diffusion barrier layer 208 are etched using the patterned first photomask layer 210 containing the second opening as a mask to form a first blind hole 212. After the first blind hole 212 is formed, the patterned first photomask layer 210 is removed, and the structure formed is as shown in FIG. Figure 2f Here, the first blind via 212 exposes a portion of the conductive layer 2071. When etching to form the first blind via 212, the conductive layer 2071 can be used as an etch stop layer. By controlling the etching selectivity, the etching of the first blind via is stopped on the copper thin film layer 207, so that the first blind via penetrates the insulating filling layer 209 and the second diffusion barrier layer 208, exposing a portion of the conductive layer 2071.

[0085] like Figure 2g As shown, a third diffusion barrier layer 213 is deposited in the first blind hole 212, covering the sidewalls of the first blind hole 212 and the exposed portion of the conductive layer 2071. A first metal material 214 is filled in the first blind hole, covering the third diffusion barrier layer 213. In some embodiments, the third diffusion barrier layer 213 is deposited in the first blind hole using a PVD process, where the material of the third diffusion barrier layer includes, but is not limited to, at least one of TaN, Ta, ZrN, and Cu. The first metal material 214 is filled in the first blind hole using an electroplating process, where the first metal material includes, but is not limited to, at least one of copper and tungsten.

[0086] Here, the third diffusion barrier layer 213 and the first diffusion barrier layer 206 may be made of the same material. The first metal material 214 and the copper thin film layer 207 may be made of the same material.

[0087] like Figure 2g As shown, a chemical mechanical polishing process is performed on the back side of the first substrate to make the top surface of the first conductive column flush with the top surface of the substrate, and the structure formed is as shown Figure 2h Here, the first substrate can also be thinned from the back side of the first substrate by the above-mentioned chemical mechanical polishing process, and the thickness of the first substrate can be polished to 40-60 μm. In actual application, the thinning thickness of the first substrate can be adjusted according to actual needs.

[0088] Combine Figures 2a to 2h , that is, a first conductive column 215 extending into the first substrate 201 is formed on the back side of the first substrate 201 , and the first conductive column 215 is formed in the trench structure and electrically connected to the conductive layer 2071 at the bottom of the trench.

[0089] like Figure 2h As shown, the third diffusion barrier layer 213 in the first conductive column 215 contacts the conductive layer 2071 through the opening of the second diffusion barrier layer 208 at the bottom of the trench, so that the first metal material 214 filled in the first conductive column 215 is electrically connected to the conductive layer 2071 through the third diffusion barrier layer 213.

[0090] Step 140: forming a device layer on the front surface of the first substrate, wherein the device layer includes a storage array and a contact structure.

[0091] like Figure 2i As shown, Figure 2h The structure shown is flipped so that the front side of the first substrate 201 faces upward.

[0092] like Figure 2j As shown, a device layer 216 is formed on the front surface of the first substrate 201. The device layer 216 includes a memory array 217 and a contact structure 218. The memory array 217 may include structures such as active areas, word lines, bit lines, and capacitors. The contact structure 218 may include a conductive contact structure and a metal layer formed on the memory array 217. The contact structure 218 is used to electrically connect the memory array. For example, the contact structure 218 can be used to control signal transmission of one or more sources and / or drains in the active area and structures such as word lines and bit lines. In this embodiment, the contact structure 218 is formed in the insulating layer.

[0093] In a specific example, the contact structure 218 may include a peripheral contact structure formed on the memory array 217, a metal layer electrically connected to the peripheral contact structure, and a conductive contact structure electrically connected to the metal layer, wherein the metal layer is located between the peripheral contact structure and the conductive contact structure.

[0094] Step 150: forming a second conductive pillar penetrating the device layer and extending into the first substrate; the second conductive pillar and the first conductive pillar are electrically connected through the conductive layer.

[0095] In the embodiments of this application, Figure 2kAs shown, a patterned second photomask layer 219 is formed, and the patterned second photomask layer 219 has a third opening 220. In one embodiment, the third opening can be a circular opening with a diameter of 7 μm. It should be noted that the third opening can also be an opening of other shapes, such as an elliptical opening or a square opening, and this application is not limited to this.

[0096] like Figure 2l As shown, the device layer 216 and the first substrate 201 are etched using a patterned second photomask layer 219 containing a third opening as a mask to form a second blind hole 221. After the second blind hole 221 is formed, the patterned second photomask layer 219 is removed, and the second blind hole 221 exposes a portion of the conductive layer 2071. The conductive layer 2071 is used as an etch stop layer to form the second blind hole 221. By controlling the etching selectivity, the second blind hole penetrates the device layer 216, the first insulating layer 205, and the first diffusion barrier layer 206, and exposes a portion of the conductive layer 2071.

[0097] In some embodiments, the opening size of the first blind hole is the same as or different from the opening size of the second blind hole, as long as the opening size of the first blind hole and the opening size of the second blind hole are smaller than the width of the conductive layer 2071 (along the horizontal direction of the first substrate).

[0098] like Figure 2m As shown, a second insulating layer 222 is deposited in the second blind hole 221, and the second insulating layer 222 at the bottom of the second blind hole is removed by etching. A fourth diffusion barrier layer 223 is deposited in the second blind hole and filled with a second metal material 224 to form a second conductive pillar 225. Here, an ALD process is used to deposit the second insulating layer in the trench. The material of the second insulating layer includes, but is not limited to, at least one of SiO2, Si3N4, and a low-k dielectric constant material. A PVD process is used to deposit the fourth diffusion barrier layer on the second insulating layer. The material of the fourth diffusion barrier layer includes, but is not limited to, at least one of TaN, Ta, ZrN, and Cu. An electroplating process is used to fill the first blind hole with a second metal material. The second metal material includes, but is not limited to, at least one of copper and tungsten.

[0099] Here, the second insulating layer 222 and the first insulating layer 205 may be made of the same material. The fourth diffusion barrier layer 223 and the third diffusion barrier layer 213 may be made of the same material. The second metal material 224 and the first metal material 214 may be made of the same material.

[0100] In an embodiment of the present application, the fourth diffusion barrier layer 223 in the second conductive column 225 contacts the conductive layer 2071 through the opening of the second insulating layer 222 at the bottom of the second blind hole, so that the second metal material 224 filled in the second conductive column 225 is electrically connected to the conductive layer 2071 through the fourth diffusion barrier layer 223.

[0101] In the embodiment of the present application, the second conductive pillar 225 and the first conductive pillar 215 are electrically connected through the conductive layer 2071 at the bottom of the trench.

[0102] right Figure 2m The structure shown in FIG. 1 is subjected to a chemical mechanical polishing process to planarize the second conductive pillar from the front side of the first substrate 201 so that the top surface of the second conductive pillar 225 is flush with the top surface of the device layer 216, and the formed silicon through hole structure is as shown in FIG. Figure 2n shown.

[0103] like Figure 2n As shown, the TSV structure includes a first conductive pillar 215 , a second conductive pillar 225 and a conductive layer 2071 that are electrically connected. The TSV structure is in a “cross” shape. The widths of the first conductive pillar 215 and the second conductive pillar 225 decrease in a direction perpendicular to and toward the conductive layer 2071 .

[0104] Thus, in the embodiment of the present application, a first conductive pillar 215 is formed in the trench structure, and the first conductive pillar 215 and the second conductive pillar 225 are electrically connected via the conductive layer 2071. In a direction parallel to the substrate, because the width of the conductive layer 2071 is greater than the width of the contact surface between the first and second conductive pillars 215, 225 and the conductive layer 2071, when the second conductive pillar 225 is formed on the front surface of the first substrate, it only needs to contact the conductive layer 2071. In other words, the projections of the first and second conductive pillars 215, 225 on the conductive layer 2071 do not need to completely overlap. This increases the process window for the second conductive pillar, reduces the difficulty of aligning the first and second conductive pillars, and increases the contact area between the first and second conductive pillars, thereby reducing the resistance of the through-silicon via and improving the conductivity of the through-silicon via.

[0105] In some embodiments, after step 140, the method further includes forming an interconnect layer on the device layer, the interconnect layer being electrically connected to the second conductive pillar; wherein the interconnect layer includes interconnect vias and an interconnect metal layer. In practical applications, multiple stacked interconnect layers may be formed on the device layer. Based on the stacking order of the interconnect layers, the interconnect layer closest to the device layer may be referred to as the first interconnect layer, the interconnect layer above the first interconnect layer may be referred to as the second interconnect layer, and so on.

[0106] In other embodiments, after step 140, the method further includes: providing a bonding structure, the bonding structure including a second substrate and an interconnection layer formed on the second substrate; wherein the interconnection layer includes interconnection vias and an interconnection metal layer; and bonding the interconnection layer to the device layer. Here, the interconnection layer is electrically connected to the second conductive pillar. In practical applications, multiple stacked interconnection layers can be formed on the second substrate. During bonding, the topmost interconnection layer is bonded to the device layer. Based on the stacking order of the interconnection layers, the interconnection layer closest to the device layer can be referred to as the first interconnection layer, the interconnection layer above the first interconnection layer can be referred to as the second interconnection layer, and so on.

[0107] In the embodiment of the present application, the interconnection through-hole in the interconnection layer is electrically connected to the second conductive pillar.

[0108] In the embodiment of the present application, the device layer and the interconnection layer are formed on different substrates. In this way, the processes of the device layer and the interconnection layer can be carried out simultaneously, thereby effectively shortening the manufacturing time of the memory chip.

[0109] A semiconductor structure is also provided in an embodiment of the present application, comprising: a substrate; a device layer, wherein the device layer is located on the front side of the substrate; and a through-silicon via, wherein the through-silicon via is arranged inside the substrate and passes through the substrate and the device layer. Figure 3 The semiconductor structure provided by the embodiment of the present application is shown; Figure 3 As shown, the semiconductor structure includes: a substrate 310; a device layer 320, wherein the device layer 320 is located on the front side of the semiconductor substrate 310;

[0110] A through silicon via (TSV) is provided inside the substrate and penetrates the substrate 310 and the device layer 320 .

[0111] In the embodiment of the present application, the device layer 320 includes a storage array 321 and a contact structure 322 .

[0112] In an embodiment of the present application, the silicon through hole includes: a first conductive column 331, the first conductive column 331 extends from the back side of the substrate to the inside of the substrate; a second conductive column 331, the second conductive column 331 passes through the device layer 320 and extends from the front side of the substrate to the inside of the substrate; a conductive layer 3333, the first conductive column 331 and the second conductive column 332 are electrically connected through the conductive layer 3333.

[0113] In the embodiment of the present application, the through silicon via further includes a trench structure 333 , which extends from the back side of the substrate toward the inside of the substrate and does not penetrate the substrate 310 .

[0114] In an embodiment of the present application, the trench structure includes: a first insulating layer 3331, a first diffusion barrier layer 3332, a copper film layer, a second diffusion barrier layer 3334 and an insulating filling layer 3335; wherein the copper film layer located at the bottom of the trench structure 333 constitutes the conductive layer 3333.

[0115] It should be noted that when forming the copper film layer, the copper film layer may be formed only at the bottom of the trench without forming the copper film layer on the sidewall of the trench. In this case, the copper film layer in the trench is the conductive layer.

[0116] In the embodiment of the present application, the first conductive pillar 331 penetrates the insulating filling layer 3335 and the second diffusion barrier layer 3334 and is electrically connected to the conductive layer 3333 .

[0117] In the embodiment of the present application, the second conductive pillar 332 passes through the first insulating dielectric layer 3331 and the first diffusion barrier layer 3332 , and is electrically connected to the conductive layer 3333 .

[0118] In the embodiments of the present application, a first conductive pillar is formed in a trench structure, and the first and second conductive pillars are electrically connected via a conductive layer in the trench structure. In a direction parallel to the substrate, because the width of the conductive layer is greater than the width of the contact surface between the first and second conductive pillars and the conductive layer, when the second conductive pillar is formed on the front surface of the first substrate, it only needs to be aligned with the conductive layer. In other words, the projections of the first and second conductive pillars on the conductive layer do not need to completely overlap. This increases the process window for the second conductive pillar, reduces the difficulty of aligning the first and second conductive pillars, and increases the contact area between the first and second conductive pillars, thereby reducing the resistance of the through-silicon via and improving the conductivity of the through-silicon via.

[0119] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

[0120] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0121] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0122] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0123] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0124] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: The method comprises: providing a first substrate; Etching a trench on the back side of the first substrate, wherein the trench structure includes: a first insulating layer, a first diffusion barrier layer, a copper film layer, a second diffusion barrier layer and an insulating filling layer; forming a conductive layer in the trench; forming a first conductive pillar extending into the trench on the back side of the first substrate; forming a device layer on the front surface of the first substrate, wherein the device layer includes a memory array and a contact structure; forming a second conductive pillar penetrating the device layer and extending into the first substrate; The first conductive pillar and the second conductive pillar are electrically connected through the conductive layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a conductive layer in the trench comprises: depositing a first insulating layer, a first diffusion barrier layer, and a copper thin film layer in sequence in the trench; The copper film layer located at the bottom of the trench constitutes the conductive layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The step of forming a first conductive pillar extending into the trench on the back side of the first substrate includes: depositing a second diffusion barrier layer in the trench, wherein the second diffusion barrier layer covers the copper thin film layer; filling the trench with an insulating material to form an insulating filling layer, wherein the insulating filling layer covers the second diffusion barrier layer; Etching the insulating filling layer and the second diffusion barrier layer to form a first blind hole, wherein the first blind hole exposes a portion of the conductive layer; depositing a third diffusion barrier layer in the first blind hole, wherein the third diffusion barrier layer covers the sidewall of the first blind hole and the exposed portion of the conductive layer; The first blind hole is filled with a first metal material, and the first metal material covers the third diffusion barrier layer.

4. The method for forming a semiconductor structure according to claim 3, wherein before the step of forming the first blind hole, The method further comprises: A first photomask layer is formed on the surface of the insulating filling layer, and the insulating filling layer and the second diffusion barrier layer are etched using the patterned first photomask layer as a mask to form the first blind hole.

5. The method for forming a semiconductor structure according to claim 3, wherein: The opening size of the groove is larger than the opening size of the first blind hole.

6. The method for forming a semiconductor structure according to claim 3, wherein: After filling the first blind hole with the first metal material, the method further includes: A chemical mechanical polishing process is performed on the back surface of the first substrate to make the top surface of the first conductive pillar flush with the top surface of the substrate.

7. The method for forming a semiconductor structure according to claim 3, wherein: The step of forming a second conductive pillar penetrating the device layer and extending into the first substrate comprises: Etching to form a second blind hole penetrating the device layer and extending into the first substrate, wherein the second blind hole exposes a portion of the conductive layer; depositing a second insulating layer in the second blind hole, and etching away the second insulating layer at the bottom of the second blind hole; A fourth diffusion barrier layer is deposited in the second blind hole and filled with a second metal material.

8. The method for forming a semiconductor structure according to claim 7, wherein before the step of forming the second blind hole, The method further comprises: A second photomask layer is formed on the surface of the device layer, and the device layer and the first substrate are etched using the patterned second photomask layer as a mask to form the second blind hole.

9. The method for forming a semiconductor structure according to claim 7, wherein: The method further comprises: A chemical mechanical polishing process is performed on the front surface of the first substrate to make the top surface of the device layer flush with the top surface of the second conductive pillar.

10. The method for forming a semiconductor structure according to claim 7, wherein: The method further comprises: forming an interconnection layer on the device layer, wherein the interconnection layer is electrically connected to the second conductive pillar; Wherein, the interconnection layer includes interconnection vias and interconnection metal layers.

11. The method for forming a semiconductor structure according to claim 7, wherein: The method further comprises: providing a bonding structure comprising a second substrate and an interconnection layer formed on the second substrate; Wherein, the interconnection layer includes interconnection vias and interconnection metal layers; The interconnect layer is bonded to the device layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The interconnection layer is electrically connected to the second conductive pillar.

13. A semiconductor structure, characterized in that include: substrate; a device layer, the device layer being located on the front side of the substrate; a through silicon via, the through silicon via being arranged inside the substrate and penetrating the substrate and the device layer; Wherein, the through silicon via comprises: a first conductive pillar, the first conductive pillar extending from the back side of the substrate toward the inside of the substrate; a second conductive pillar, the second conductive pillar penetrating the device layer and extending from the front surface of the substrate toward the interior of the substrate; a conductive layer, wherein the first conductive pillar and the second conductive pillar are electrically connected via the conductive layer; A trench structure extending from the back side of the substrate toward the inside of the substrate without penetrating the substrate; the trench structure comprising: a first insulating layer, a first diffusion barrier layer, a copper film layer, a second diffusion barrier layer, and an insulating filling layer; Wherein, the copper film layer located at the bottom of the trench structure constitutes the conductive layer.

14. The semiconductor structure according to claim 13, wherein: The device layer includes a storage array and a contact structure.

15. The semiconductor structure according to claim 13, wherein: The first conductive column penetrates the insulating filling layer and the second diffusion barrier layer and is electrically connected to the conductive layer.

16. The semiconductor structure according to claim 15, wherein: The second conductive pillar penetrates the first insulating layer and the first diffusion barrier layer and is electrically connected to the conductive layer.

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