Driving circuit, dual active bridge conversion circuit, circuit working method and electronic device

Abstract

The present disclosure relates to the field of integrated circuit technology, and specifically to a driving circuit, a dual active bridge conversion circuit, a circuit working method and an electronic device, wherein the driving circuit comprises: a first power device, a second power device, a first sub-driving circuit, a second sub-driving circuit and a feedforward circuit; wherein the first sub-driving circuit is used to drive the first power device, and the second sub-driving circuit is used to drive the second power device; and the feedforward circuit is used to provide a charging and discharging path when the first power device and the second power device are turned off. The technical solution of the present disclosure, by respectively providing independent driving circuits for the first power device and the second power device, and adding a feedforward circuit, greatly reduces the series current while reducing the turn-on delay time, avoids the false start of the power device caused by large noise on the power line or the ground line, reduces the power consumption of the circuit, and improves the reliability of the circuit.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a driving circuit, a dual active bridge conversion circuit, a circuit working method and an electronic device. Background Art

[0002] In the field of integrated circuits, power tubes are usually driven by multiple cascade-connected inverters. However, due to the series conduction phenomenon of the inverters, the series conduction current increases with the frequency of the switching signal that controls the on and off of the inverters, resulting in large circuit losses. At the same time, in the existing inverter chain, the N-type transistors and P-type transistors of each stage of the inverter are set in similar proportions, for example, the size ratio is 1:3, resulting in a slow response speed of the inverter chain. Summary of the invention

[0003] In order to solve the problems in the related art, the embodiments of the present disclosure provide a driving circuit, a dual active bridge conversion circuit, a circuit working method and an electronic device.

[0004] In a first aspect, an embodiment of the present disclosure provides a driving circuit, including:

[0005] A first power device, a second power device, a first sub-driving circuit, a second sub-driving circuit and a feedforward circuit;

[0006] Wherein, the first sub-driving circuit is used to drive the first power device, and the second sub-driving circuit is used to drive the second power device;

[0007] The feedforward circuit is used to provide a charging and discharging path for the driving circuit when the first power device and the second power device are turned off.

[0008] According to an embodiment of the present disclosure, the first power device includes a first P-type transistor Q1, and the second power device includes a first N-type transistor Q2;

[0009] The gate of the first P-type transistor Q1 is connected to the output end of the first sub-driving circuit, the gate of the first N-type transistor Q2 is connected to the output end of the second sub-driving circuit, and the drains of the first P-type transistor Q1 and the first N-type transistor Q2 are connected to form the output end of the power device.

[0010] According to an embodiment of the present disclosure, the feedforward circuit is used to provide a charging and discharging path for the driving circuit when the first power device and the second power device are turned off, and includes:

[0011] The feed-forward circuit is used to provide a charging path from a power supply to an output terminal of the power device for the drive circuit when the first power device and the second power device are turned off; and / or

[0012] The feed-forward circuit is used to provide a discharge path from the output end of the power device to the ground for the driving circuit when the first power device and the second power device are turned off.

[0013] According to an embodiment of the present disclosure, the feedforward circuit includes:

[0014] A second P-type transistor Q3, a second N-type transistor Q4, a first feedforward logic branch, and a second feedforward logic branch;

[0015] The gate of the second P-type transistor Q3 is connected to the output end of the first feedforward logic branch, the gate of the second N-type transistor Q4 is connected to the output end of the second feedforward logic branch, the drain of the second P-type transistor Q3 and the second N-type transistor Q4 is connected, and is connected to the drain of the first P-type transistor Q1 and the first N-type transistor Q2 via the first resistor R1;

[0016] The input end of the first feedforward logic branch is respectively connected to the input end of the driving circuit and the first intermediate node of the first sub-driving circuit, and the input end of the second feedforward logic branch is respectively connected to the input end of the driving circuit and the second intermediate node of the second sub-driving circuit, wherein the logic level of the first intermediate node is the same as the gate logic level of the first P-type transistor Q1, and the logic level of the second intermediate node is the same as the gate logic level of the first N-type transistor Q2.

[0017] According to an embodiment of the present disclosure, the first feedforward logic branch includes a second NAND gate, a fifth inverter and a sixth inverter connected in series, a first input end of the second NAND gate is connected to an input end of the driving circuit, a second input end is connected to the first intermediate node, an output end of the second NAND gate is connected to the fifth inverter, the fifth inverter and the sixth inverter are connected in series, and an output end of the sixth inverter is connected to the gate of the second P-type transistor Q3;

[0018] The second feedforward logic branch includes a second NOR gate, a seventh inverter and an eighth inverter connected in series, a first input terminal of the second NOR gate is connected to the input terminal of the drive circuit, a second input terminal is connected to the second intermediate node, an output terminal of the second NOR gate is connected to the seventh inverter, the seventh inverter and the eighth inverter are connected in series, and an output terminal of the eighth inverter is connected to the gate of the second N-type transistor Q4.

[0019] According to an embodiment of the present disclosure, the device size of the second P-type transistor Q3 is smaller than the device size of the first P-type transistor Q1, and the device size of the second N-type transistor Q4 is smaller than the device size of the first N-type transistor Q2, so that the ratio of the series current in the conductive path formed by the first P-type transistor Q1 and the second N-type transistor Q4 to the series current in the conductive path formed by the first P-type transistor Q1 and the first N-type transistor Q2 is greater than or equal to a first threshold and less than or equal to a second threshold; or

[0020] A ratio of a series current in a conductive path formed by the second P-type transistor Q3 and the first N-type transistor Q2 to a series current in a conductive path formed by the first P-type transistor Q1 and the first N-type transistor Q2 is greater than or equal to a first threshold and less than or equal to a second threshold.

[0021] According to an embodiment of the present disclosure, the first threshold is 0.1 and the second threshold is 0.2.

[0022] According to an embodiment of the present disclosure, the first sub-driving circuit includes a first inverter chain, and the second sub-driving circuit includes a second inverter chain;

[0023] The first inverter chain and the second inverter chain both have an asymmetric structure.

[0024] According to an embodiment of the present disclosure, both the first inverter chain and the second inverter chain have an asymmetric structure, including:

[0025] In each stage of the inverter chain, a device size ratio of a transistor corresponding to a driving signal to another transistor is greater than or equal to a third threshold and less than or equal to a fourth threshold.

[0026] According to an embodiment of the present disclosure, the first threshold is 3 and the second threshold is 5.

[0027] According to an embodiment of the present disclosure, the transistor corresponding to the driving signal includes:

[0028] When the first inverter chain drives the first P-type transistor Q1 and the driving signal of the first-stage inverter in the first inverter chain is a low-level signal, the transistors corresponding to the driving signal in the odd-numbered inverters of the first inverter chain are P-type transistors in the inverters of the same stage, and the transistors corresponding to the driving signal in the even-numbered inverters of the first inverter chain are N-type transistors in the inverters of the same stage;

[0029] When the second inverter chain drives the first N-type transistor Q2 and the driving signal of the first-stage inverter in the second inverter chain is a high-level signal, the transistors corresponding to the driving signal in the odd-numbered stages of the second inverter chain are N-type transistors in the inverter of that stage, and the transistors corresponding to the driving signal in the even-numbered stages of the second inverter chain are P-type transistors in the inverter of that stage.

[0030] According to an embodiment of the present disclosure, the first sub-driving circuit further includes a first feedback circuit, and the second sub-driving circuit further includes a second feedback circuit;

[0031] Among them, the input end of the first feedback circuit is connected to the drain of the first P-type transistor Q1, and the output end is connected to the second input end of the first sub-driving circuit; the input end of the second feedback circuit is connected to the drain of the first N-type transistor Q2, and the output end is connected to the second input end of the second sub-driving circuit; the first input ends of the first sub-driving circuit and the second sub-driving circuit are both connected to the input end of the driving circuit.

[0032] According to an embodiment of the present disclosure, the first sub-driving circuit further includes a first NAND gate, and the second sub-driving circuit further includes a first NOR gate;

[0033] Among them, the first input end of the first NAND gate is connected to the first input end of the first sub-driving circuit, the second input end of the first NAND gate is connected to the second input end of the first sub-driving circuit, the first input end of the first NOR gate is connected to the first input end of the second sub-driving circuit, and the second input end of the first NOR gate is connected to the second input end of the second driving circuit.

[0034] In a second aspect, an embodiment of the present disclosure provides a circuit operation method, the method being applied to a driving circuit as described in any one of the first aspects, the method comprising:

[0035] When the first P-type transistor Q1 and the first N-type transistor Q2 of the driving circuit are both in the off state, and the initial state of the input terminal of the driving circuit is a low level, the second N-type transistor Q4 is turned on through the second feedforward logic branch, so as to provide a discharge path from the output terminal of the power device to the ground for the driving circuit when the first P-type transistor Q1 and the first N-type transistor Q2 are both in the off state;

[0036] When the input terminal of the driving circuit is converted from a low level to a high level, the first P-type transistor Q1 is turned on through the first sub-driving circuit, the second N-type transistor Q4 is turned off through the second feedforward logic branch, and the first N-type transistor Q2 and the second P-type transistor Q3 are respectively kept turned off through the second sub-driving circuit and the first feedforward logic branch, so that when the input terminal of the driving circuit is converted from a low level to a high level, the first P-type transistor Q1 is provided with a high-level driving signal, and the first P-type transistor Q1 is turned off after being turned on for a first time period through the first sub-driving circuit;

[0037] When the first P-type transistor Q1 and the first N-type transistor Q2 of the driving circuit are both in the off state, and the initial state of the input terminal of the driving circuit is a high level, the second P-type transistor Q3 is turned on through the first feedforward logic branch, so as to provide a charging path from the power supply to the output terminal of the power device for the driving circuit when the first P-type transistor Q1 and the first N-type transistor Q2 are both in the off state;

[0038] When the input end of the drive circuit is converted from a high level to a low level, the first N-type transistor Q2 is turned on through the second sub-drive circuit, the second P-type transistor Q3 is turned off through the first feedforward logic branch, and the first P-type transistor Q1 and the second N-type transistor Q4 are kept turned off through the first sub-drive circuit and the second feedforward logic branch, respectively, so that when the input end of the drive circuit is converted from a high level to a low level, a low-level drive signal is provided through the first N-type transistor Q2, and the first N-type transistor Q2 is turned off after being turned on for a second time period through the second sub-drive circuit.

[0039] In a third aspect, an embodiment of the present disclosure provides a dual active bridge conversion circuit, comprising:

[0040] Dual active bridge converter and driver circuit;

[0041] Wherein, the driving circuit is the driving circuit described in any embodiment of the first aspect above.

[0042] In a fourth aspect, an electronic device is provided in an embodiment of the present disclosure, and the electronic device includes a driving circuit as described in any embodiment of the first aspect.

[0043] In a fifth aspect, an electronic device is provided in an embodiment of the present disclosure, and the electronic device includes the dual active bridge conversion circuit as described in the third aspect.

[0044] In a sixth aspect, a chip is provided in an embodiment of the present disclosure, wherein the chip comprises a driving circuit as described in any embodiment of the first aspect.

[0045] In a seventh aspect, a chip is provided in an embodiment of the present disclosure, and the chip includes the driving circuit as described in the third aspect.

[0046] According to the technical solution provided by the embodiment of the present disclosure, a driving circuit is provided, the driving circuit comprising: a first power device, a second power device, a first sub-driving circuit, a second sub-driving circuit and a feedforward circuit; wherein the first sub-driving circuit is used to drive the first power device, and the second sub-driving circuit is used to drive the second power device; the feedforward circuit is used to provide a charging and discharging path for the driving circuit when the first power device and the second power device are turned off. By adopting the technical solution of the embodiment of the present disclosure, by respectively providing independent driving circuits for the first power device and the second power device, and adding a feedforward circuit, the conduction delay time is reduced while the series current is greatly reduced, the erroneous start-up of the power device caused by large noise on the power line or the ground line is avoided, the power consumption of the circuit is reduced, and the reliability of the circuit is improved.

[0047] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings.

[0049] Figure 1 A structural diagram of a driving circuit according to an embodiment of the present disclosure is shown.

[0050] Figure 2 A flow chart showing a working method of a circuit according to an embodiment of the present disclosure is shown.

[0051] Figure 3 A structural diagram of a dual active bridge conversion circuit according to an embodiment of the present disclosure is shown.

[0052] Figure 4 A structural diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0053] Figure 5 A structural diagram of another electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0054] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0055] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0056] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0057] In the present disclosure, if it involves operations of obtaining user information or user data or displaying user information or user data to others, the operations are all authorized and confirmed by the user, or actively selected by the user.

[0058] Figure 1 FIG. 2 shows a structural diagram of a driving circuit according to an embodiment of the present disclosure. Figure 1 As shown, the driving circuit includes:

[0059] A first power device, a second power device, a first sub-driving circuit, a second sub-driving circuit and a feedforward circuit;

[0060] Wherein, the first sub-driving circuit is used to drive the first power device, and the second sub-driving circuit is used to drive the second power device;

[0061] The feedforward circuit is used to provide a charging and discharging path for the driving circuit when the first power device and the second power device are turned off.

[0062] As mentioned above, in the field of integrated circuits, power tubes are usually driven by multiple cascade-connected inverters. However, due to the series connection phenomenon of the inverters, the series current increases with the frequency of the switch signal that controls the inverter to be turned on and off, resulting in large circuit losses. This technical problem can be solved by driving the P-type power tube and the N-type power tube separately, and making the P-type power tube and the N-type power tube turn off quickly after turning on. However, the circuit structure that directly drives the P-type power tube and the N-type power tube separately has low noise resistance. This is because when this circuit is working, the P-type power tube and the N-type power tube are in a simultaneous off state for a long time. In the off state, there is no current charging and discharging path in the circuit. At this time, if a large noise is generated on the power line, the ground line or other leads, such as noise greater than the threshold voltage of the P-type power tube or the N-type power tube, it may cause the P-type power tube or the N-type power tube to be turned on by mistake, thereby affecting the normal operation of the circuit.

[0063] In view of this, a driving circuit is proposed in the embodiment of the present disclosure, by adding a feedforward circuit, and setting the feedforward circuit to provide a charging and discharging path for the driving circuit when the P-type power tube and the N-type power tube are in the off state at the same time, so as to solve the above technical problems. At the same time, the size of the device in the feedforward circuit is much smaller than the power tube, so that the new series current brought by the feedforward circuit is small enough, and the impact on the circuit loss is within an acceptable range.

[0064] In the embodiment of the present disclosure, the driving circuit may be a circuit that provides a driving signal for any switch tube, and the driving circuit includes a first power device, a second power device, a first sub-driving circuit, a second sub-driving circuit, and a feedforward circuit. The first power device may include a first P-type transistor Q1, and the second power device may include a first N-type transistor Q2. The gate of the first P-type transistor Q1 is connected to the output end of the first sub-driving circuit, the source is connected to the power supply voltage, the drain is connected to the drain of the first N-type transistor Q2, and is connected to the feedforward circuit. The gate of the first N-type transistor Q2 is connected to the output end of the second sub-driving circuit, and the source is grounded.

[0065] In the embodiment of the present disclosure, the feedforward circuit includes a second P-type transistor Q3, a second N-type transistor Q4, a first feedforward logic branch and a second feedforward logic branch, wherein the gate of the second P-type transistor Q3 is connected to the output end of the first feedforward logic branch, the gate of the second N-type transistor Q4 is connected to the output end of the second feedforward logic branch, the drains of the second P-type transistor Q3 and the second N-type transistor Q4 are connected, and are connected to the drains of the first P-type transistor Q1 and the first N-type transistor Q2, the input end of the first feedforward logic branch is respectively connected to the input end of the drive circuit and the first intermediate node of the first sub-drive circuit, the input end of the second feedforward logic branch is respectively connected to the input end of the drive circuit and the second intermediate node of the second sub-drive circuit, wherein the logic level of the first intermediate node is the same as the gate logic level of the first P-type transistor Q1, and the logic level of the second intermediate node is the same as the gate logic level of the first N-type transistor Q2.

[0066] In the embodiment of the present disclosure, the second P-type transistor Q3 and the second N-type transistor Q4 form an auxiliary path in the driving circuit to provide a charging and discharging path for the driving circuit when the first P-type transistor Q1 and the first N-type transistor Q2 are both in the off state, thereby preventing the noise generated on the power line, ground line or other leads from causing the first P-type transistor Q1 and / or the first N-type transistor Q2 to be mistakenly turned on, thereby causing the driving circuit to generate an erroneous output.

[0067] In the embodiment of the present disclosure, the first feedforward logic branch and the second logic feedforward branch are used to immediately turn off the second N-type transistor Q4 when the input signal of the drive circuit is converted from a low level to a high level so that the drive circuit outputs a high-level drive signal, and then turn on the second P-type transistor Q3 when the input signal is switched again so that the first P-type transistor Q1 and the first N-type transistor Q2 are both in the off state, so as to provide the drive circuit with a charging path from the power supply to the output end of the power device; and when the input signal of the drive circuit is converted from a high level to a low level so that the drive circuit outputs a low-level drive signal, immediately turn off the second P-type transistor Q3, and then turn on the second N-type transistor Q4 when the input signal is switched again so that the first P-type transistor Q1 and the first N-type transistor Q2 are both in the off state, so as to provide the drive circuit with a charging path from the output end of the power device to the ground.

[0068] In the embodiments of the present disclosure, Figure 1 As shown, the first feedforward logic branch may include a second NAND gate NAND2, a fifth inverter I5 and a sixth inverter I6, wherein the first input end of the second NAND gate NAND2 is connected to the input end of the driving circuit, and the second input end is connected to the first intermediate node of the first sub-driving circuit, and the first intermediate node of the first sub-driving circuit may be a node in the first inverter chain, and it should be noted that the logic level of the first intermediate node must meet the same logic level as the gate of the first P-type transistor Q1; the output end of the second NAND gate NAND2 is connected to the input end of the sixth inverter I6, and the fifth inverter I5, the sixth inverter I6 and the sixth inverter I6 are connected in series, and the output end of the sixth inverter I6 is connected to the gate of the second P-type transistor Q3. With such a structure, the second P-type transistor Q3 can be controlled to turn on when the first P-type transistor Q1 and the first N-type transistor Q2 are both in the off state through the first feedforward logic branch, so as to form a charging path in the circuit, thereby avoiding the large noise on the power line causing the first P-type transistor Q1 to turn on by mistake.

[0069] In the embodiment of the present disclosure, the second feedforward logic branch may include a second NOR gate NOR2, a seventh inverter I7 and an eighth inverter I8, wherein the first input terminal of the second NOR gate NOR2 is connected to the input terminal of the driving circuit, and the second input terminal is connected to the second intermediate node of the second sub-driving circuit, wherein the second intermediate node of the second sub-driving circuit may be a node in the second inverter chain, and similarly, the logic level of the second intermediate node is the same as the gate logic level of the first N-type transistor Q2; the output terminal of the second NOR gate NOR2 is connected to the input terminal of the eighth inverter I8, the seventh inverter I7, the eighth inverter I8 and the eighth inverter I8 are connected in series, and the output terminal of the eighth inverter I8 is connected to the gate of the second N-type transistor Q4. With such a structure, the second feedforward logic branch can be used to control the second N-type transistor Q4 to be turned on when both the first P-type transistor Q1 and the first N-type transistor Q2 are in the off state, so as to form a discharge path in the circuit, thereby preventing the first N-type transistor Q2 from being turned on by mistake due to the large noise on the ground line.

[0070] According to the technical solution of the embodiment of the present disclosure, by respectively providing independent driving circuits for the first power device and the second power device and adding a feedforward circuit, the series current between the first power device and the second power device is greatly reduced while the turn-on delay time is reduced, thereby avoiding the erroneous start-up of the power device caused by large noise on the power line or the ground line, reducing the power consumption of the circuit and improving the reliability of the circuit.

[0071] In the embodiment of the present disclosure, in the additional feedforward circuit, the charge-discharge branch formed by the second P-type transistor Q3 and the second N-type transistor Q4 can eliminate the noise caused by the power line and the ground line, but it also brings new series current. Specifically, the newly introduced second N-type transistor Q4 and the first P-type transistor Q1 may still form a conductive path to generate a series current, and the newly introduced second P-type transistor Q3 and the first N-type transistor Q2 may also form a conductive path to generate a series current. In view of this, the device size of the second P-type transistor Q3 can be set to be smaller than the device size of the first P-type transistor Q1, and the device size of the second N-type transistor Q4 can be set to be smaller than the device size of the first N-type transistor Q2, so that the ratio of the series current in the conductive path formed by the first P-type transistor Q1 and the second N-type transistor Q4 to the series current in the conductive path formed by the first P-type transistor Q1 and the first N-type transistor Q2 is greater than or equal to the first threshold and less than or equal to the second threshold; or the ratio of the series current in the conductive path formed by the second P-type transistor Q3 and the first N-type transistor Q2 to the series current in the conductive path formed by the first P-type transistor Q1 and the first N-type transistor Q2 is greater than or equal to the first threshold and less than or equal to the second threshold. In a specific embodiment of the present disclosure, the device size ratio of the second P-type transistor Q3 to the first P-type transistor Q1, and the device size ratio of the second N-type transistor Q4 to the first N-type transistor Q2 can be 1:10, the first threshold can be 0.1, and the second threshold can be 0.2.

[0072] According to the technical solution of the embodiment of the present disclosure, by setting the device size of the second P-type transistor Q3 to be smaller than the device size of the first P-type transistor Q1, and the device size of the second N-type transistor Q4 to be smaller than the device size of the first N-type transistor Q2, the series current caused by the newly introduced second P-type transistor Q3 and the second N-type transistor Q4 can be greatly reduced, thereby achieving a higher reliability improvement at a lower noise cost.

[0073] In the embodiment of the present disclosure, the drains of the first P-type transistor Q1 and the first N-type transistor Q2 may also be connected to the drains of the second P-type transistor Q3 and the second N-type transistor Q4 via the first resistor R1, so as to further reduce the series current generated by the conductive path formed by the second N-type transistor Q4 and the first P-type transistor Q1, and / or the series current generated by the conductive path formed by the second P-type transistor Q3 and the first N-type transistor Q2.

[0074] In the embodiments of the present disclosure, Figure 1As shown, the first sub-driving circuit may include a first inverter chain and a first feedback circuit, wherein the input end of the first inverter chain is connected to the output end of the first NAND gate NAND1, and the output end of the first inverter chain is connected to the gate of the first P-type transistor Q1; the first input end of the first NAND gate NAND1 is connected to the input end of the driving circuit, and the second input end is connected to the output end of the first feedback circuit. The first feedback circuit includes a first inverter I1, a second inverter I2, a third P-type transistor Q5 and a first current source S1, wherein the gate of the third P-type transistor Q5 is connected to the drain of the first P-type transistor Q1, the source is connected to the power supply voltage, the drain is connected to the input end of the first current source S1, and is connected to the input end of the second inverter I2, the output end of the current source is grounded, the second inverter I2 is connected in series with the first inverter I1, and the output end of the first inverter I1 is connected to the second input end of the first NAND gate NAND1. By adopting such a structure, a driving signal can be provided separately for the first P-type transistor Q1 through the first inverter chain, and the first P-type transistor Q1 can be turned off quickly after being turned on through the first feedback circuit, thereby avoiding the generation of series current in the branch formed by the first P-type transistor Q1 and the first N-type transistor Q2.

[0075] In the embodiment of the present disclosure, the second sub-driving circuit may include a second inverter chain and a second feedback circuit, the input end of the second inverter chain is connected to the output end of the first NOR gate NOR1, and the output end of the second inverter chain is connected to the gate of the first N-type transistor Q2; the first input end of the first NOR gate NOR1 is connected to the input end of the driving circuit, and the second input end is connected to the output end of the second feedback circuit; the second feedback circuit includes a third inverter I3, a fourth inverter I4, a third N-type transistor Q6 and a second current source S2, the gate of the third N-type transistor Q6 is connected to the drain of the first N-type transistor Q2, the source is grounded, the drain is connected to the output end of the second current source S2, and is connected to the input end of the fourth inverter I4, the input end of the current source is connected to the power supply voltage, the fourth inverter I4 is connected in series with the third inverter I3, and the output end of the third inverter I3 is connected to the second input end of the first NOR gate NOR1. With such a structure, a driving signal can be provided separately for the first N-type transistor Q2 through the second inverter chain, and the second feedback circuit can be used to turn off the N-type transistor Q2 quickly after it is turned on, thereby also avoiding the generation of series current in the branch formed by the first P-type transistor Q1 and the first N-type transistor Q2.

[0076] Through the technical solution of the embodiment of the present disclosure, the first P-type transistor Q1 and the first N-type transistor Q2 are respectively set to be turned off quickly after being turned on through the first sub-driving circuit and the second sub-driving circuit, thereby further avoiding the series current caused by the simultaneous conduction of the first P-type transistor Q1 and the first N-type transistor Q2, and reducing the power consumption of the circuit.

[0077] It is also mentioned above that in the existing inverter chain, the N-type transistors and the P-type transistors of each stage of the inverter are arranged in similar proportions, for example, the size ratio is 1:3, which results in a slow response speed of the inverter chain.

[0078] In view of this, in the embodiment of the present disclosure, the first inverter chain and the second inverter chain may be set to an asymmetric structure. The asymmetric structure means that in each stage of the inverter chain, the transistor corresponding to the drive signal has a larger size and the other transistor has a smaller size. Specifically, when the first inverter chain drives the first P-type transistor Q1 and the driving signal of the first-stage inverter in the first inverter chain is a low-level signal, the transistors corresponding to the driving signal in the odd-numbered inverters of the first inverter chain are P-type transistors in the inverter of this stage, and the transistors corresponding to the driving signal in the even-numbered inverters of the first inverter chain are N-type transistors in the inverter of this stage; when the second inverter chain drives the first N-type transistor Q2 and the driving signal of the first-stage inverter in the second inverter chain is a high-level signal, the transistors corresponding to the driving signal in the odd-numbered inverters of the second inverter chain are N-type transistors in the inverter of this stage, and the transistors corresponding to the driving signal in the even-numbered inverters of the second inverter chain are P-type transistors in the inverter of this stage, and so on, which will not be repeated here.

[0079] In an embodiment of the present disclosure, the device size ratio of the transistor corresponding to the driving signal to another transistor can be set to be greater than or equal to a third threshold and less than or equal to a fourth threshold. In a specific implementation of the present disclosure, the first threshold can be 3 and the second threshold can be 5.

[0080] Through the technical solution of the embodiment of the present disclosure, by setting the inverter chain in the self-driving circuit to an asymmetric structure, only one driving tube with a larger size is required at each level, and the other transistor can be set to a smaller size, thereby improving the response speed, saving the layout area, and improving the integration of the circuit.

[0081] Figure 2 A flowchart showing a circuit operation method according to an embodiment of the present disclosure is shown. The circuit operation method is applied to Figure 1 The driving circuit in the embodiment shown. Figure 2 As shown, the method includes steps S201-S204:

[0082] In step S201, when the first P-type transistor Q1 and the first N-type transistor Q2 of the driving circuit are both in the off state and the initial state of the input terminal of the driving circuit is a low level, the second N-type transistor Q4 is turned on through the second feedforward logic branch to provide a discharge path from the output terminal of the power device to the ground for the driving circuit when the first P-type transistor Q1 and the first N-type transistor Q2 are both in the off state;

[0083] In step S202, when the input terminal of the driving circuit is converted from a low level to a high level, the first P-type transistor Q1 is turned on through the first sub-driving circuit, the second N-type transistor Q4 is turned off through the second feedforward logic branch, and the first N-type transistor Q2 and the second P-type transistor Q3 are respectively kept turned off through the second sub-driving circuit and the first feedforward logic branch, so that when the input terminal of the driving circuit is converted from a low level to a high level, the first P-type transistor Q1 is provided with a high-level driving signal, and the first P-type transistor Q1 is turned off after being turned on for a first time period through the first sub-driving circuit;

[0084] In step S203, when the first P-type transistor Q1 and the first N-type transistor Q2 of the driving circuit are both in the off state and the initial state of the input terminal of the driving circuit is a high level, the second P-type transistor Q3 is turned on through the first feedforward logic branch to provide a charging path from the power supply to the output terminal of the power device for the driving circuit when the first P-type transistor Q1 and the first N-type transistor Q2 are both in the off state;

[0085] In step S204, when the input end of the drive circuit is converted from a high level to a low level, the first N-type transistor Q2 is turned on through the second sub-drive circuit, the second P-type transistor Q3 is turned off through the first feedforward logic branch, and the first P-type transistor Q1 and the second N-type transistor Q4 are respectively kept turned off through the first sub-drive circuit and the second feedforward logic branch, so that when the input end of the drive circuit is converted from a high level to a low level, a low-level drive signal is provided through the first N-type transistor Q2, and the first N-type transistor Q2 is turned off after being turned on for a second time period through the second sub-drive circuit.

[0086] According to the technical solution of the embodiment of the present disclosure, during the level flipping process of the driving circuit, the large size of the first P-type transistor Q1 and the first N-type transistor Q2 is utilized to ensure the rapid change of the drain voltage of the output end of the power device, i.e., the first P-type transistor Q1 and the first N-type transistor Q2. At the same time, after the output end of the power device reaches the required state, the first P-type transistor Q1 and the first N-type transistor Q2 are turned off, thereby eliminating the series current caused by the turning off of the first P-type transistor Q1 and the first N-type transistor Q2. In addition, when the first P-type transistor Q1 and the first N-type transistor Q2 are turned off and the output level is maintained, the small size of the second P-type transistor Q3 and the second N-type transistor Q4 is utilized to provide a charging and discharging path for the driving circuit, thereby avoiding the first P-type transistor Q1 and / or the first N-type transistor Q2 being mistakenly turned on due to large noise on the power supply or ground line, thereby improving the reliability of the circuit.

[0087] Figure 3 A structural diagram of a dual active bridge conversion circuit according to an embodiment of the present disclosure is shown.

[0088] like Figure 3 As shown, the dual active bridge conversion circuit includes a dual active bridge converter and a drive circuit; wherein the drive circuit is Figure 1 The driving circuit shown.

[0089] Figure 4 A structural diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0090] like Figure 4 As shown, the electronic device includes Figure 1 The driving circuit shown, the electronic device can be any device including a driven circuit, and is not limited here.

[0091] Figure 5 FIG. 2 shows a structural diagram of another electronic device according to an embodiment of the present disclosure. Figure 5 As shown, the electronic device includes Figure 3 In the dual active bridge conversion circuit shown, the electronic device can be any device including a driven circuit, and no limitation is made here.

[0092] The present disclosure also provides a chip, the chip comprising: Figure 1 The driving circuit shown.

[0093] The present disclosure also provides another chip, the chip comprising: Figure 3 The driving circuit shown.

[0094] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A driving circuit, It is characterized in that include: A first power device, a second power device, a first sub-driving circuit, a second sub-driving circuit and a feedforward circuit; Wherein, the first sub-driving circuit is used to drive the first power device, and the second sub-driving circuit is used to drive the second power device; The feedforward circuit is used to provide a charging and discharging path for the driving circuit when the first power device and the second power device are turned off; Wherein, the first power device includes a first P-type transistor Q1, and the second power device includes a first N-type transistor Q2; The gate of the first P-type transistor Q1 is connected to the output end of the first sub-driving circuit, the gate of the first N-type transistor Q2 is connected to the output end of the second sub-driving circuit, and the drains of the first P-type transistor Q1 and the first N-type transistor Q2 are connected to form the output end of the power device; The feedforward circuit comprises: A second P-type transistor Q3, a second N-type transistor Q4, a first feedforward logic branch, and a second feedforward logic branch; The gate of the second P-type transistor Q3 is connected to the output end of the first feedforward logic branch, the gate of the second N-type transistor Q4 is connected to the output end of the second feedforward logic branch, the drain of the second P-type transistor Q3 and the second N-type transistor Q4 is connected, and is connected to the drain of the first P-type transistor Q1 and the first N-type transistor Q2 via the first resistor R1; The input end of the first feedforward logic branch is respectively connected to the input end of the driving circuit and the first intermediate node of the first sub-driving circuit, and the input end of the second feedforward logic branch is respectively connected to the input end of the driving circuit and the second intermediate node of the second sub-driving circuit, wherein the logic level of the first intermediate node is the same as the gate logic level of the first P-type transistor Q1, and the logic level of the second intermediate node is the same as the gate logic level of the first N-type transistor Q2.

2. The circuit according to claim 1, It is characterized in that The feedforward circuit is used to provide a charging and discharging path for the driving circuit when the first power device and the second power device are turned off, and includes: The feed-forward circuit is used to provide a charging path from a power supply to an output terminal of the power device for the drive circuit when the first power device and the second power device are turned off; and / or The feed-forward circuit is used to provide a discharge path from the output end of the power device to the ground for the driving circuit when the first power device and the second power device are turned off.

3. The circuit according to claim 1, It is characterized in that The first feedforward logic branch includes a second NAND gate, a fifth inverter and a sixth inverter connected in series, a first input terminal of the second NAND gate is connected to the input terminal of the driving circuit, a second input terminal is connected to the first intermediate node, an output terminal of the second NAND gate is connected to the input terminal of the fifth inverter, the fifth inverter and the sixth inverter are connected in series, and an output terminal of the sixth inverter is connected to the gate of the second P-type transistor Q3; The second feedforward logic branch includes a second NOR gate, a seventh inverter and an eighth inverter connected in series, a first input terminal of the second NOR gate is connected to the input terminal of the drive circuit, a second input terminal is connected to the second intermediate node, an output terminal of the second NOR gate is connected to the input terminal of the seventh inverter, the seventh inverter and the eighth inverter are connected in series, and an output terminal of the eighth inverter is connected to the gate of the second N-type transistor Q4.

4. The circuit according to claim 1, It is characterized in that The device size of the second P-type transistor Q3 is smaller than the device size of the first P-type transistor Q1, and the device size of the second N-type transistor Q4 is smaller than the device size of the first N-type transistor Q2, so that the ratio of the series current in the conductive path formed by the first P-type transistor Q1 and the second N-type transistor Q4 to the series current in the conductive path formed by the first P-type transistor Q1 and the first N-type transistor Q2 is greater than or equal to a first threshold and less than or equal to a second threshold; or A ratio of a series current in a conductive path formed by the second P-type transistor Q3 and the first N-type transistor Q2 to a series current in a conductive path formed by the first P-type transistor Q1 and the first N-type transistor Q2 is greater than or equal to a first threshold and less than or equal to a second threshold.

5. The circuit according to claim 4, It is characterized in that The first threshold is 0.1, and the second threshold is 0.

2.

6. The circuit according to claim 2, It is characterized in that The first sub-driving circuit comprises a first inverter chain, and the second sub-driving circuit comprises a second inverter chain; The first inverter chain and the second inverter chain both have an asymmetric structure.

7. The circuit according to claim 6, It is characterized in that The first inverter chain and the second inverter chain both have an asymmetric structure, including: In each stage of the inverter chain, a device size ratio of a transistor corresponding to a driving signal to another transistor is greater than or equal to a third threshold and less than or equal to a fourth threshold.

8. The circuit according to claim 7, It is characterized in that The third threshold is 3, and the fourth threshold is 5.

9. The circuit according to claim 7, It is characterized in that The transistor corresponding to the driving signal includes: When the first inverter chain drives the first P-type transistor Q1 and the driving signal of the first-stage inverter in the first inverter chain is a low-level signal, the transistors corresponding to the driving signal in the odd-numbered inverters of the first inverter chain are P-type transistors in the inverters of the same stage, and the transistors corresponding to the driving signal in the even-numbered inverters of the first inverter chain are N-type transistors in the inverters of the same stage; When the second inverter chain drives the first N-type transistor Q2 and the driving signal of the first-stage inverter in the second inverter chain is a high-level signal, the transistors corresponding to the driving signal in the odd-numbered stages of the second inverter chain are N-type transistors in the inverter of that stage, and the transistors corresponding to the driving signal in the even-numbered stages of the second inverter chain are P-type transistors in the inverter of that stage.

10. The circuit according to claim 2, It is characterized in that The first sub-driving circuit further includes a first feedback circuit, and the second sub-driving circuit further includes a second feedback circuit; Among them, the input end of the first feedback circuit is connected to the drain of the first P-type transistor Q1, and the output end is connected to the second input end of the first sub-driving circuit; the input end of the second feedback circuit is connected to the drain of the first N-type transistor Q2, and the output end is connected to the second input end of the second sub-driving circuit; the first input ends of the first sub-driving circuit and the second sub-driving circuit are both connected to the input end of the driving circuit.

11. The circuit according to claim 10, It is characterized in that The first sub-driving circuit further includes a first NAND gate, and the second sub-driving circuit further includes a first NOR gate; Among them, the first input end of the first NAND gate is connected to the first input end of the first sub-driving circuit, the second input end of the first NAND gate is connected to the second input end of the first sub-driving circuit, the first input end of the first NOR gate is connected to the first input end of the second sub-driving circuit, and the second input end of the first NOR gate is connected to the second input end of the second sub-driving circuit.

12. A method of operating a circuit, It is characterized in that The method is applied to the driving circuit according to any one of claims 1 to 11, and the method comprises: When the first P-type transistor Q1 and the first N-type transistor Q2 of the driving circuit are both in the off state, and the initial state of the input terminal of the driving circuit is a low level, the second N-type transistor Q4 is turned on through the second feedforward logic branch, so as to provide a discharge path from the output terminal of the power device to the ground for the driving circuit when the first P-type transistor Q1 and the first N-type transistor Q2 are both in the off state; When the input terminal of the driving circuit is converted from a low level to a high level, the first P-type transistor Q1 is turned on through the first sub-driving circuit, the second N-type transistor Q4 is turned off through the second feedforward logic branch, and the first N-type transistor Q2 and the second P-type transistor Q3 are respectively kept turned off through the second sub-driving circuit and the first feedforward logic branch, so that when the input terminal of the driving circuit is converted from a low level to a high level, the first P-type transistor Q1 is provided with a high-level driving signal, and the first P-type transistor Q1 is turned off after being turned on for a first time period through the first sub-driving circuit; When the first P-type transistor Q1 and the first N-type transistor Q2 of the driving circuit are both in the off state, and the initial state of the input terminal of the driving circuit is a high level, the second P-type transistor Q3 is turned on through the first feedforward logic branch, so as to provide a charging path from the power supply to the output terminal of the power device for the driving circuit when the first P-type transistor Q1 and the first N-type transistor Q2 are both in the off state; When the input end of the drive circuit is converted from a high level to a low level, the first N-type transistor Q2 is turned on through the second sub-drive circuit, the second P-type transistor Q3 is turned off through the first feedforward logic branch, and the first P-type transistor Q1 and the second N-type transistor Q4 are kept turned off through the first sub-drive circuit and the second feedforward logic branch, respectively, so that when the input end of the drive circuit is converted from a high level to a low level, a low-level drive signal is provided through the first N-type transistor Q2, and the first N-type transistor Q2 is turned off after being turned on for a second time period through the second sub-drive circuit.

13. A dual active bridge conversion circuit, It is characterized in that include: Dual active bridge converter and driver circuit; Wherein, the driving circuit is the driving circuit according to any one of claims 1-11.

14. An electronic device, It is characterized in that include: A drive circuit as claimed in any one of claims 1 to 11.

15. An electronic device, It is characterized in that include: The dual active bridge converter circuit as claimed in claim 13.

16. A chip, It is characterized in that The chip comprises the driving circuit according to any one of claims 1-11.

17. A chip, It is characterized in that The chip includes the dual active bridge conversion circuit as claimed in claim 13.

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