An interleaved signal generation circuit and integrated chip

Abstract

This invention discloses an interleaved signal generation circuit and an integrated chip to address the lack of flexibility in existing interleaved signal generation circuits. In this embodiment, a pulse generation circuit generates a first-cycle pulse signal and a second-cycle pulse signal. A counting circuit counts the first-cycle pulse signal and the second-cycle pulse signal to generate a rising-edge trigger signal and a falling-edge trigger signal. The signal generation circuit generates an interleaved pulse signal based on the input rising-edge trigger signal and the input falling-edge trigger signal. Since the interval between the rising-edge trigger signals input to each signal generation circuit can be the same or different, and the interval between the rising-edge trigger signals and the falling-edge trigger signals input to each signal generation circuit can also be the same or different, the pulse width and spacing of the resulting interleaved pulse signal can be flexibly set, thereby improving the flexibility of the interleaved pulse signal generation circuit.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to an interleaved signal generation circuit and an integrated chip. Background Technology

[0002] Currently, the chip design field is increasingly focusing on technical indicators such as high integration, multifunctionality, low power consumption, and miniaturization. With continuous technological innovation in the chip industry, and the emergence of requirements for simplified system application design and diversified design functions, chip circuit design is becoming more complex. Therefore, the demands for flexibility and functional diversity in signal generation circuits are increasing.

[0003] Interleaved signals are frequently used in chip circuit design. Interleaved signals can be categorized into equal-interval, equal-pulse-width, non-equal-interval, equal-interval, and non-equal-interval, non-equal-pulse-width interleaved signals. Currently, existing circuits for generating interleaved signals can only produce one type, which is not flexible enough. Summary of the Invention

[0004] This invention provides an interleaved signal generation circuit and an integrated chip to solve the problem of insufficient flexibility in existing interleaved signal generation circuits.

[0005] In a first aspect, embodiments of the present invention provide an interleaved signal generation circuit, comprising:

[0006] The pulse generation circuit is used to generate a first-cycle pulse signal and a second-cycle pulse signal based on the delayed signal and the initial signal.

[0007] A counting circuit is used to count the first periodic pulse signal and the second periodic pulse signal, and generate a rising edge trigger signal and a falling edge trigger signal;

[0008] The signal generation circuit is used to generate interleaved pulse signals based on the input rising edge trigger signal and the input falling edge trigger signal.

[0009] In one possible implementation, the signal generation circuit includes multiple signal generation sub-circuits;

[0010] Each signal generation sub-circuit is used to generate interleaved pulse sub-signals based on the input rising edge trigger signal and the input falling edge trigger signal;

[0011] The interleaved pulse signal is composed of multiple interleaved pulse sub-signals.

[0012] In one possible implementation, the signal generation sub-circuit includes an SR latch, a first NOT gate, and a second NOT gate:

[0013] The first input terminal of the SR latch is used to input a rising edge trigger signal, the second input terminal of the SR latch is used to input a falling edge trigger signal, the third input terminal of the SR latch is used to input a rising edge interleaving enable signal, and the output terminal of the SR latch is connected to the input terminal of the first NOT gate.

[0014] The output of the first NOT gate is connected to the input of the second NOT gate;

[0015] The output of the second NOT gate is used to output the interleaved pulse sub-signal.

[0016] In one possible implementation, if the time interval between the rising edge counting signals input to adjacent signal generation sub-circuits in the plurality of signal generation sub-circuits is the same, then the interleaved pulse signal is an equally spaced interleaved pulse signal.

[0017] If the time intervals of the rising edge counting signals input to adjacent signal generation sub-circuits in the plurality of signal generation sub-circuits are different, then the interleaved pulse signal is an interleaved pulse signal with non-equal intervals.

[0018] If the time interval between the rising edge counting signal and the corresponding falling edge counting signal input to each of the signal generation sub-circuits is the same, then the interleaved pulse signal is an interleaved pulse signal with equal pulse width.

[0019] If the time interval between the rising edge counting signal and its corresponding falling edge counting signal input to each of the signal generation sub-circuits is different, then the interleaved pulse signal is an interleaved pulse signal with non-equal pulse width.

[0020] In one possible implementation, the pulse generation circuit includes a first periodic pulse signal generation circuit and a second periodic pulse signal generation circuit.

[0021] The first periodic pulse signal generating circuit is used to generate the first periodic pulse signal based on the delayed signal, the initial signal, the rising edge interleaving enable signal, the rising edge interleaving adjustment delay signal, and the rising edge interleaving adjustment delay inverse signal.

[0022] The falling edge clock signal generation circuit is used to generate the second periodic pulse signal based on the delay signal, the initial signal, the falling edge interleaving enable signal, the rising edge interleaving adjustment delay signal, and the rising edge interleaving adjustment delay inverse signal.

[0023] In one possible implementation, the rising edge clock signal generation circuit includes: a first oscillator and a third NOT gate;

[0024] The first input terminal of the first oscillator is used to input the initial signal; the second input terminal of the first oscillator is used to input the rising edge interleaving enable signal; the third input terminal of the first oscillator is used to input the rising edge interleaving adjustment delay signal; the fourth input terminal of the first oscillator is used to input the rising edge interleaving adjustment delay inverse signal; the fifth input terminal of the first oscillator is used to input the delay signal; the output terminal of the first oscillator is connected to the input terminal of the third NOT gate and is used to output the rising edge clock signal; the output terminal of the third NOT gate is used to output the first periodic pulse signal.

[0025] The falling edge clock signal generation circuit includes a second oscillator, a fourth NOT gate, and a first NAND gate;

[0026] The input terminal of the fourth NOT gate is used to input the initial signal, and the output terminal of the fourth NOT gate is connected to the first input terminal of the second oscillator;

[0027] The second input terminal of the second oscillator is used to input the falling edge interleaving enable signal, the third input terminal of the second oscillator is used to input the rising edge interleaving adjustment delay signal, the fourth input terminal of the second oscillator is used to input the rising edge interleaving adjustment delay inverse signal, the fifth input terminal of the second oscillator is used to input the delay signal, and the output terminal of the second oscillator is connected to the first input terminal of the first NAND gate to output the falling edge clock signal;

[0028] The second input terminal of the first NAND gate is used to input the falling edge enable signal, and the output terminal of the first NAND gate is used to output the second periodic pulse signal.

[0029] One possible implementation also includes a fifth NOT gate and a flip-flop;

[0030] The input terminal of the fifth NOT gate is connected to the Clk terminal of the flip-flop for inputting ActEnPlaN, and the output terminal of the fifth NOT gate is connected to the ClkN terminal of the flip-flop.

[0031] The D terminal of the flip-flop is grounded, the RN terminal of the flip-flop is used to input the rising edge interleaved enable signal, and the Q terminal of the flip-flop is used to output the falling edge enable signal.

[0032] In one possible implementation, it also includes a second NAND gate, a third NAND gate, a fourth NAND gate, a sixth NOT gate, a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a tenth NOT gate, and a pulse conversion unit;

[0033] The first input terminal of the second NAND gate is used to input FnCoreActAllBnk, the second input terminal of the second NAND gate is used to input Burnin, and the output terminal of the second NAND gate is connected to the input terminal of the sixth NOT gate.

[0034] The output of the sixth NOT gate is used to output a rising edge interleaved enable signal;

[0035] The first input terminal of the third NAND gate is used to input RosEnBnki, the second input terminal of the third NAND gate is used to input the rising edge interleaved enable signal, and the output terminal of the third NAND gate is connected to the input terminal of the seventh NOT gate.

[0036] The output of the seventh gate is connected to the input of the pulse conversion unit and is used to output the initial signal;

[0037] The output terminal of the pulse conversion unit is connected to the first input terminal of the fourth NAND gate;

[0038] The second input terminal of the fourth NAND gate is used to input the rising edge interleaved enable signal, and the output terminal of the fourth NAND gate is connected to the input terminal of the eighth NOT gate.

[0039] The output of the eighth NOT gate is used to output the falling edge interleaved enable signal;

[0040] The input terminal of the ninth NOT gate is used to input ActStaggerDly, and the output terminal of the ninth NOT gate is connected to the input terminal of the tenth NOT gate to output the rising edge interleaved adjustment delay inverse signal.

[0041] The output of the tenth NOT gate is used to output the rising edge interleaved delay signal.

[0042] In one possible implementation, the counting circuit includes a plurality of series-connected rising edge trigger signal generating circuits and a plurality of series-connected falling edge trigger signal generating circuits.

[0043] A rising edge trigger signal generation circuit is used to generate the rising edge trigger signal based on the first periodic pulse signal, the rising edge interleaving enable delay signal, the rising edge interleaving enable signal, VSS, and the rising edge counting signal output by the previous rising edge counting signal generation circuit connected to the rising edge trigger signal generation circuit.

[0044] The falling edge trigger signal generation circuit is used to generate the falling edge trigger signal based on the second periodic pulse signal, the falling edge interleaving enable delay signal, the falling edge interleaving enable signal, VSS, and the falling edge count signal output by the previous falling edge count signal generation circuit connected to the falling edge trigger signal generation circuit.

[0045] In one possible implementation, the rising edge counting signal includes a first counter and an eleventh NOT gate;

[0046] The first input terminal of the first counter is used to input the first periodic pulse signal, the second input terminal of the first counter is used to input the rising edge interleaving enable delay signal, the third input terminal of the first counter is used to input VSS or the rising edge counting signal output by the previous first counter connected to the first counter, the fourth input terminal of the first counter is used to input the rising edge interleaving enable signal, the fifth input terminal of the first counter is used to input VSS, and the output terminal of the first counter is connected to the third input terminal of the next first counter and the input terminal of the eleventh NOT gate to output the rising edge counting signal;

[0047] The output of the eleventh NOT gate is used to output the rising edge trigger signal;

[0048] The falling edge counting signal circuit includes a second counter and a twelfth NOT gate;

[0049] The first input terminal of the second counter is used to input the second periodic pulse signal, the second input terminal of the second counter is used to input the falling edge interleaving enable delay signal, the third input terminal of the second counter is used to input VSS or the falling edge counting signal output by the previous second counter connected to the second counter, the fourth input terminal of the second counter is used to input the falling edge interleaving enable signal, the fifth input terminal of the second counter is used to input VSS, and the output terminal of the second counter is connected to the input terminal of the twelfth NOT gate to output the falling edge counting signal;

[0050] The output of the twelfth NOT gate is used to output the falling edge trigger signal.

[0051] One possible implementation also includes a first delay, a second delay, a third delay, a fourth delay, a fifth delay, a sixth delay, a seventh delay, an eighth delay, a NOR gate, and a thirteenth NOT gate;

[0052] The input terminal of the first delay is used to input the initial signal. The output terminal of the first delay is connected to the input terminal of the second delay. The output terminal of the second delay is connected to the input terminal of the third delay. The output terminal of the third delay is connected to the input terminal of the fourth delay. The output terminal of the fourth delay is used to output the rising edge interleaved enable delay signal.

[0053] The first input terminal of the NOR gate is used to input the initial signal, the second input terminal of the NOR gate is used to input the falling edge enable signal, the output terminal of the NOR gate is connected to the input terminal of the thirteenth NOT gate, the output terminal of the thirteenth NOT gate is connected to the input terminal of the fifth delay, the output terminal of the fifth delay is connected to the input terminal of the sixth delay, the output terminal of the sixth delay is connected to the input terminal of the seventh delay, the output terminal of the seventh delay is connected to the input terminal of the eighth delay, and the output terminal of the eighth delay is used to output the falling edge interleaved enable delay signal.

[0054] Secondly, embodiments of the present invention provide an integrated chip including the interleaved signal generation circuit described in any of the first aspects.

[0055] The beneficial effects of this invention are as follows:

[0056] In this embodiment of the invention, the counting circuit counts the first period pulse signal and the second period pulse signal to generate a rising edge clock count inverse signal and a falling edge trigger signal. The signal generation circuit generates an interleaved pulse signal based on the input rising edge trigger signal and the input falling edge trigger signal. Since the interval between the rising edge trigger signals input to each signal generation circuit can be the same or different, and the interval between the rising edge trigger signal and the falling edge trigger signal input to each signal generation circuit can be the same or different, the pulse width and spacing of the resulting interleaved pulse signal can be flexibly set, thereby improving the flexibility of the interleaved pulse signal generation circuit. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a schematic diagram of an interleaved signal generation circuit provided in an embodiment of the present invention;

[0059] Figure 2 This is a schematic diagram of the structure of a first-cycle pulse signal generation circuit provided in an embodiment of the present invention;

[0060] Figure 3 A schematic diagram of a falling edge clock signal generation circuit provided in an embodiment of the present invention;

[0061] Figure 4 A schematic diagram of an oscillator provided in an embodiment of the present invention;

[0062] Figure 5 This is a schematic diagram of another interleaved signal generation circuit provided in an embodiment of the present invention;

[0063] Figure 6 This is a schematic diagram of a rising edge interleaved enable signal generation circuit provided in an embodiment of the present invention;

[0064] Figure 7 This is a schematic diagram of a falling edge interleaved enable signal generation circuit provided in an embodiment of the present invention;

[0065] Figure 8 A circuit for generating a rising edge interleaved adjustment delay signal and a rising edge interleaved adjustment delay inverse signal is provided in an embodiment of the present invention;

[0066] Figure 9 A waveform diagram of a signal provided in an embodiment of the present invention;

[0067] Figure 10 This is a schematic diagram of a rising edge trigger signal generation circuit provided in an embodiment of the present invention;

[0068] Figure 11 This is a schematic diagram of a rising edge trigger signal generation circuit provided in an embodiment of the present invention;

[0069] Figure 12 This is a schematic diagram of the structure of a counter provided in an embodiment of the present invention;

[0070] Figure 13 A schematic diagram of a rising edge interleaved enable delay signal generation circuit provided in an embodiment of the present invention;

[0071] Figure 14 A schematic diagram of a falling edge interleaved enable delay signal generation circuit provided in an embodiment of the present invention;

[0072] Figure 15 This is a schematic diagram of a signal generation sub-circuit provided in an embodiment of the present invention;

[0073] Figure 16 This is a schematic diagram of another signal generation sub-circuit provided in an embodiment of the present invention;

[0074] Figure 17 A waveform diagram of an interleaved signal provided in an embodiment of the present invention;

[0075] Figure 18 This is a schematic diagram of another signal generation sub-circuit provided in an embodiment of the present invention;

[0076] Figure 19 A waveform diagram of another interleaved signal provided in an embodiment of the present invention;

[0077] Figure 20 This is a schematic diagram of another signal generation sub-circuit provided in an embodiment of the present invention;

[0078] Figure 21 A waveform diagram of another interleaved signal provided in an embodiment of the present invention;

[0079] Figure 22 This is a schematic diagram of another signal generation sub-circuit provided in an embodiment of the present invention;

[0080] Figure 23 This is a waveform diagram of another interleaved signal provided in an embodiment of the present invention. Detailed Implementation

[0081] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0082] This application provides an interleaved signal generation circuit and an integrated chip to solve the problem of poor flexibility in existing interleaved signal generation circuits.

[0083] The interleaved signal generation circuit and the integrated chip are based on the same inventive concept. Since the interleaved signal generation circuit and the integrated chip solve technical problems in similar ways, the implementation of the signal interleaved generation circuit and the integrated chip can refer to each other, and the repeated parts will not be described again.

[0084] In the detailed description of the following embodiments, it should be noted that "multiple" in this application refers to two or more. The term "or" in this application describes the relationship between related objects, indicating that three relationships can exist. For example, A or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The term "connection" in this application describes the connection relationship between two objects, which can represent two connection relationships. For example, A and B are connected, indicating: A and B are directly connected, or A is connected to B through C. Furthermore, it should be understood that in the description of this application, terms such as "first," "second," "third," etc., are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order.

[0085] like Figure 1The diagram shown is a schematic diagram of an interleaved signal generation circuit provided in an embodiment of the present invention, including a pulse generation circuit 10, a counting circuit 20, and a signal generation circuit 30.

[0086] The pulse generation circuit 10 is used to generate a first-cycle pulse signal ActCkN and a second-cycle pulse signal PrechgCkN based on the initial signal ActEn.

[0087] The counting circuit 20 is used to count the first periodic pulse signal ActCkN and the second periodic pulse signal PrechgCkN, and generate a rising edge trigger signal CntActN and a falling edge trigger signal CntPreN;

[0088] The signal generation circuit 30 is used to generate an interleaved pulse signal Pwl based on the input rising edge trigger signal CntActN and the input falling edge trigger signal CntPrechgN.

[0089] In this embodiment of the invention, the counting circuit counts the first period pulse signal and the second period pulse signal to generate a rising edge trigger signal and a falling edge trigger signal. The signal generation circuit generates an interleaved pulse signal based on the input rising edge trigger signal and the input falling edge trigger signal. Since the interval between the rising edge trigger signals input to each signal generation circuit can be the same or different, and the interval between the rising edge trigger signal and the falling edge trigger signal input to each signal generation circuit can be the same or different, the pulse width and spacing of the resulting interleaved pulse signal can be flexibly set, thereby improving the flexibility of the interleaved pulse signal generation circuit.

[0090] In a specific implementation, the pulse generation circuit 10 may include a first period pulse signal generation circuit and a second period pulse signal generation circuit.

[0091] The first cycle pulse signal generation circuit is used to generate the first cycle pulse signal ActCkN based on the initial signal ActEn and the first control signal.

[0092] The falling edge clock signal generation circuit generates the second cycle pulse signal PrechgCkN based on the initial signal ActEn and the second control signal.

[0093] The first control signal may include a rising edge interleaving enable signal FnstaggerActEn, a rising edge interleaving delay adjustment signal FnAdjActStaggerDly, and a rising edge interleaving delay adjustment inverse signal FnAdjActStaggerDlyN. The second control signal may include a falling edge interleaving enable signal FnstaggerPrechgEn, a rising edge interleaving delay adjustment signal FnAdjActStaggerDly, a rising edge interleaving delay adjustment inverse signal FnAdjActStaggerDlyN, and a falling edge enable signal PreEn.

[0094] Specifically, such as Figure 2 The diagram shown is a schematic diagram of the first periodic pulse signal generation circuit provided in an embodiment of the present invention.

[0095] The rising edge clock signal generation circuit may include a first oscillator 201 and a third NOT gate INV3;

[0096] The first input terminal of the first oscillator 201 is used to input the initial signal ActEn, the second input terminal of the first oscillator 201 is used to input the rising edge interleaving enable signal FnStaggerActEn, the third input terminal of the first oscillator 201 is used to input the rising edge interleaving adjustment delay signal FnAdjActStaggerDly, the fourth input terminal of the first oscillator 201 is used to input the rising edge interleaving adjustment delay inverse signal FnAdjActStaggerDlyN, the output terminal of the first oscillator 201 is connected to the input terminal of the third NOT gate INV3, and is used to output the rising edge clock signal ActClk; the output terminal of the third NOT gate INV3 is used to output the first period pulse signal ActCkN.

[0097] like Figure 3 The diagram shown is a schematic diagram of a second-cycle pulse signal generation circuit provided in an embodiment of the present invention.

[0098] The second-cycle pulse signal generation circuit may include a second oscillator 202, a fourth NOT gate INV4, and a first NAND gate AN1;

[0099] The input terminal of the fourth NOT gate INV4 is used to input the initial signal ActEn, and the output terminal of the fourth NOT gate INV4 is connected to the first input terminal of the second oscillator 202 to output the inverted signal PrechgEn of the initial signal.

[0100] The second input terminal of the second oscillator 202 is used to input the falling edge interleaving enable signal FnStaggerPreEn, the third input terminal of the second oscillator 202 is used to input the rising edge interleaving adjustment delay signal FnAdjActStaggerDly, the fourth input terminal of the second oscillator 202 is used to input the rising edge interleaving adjustment delay inverse signal FnAdjActStaggerDlyN, and the output terminal of the second oscillator 202 is connected to the first input terminal of the first NAND gate AN1 to output the falling edge clock signal PrechgClk;

[0101] The second input terminal of the first NAND gate AN1 is used to input the falling edge enable signal PreEn, and the output terminal of the first NAND gate AN1 is used to output the second period pulse signal PrechgCkN.

[0102] In this embodiment of the invention, the specific structures of the first oscillator 201 and the second oscillator 202 can be the same; specifically, refer to... Figure 4 The oscillator structure shown.

[0103] like Figure 4 The diagram shown is a structural schematic of an oscillator provided in an embodiment of the present invention.

[0104] The oscillator may include a fifth NAND gate AN5, a sixth NAND gate AN6, a fourteenth NOT gate INV14, a fifteenth NOT gate INV15, a sixteenth NOT gate INV16, a seventeenth NOT gate INV17, an eighteenth NOT gate INV18, a nineteenth NOT gate INV19, a twentieth NOT gate INV20, a twenty-first NOT gate INV21, a twenty-second NOT gate INV22, a first selector Mul1, a second selector Mul2, a third selector Mul3, a first flip-flop DFF1, a second flip-flop DFF2, a third flip-flop DFF3, a ninth delay 409, a tenth delay 410, an eleventh delay 411, a twelfth delay 412, and a first pulse conversion unit 413;

[0105] The first input of the fifth NAND gate AN5 is connected to the output of the sixteenth NOT gate INV16. The second input of the fifth NAND gate AN5 serves as the first input of the oscillator. The output of the fifth NAND gate AN5 is connected to the first input of the sixth NAND gate AN6 to output the delay signal Osc0. The second input of the sixth NAND gate AN6, the RN terminals of the first flip-flop DFF1, the second flip-flop DFF2, and the third flip-flop DFF3 serve as the second input of the oscillator. The output of the sixth NAND gate AN6 is connected to the input of the fourteenth NOT gate INV14. The output of the fourteenth NOT gate INV14 is connected to the first NAND gate AN6. The input of the 15th NOT gate INV15 is connected to output a delayed inverted signal Osc0N; the output of the 15th NOT gate INV15 is connected to the first input of the first selector Mul1 and the input of the ninth delay unit 409; the output of the ninth delay unit 409 is connected to the second input of the first selector Mul1; the output of the first selector Mul1 is connected to the first input of the second selector Mul2 and the input of the tenth delay unit 410; the first control terminal of the first selector Mul1 serves as the third input of the oscillator, used to input the first rising edge interleaved adjustment delay signal FnAdjActStaggerDly. <0> The second control terminal of the first selector Mul1 serves as the fourth input terminal of the oscillator, used to input the first rising edge interleaved adjustment delay inverse signal FnAdjActStaggerDlyN. <0> The output of the tenth delay unit 410 is connected to the second input of the second selector Mul2; the output of the second selector Mul2 is connected to the input of the eleventh delay unit 411; the first control terminal of the second selector Mul2 serves as the third input of the oscillator, used to input the second rising edge interleaved adjustment delay signal FnAdjActStaggerDly. <1> The second control terminal of the second selector Mul2 serves as the fourth input terminal of the oscillator, used to input the second rising edge interleaved adjustment delay inverse signal FnAdjActStaggerDlyN. <1> The output of the eleventh delay unit 411 is connected to the input of the twelfth delay unit 412; the output of the twelfth delay unit 412 is connected to the input of the sixteenth NOT gate INV16.

[0106] The D input of the first flip-flop DFF1 is connected to the output of the seventeenth NOT gate INV17 and the ClkN input of the second flip-flop DFF2. The Clk input of the first flip-flop DFF1 is used to input the delay signal Osc0, and the ClkN input of the first flip-flop DFF1 is used to input the delay inverted signal Osc0N. The Q input of the first flip-flop DFF1 is connected to the input of the seventeenth NOT gate INV7 and the Clk input of the second flip-flop DFF2. The D input of the second flip-flop DFF2 is connected to the output of the eighteenth NOT gate INV18 and the ClkN input of the third flip-flop DFF3. The Q input of the second flip-flop DFF2 is connected to the input of the eighteenth NOT gate INV18 and the ClkN input of the third flip-flop DFF3. The Clk terminal of FF3 is connected to the first input terminal of the third selector Mul3; the D terminal of the third flip-flop DFF3 is connected to the output terminal of the nineteenth NOT gate INV19, and the Q terminal of the third flip-flop DFF3 is connected to the input terminal of the nineteenth NOT gate INV19 and the second input terminal of the third selector Mul3; the output terminal of the third selector Mul3 is connected to the input terminal of the first pulse conversion unit 413, and the output terminal of the first pulse conversion unit 413 is connected to the input terminal of the twentieth NOT gate INV20; the first control terminal of the third selector Mul3 serves as the third input terminal of the oscillator, used to input the third rising edge interleaved adjustment delay signal FnAdjActStaggerDly. <2> The second control terminal of the third selector Mul3 serves as the fourth input terminal of the oscillator, used to input the third rising edge interleaved adjustment delay inverse signal FnAdjActStaggerDlyN. <2> The output of the 20th NOT gate INV20 is connected to the input of the 21st NOT gate INV21; the output of the 21st NOT gate INV21 is connected to the input of the 22nd NOT gate INV22; the output of the 22nd NOT gate INV22 serves as the output of the oscillator.

[0107] In one embodiment, such as Figure 5 As shown, the interleaved signal generation circuit provided in this embodiment of the invention may further include a fifth NOT gate INV5 and a fourth flip-flop DFF4;

[0108] The input of the fifth NOT gate INV5 is connected to the clock Clk terminal of the fourth flip-flop DFF4 to input the first original signal ActEnPlaN. The output of the fifth NOT gate INV5 is connected to the inverted clock ClkN terminal of the fourth flip-flop DFF4.

[0109] The input D terminal of the fourth flip-flop DFF4 is grounded. The asynchronous reset RN terminal of the fourth flip-flop DFF4 is used to input the rising edge interleaved enable signal FnStaggerActEn. The output Q terminal of the fourth flip-flop DFF4 is used to output the falling edge enable signal PreEn.

[0110] In specific implementations, embodiments of the present invention also include a rising edge interleaved enable signal generation circuit, a falling edge interleaved enable signal generation circuit, a rising edge interleaved adjustment delay signal generation circuit, and a rising edge interleaved adjustment delay inverse signal generation circuit.

[0111] The rising edge interleaved enable signal circuit is used to generate the rising edge interleaved enable signal FnStaggerActEn based on the second original signal FnCoreActAllBnk and the third original signal Burnin.

[0112] The falling edge interleaved enable signal generation circuit is used to generate the falling edge interleaved enable signal FnStaggerPreEn based on the fourth original signal RosEnBnki and the rising edge interleaved enable signal FnStaggerActEn.

[0113] The circuit for generating rising edge interleaved adjustment delay signal and rising edge interleaved adjustment delay inverse signal is used to generate rising edge interleaved adjustment delay inverse signal FnAdjActStaggerDlyN and rising edge interleaved adjustment delay signal FnAdjActStaggerDly based on the rising edge interleaved delay signal ActStaggerDly.

[0114] like Figure 6 The diagram shown is a schematic diagram of a rising edge interleaved enable signal generation circuit provided in an embodiment of the present invention.

[0115] The rising edge interleaved enable signal generation circuit includes a second NAND gate AN2 and a sixth NOT gate INV6;

[0116] The first input terminal of the second NAND gate AN2 is used to input the second original signal FnCoreActAllBnk, the second input terminal of the second NAND gate AN2 is used to input the third original signal Burnin, the output terminal of the second NAND gate AN2 is connected to the input terminal of the sixth NOT gate INV6, and the output terminal of the sixth NOT gate INV6 is used to output the rising edge interleaved enable signal FnStagerActEn.

[0117] like Figure 7 The diagram shown is a schematic diagram of a falling edge interleaved enable signal generation circuit provided in an embodiment of the present invention.

[0118] The falling edge interleaved enable signal generation circuit includes a third NAND gate AN3, a fourth NAND gate AN4, a seventh NOT gate INV7, an eighth NOT gate INV8, and a pulse conversion unit 1011;

[0119] The first input of the third NAND gate AN3 is used to input the fourth original signal RosEnBnki, the second input of the third NAND gate AN3 is used to input the rising edge interleaving enable signal FnStaggerActEn, and the output of the third NAND gate AN3 is connected to the input of the seventh NOT gate INV7.

[0120] The output of the seventh NOT gate INV7 is connected to the input of the pulse conversion unit 1011 and is used to output the initial signal ActEn.

[0121] The output of pulse conversion unit 1011 is connected to the first input of fourth NAND gate AN4;

[0122] The second input of the fourth NAND gate AN4 is used to input the rising edge interleaved enable signal FnStaggerActEn, and the output of the fourth NAND gate AN4 is connected to the input of the eighth NOT gate INV8.

[0123] The output of the eighth NOT gate INV8 is used to output the falling edge interleaved enable signal FnStagePreEn.

[0124] like Figure 8 As shown, this is a circuit for generating a rising edge interleaved adjustment delay signal and a rising edge interleaved adjustment delay inverse signal, provided in an embodiment of the present invention.

[0125] The circuit for generating rising edge interleaved adjustment delay signal and rising edge interleaved adjustment delay inverse signal includes the ninth NOT gate INV9 and the tenth NOT gate INV10;

[0126] The input of the ninth NOT gate INV9 is used to input ActStaggerDly. The output of the ninth NOT gate INV9 is connected to the input of the tenth NOT gate INV10 to output the rising edge interleaved adjustment delay inverted signal FnAdjActStaggerDlyN. The output of the tenth NOT gate INV10 is used to output the rising edge interleaved adjustment delay signal FnAdjActStaggerDly.

[0127] The following explanation, using waveform diagrams, covers the initial signal ActEn, the rising edge clock signal ActClk, the falling edge clock signal PrechgClk, the first cycle pulse signal ActCkN, and the second cycle pulse signal PrechgCkN.

[0128] like Figure 9As shown, the initial signal ActEn includes a rising edge and a falling edge. The first pulse in the rising edge clock signal ActClk occurs at the rising edge of the initial signal ActEn, and then a pulse is generated at each delay time. Similarly, the first pulse in the falling edge clock signal PreClk occurs at the falling edge of the initial signal ActEn, and then a pulse is generated at each delay time. The time interval between the first and last pulses in the rising edge clock signal ActClk is the same as the time interval between the rising and falling edges of the initial signal ActEn, and the time interval between the first and last pulses in the falling edge clock signal PreClk is the same as the time interval between the rising and falling edges of the initial signal ActEn.

[0129] from Figure 9 As can be seen from the data, the first-cycle pulse signal ActCkN is the inverted signal of the rising edge clock signal ActClk, and the second-cycle pulse signal is the inverted signal of the falling edge clock signal PreClk.

[0130] In the above embodiment, a first periodic pulse signal and a second periodic pulse signal are generated based on the initial signal. Then, the first periodic pulse signal and the second periodic pulse signal are counted. The following explains how to count the first periodic pulse signal and the second periodic pulse signal.

[0131] The counting circuit provided in this embodiment of the invention includes multiple rising edge trigger signal generation circuits and multiple falling edge trigger signal generation circuits that can be connected in series.

[0132] The number of rising edge trigger signal generation circuits is the same as the number of falling edge trigger signal generation circuits.

[0133] For each rising edge trigger signal generation circuit, a rising edge trigger signal CntActN is generated based on the first period pulse signal ActCkN, the rising edge interleaving enable delay signal FnStaggerActEnDly, the rising edge interleaving enable signal FnStaggerActEn, the supply voltage, and the rising edge count signal CntAct output by the previous rising edge trigger signal generation circuit connected to the rising edge trigger signal generation circuit.

[0134] For each falling edge trigger signal generation circuit, a falling edge trigger signal CntPreN is generated based on the second period pulse signal PrechgCkN, the falling edge interleaved pulse delay signal fnStaggerPrechgEnDly, the falling edge interleaved enable signal fnStaggerPrechgEn, the supply voltage, and the falling edge count signal CntPre output by the previous falling edge trigger signal generation circuit connected in series with the falling edge trigger signal generation circuit.

[0135] The rising edge trigger signal generation circuit and the falling edge trigger signal generation circuit are described in detail below.

[0136] like Figure 10 The diagram shown is a schematic diagram of the rising edge trigger signal generation circuit provided in an embodiment of the present invention.

[0137] The rising edge trigger signal generation circuit may include a first counter 101 and an eleventh NOT gate INV11;

[0138] The first input terminal of the first counter 101 is used to input the first period pulse signal ActCkN, the second input terminal of the first counter 101 is used to input the rising edge interleaving enable delay signal FnStaggerActEnDly, the third input terminal of the first counter 101 is used to input the power supply voltage VSS or the rising edge counting signal CntAct output by the previous first counter 101 connected to the first counter 101, the fourth input terminal of the first counter 101 is used to input the rising edge interleaving enable signal FnStaggerActEn, the fifth input terminal of the first counter 101 is used to input the power supply voltage VSS, and the output terminal of the first counter 101 is connected to the third input terminal of the next first counter 101 and the input terminal of the eleventh NOT gate INV11 to output the rising edge counting signal CntAct;

[0139] The output of the eleventh NOT gate INV11 is used to output the rising edge trigger signal CntActN.

[0140] It should be noted that, Figure 10 In the middle, CntAct<7:0> represents 8 CntActs, i.e., CntAct <0> CntAct <1> CntAct <2> CntAct <3> CntAct <4> CntAct <5> CntAct <6> CntAct <7> That is, there are 8 rising edge clock counting circuits. The third input terminal of the first counter in the first rising edge counting circuit, namely the In terminal, is connected to the power supply voltage VSS. The output terminal of the first counter in the second rising edge counting circuit is connected to the third input terminal of the first counter in the first rising edge trigger signal generation circuit, and so on.

[0141] like Figure 11 The diagram shown is a schematic diagram of the falling edge trigger signal generation circuit provided in an embodiment of the present invention.

[0142] The falling edge trigger signal generation circuit may include a second counter 102 and a twelfth NOT gate INV12;

[0143] The first input terminal of the second counter 102 is used to input the second period pulse signal PreCkN. The second input terminal of the second counter 102 is used to input the falling edge interleaving enable delay signal FnStaggerPreEnDly. The third input terminal of the second counter 102 is used to input the power supply voltage VSS or the falling edge counting signal CntPre output by the previous second counter 102 connected to this second counter 102. The fourth input terminal of the second counter 102 is used to input the falling edge interleaving enable signal FnStaggerPreEn. The fifth input terminal of the second counter 102 is used to input the power supply voltage VSS. The output terminal of the second counter 102 is connected to the input terminal of the twelfth NOT gate INV12 and is used to output the falling edge counting signal CntPre.

[0144] The output of the twelfth NOT gate INV12 is used to output the falling edge trigger signal CntPreN.

[0145] It should be noted that, Figure 11 In the middle, CntPre<7:0> means there are 8 CntPre, i.e., CntPre <0> CntPre <1> CntPret <2> CntPre <3> CntPre <4> CntPre <5> CntPre <6> CntPre <7> That is, there are 8 falling edge trigger signal generation circuits. The third input terminal of the second counter in the first falling edge trigger signal generation circuit, namely the In terminal, is input to VSS. The output terminal of the second counter in the second falling edge trigger signal generation circuit is connected to the third input terminal of the second counter in the first falling edge trigger signal generation circuit, and so on.

[0146] In specific implementations, the first counter 101 and the second counter 102 can be the same counter, such as... Figure 12 As shown, the counter may include the twenty-fourth NOT gate INV24, the twenty-fifth NOT gate INV25, the twenty-sixth NOT gate INV26, the twenty-seventh NOT gate INV27, the fifth flip-flop DFF5, and the fourth selector Mul4.

[0147] The input of the 24th NOT gate and the second control terminal of the fourth selector Mul4 serve as the En terminal of the counter. The output of the 24th NOT gate INV27 is connected to the first control terminal of the fourth selector Mul4. The input of the 25th NOT gate INV25 serves as the In terminal of the counter. The output of the 25th NOT gate INV25 is connected to the first input of the fourth selector Mul4. The input of the 26th NOT gate INV26 serves as the Temp terminal of the counter. The output of the 26th NOT gate INV26 is connected to the second input of the fourth selector Mul4. The input of the 27th NOT gate INV27 and the Clk terminal of the fifth flip-flop DFF5 serve as the Clk terminal of the counter. The output of the 27th NOT gate INV27 is connected to the ClkN terminal of the fifth flip-flop DFF5. The RN terminal of the fifth flip-flop DFF5 serves as the RN terminal of the counter. The Q terminal of the fifth flip-flop DFF5 serves as the Cnt terminal of the counter.

[0148] In the above embodiments, the counting circuit counts the first period pulse signal and the second period pulse signal to generate a rising edge trigger signal and a falling edge trigger signal. The signal generation circuit generates an interleaved pulse signal based on the input rising edge trigger signal and the input falling edge trigger signal.

[0149] The interleaved pulse signal generation circuit provided in this embodiment of the invention may further include a rising edge interleaved enable delay signal generation circuit and a falling edge interleaved enable delay signal generation circuit;

[0150] like Figure 13 As shown, the rising edge interleaved enable delay signal generation circuit may include a first delay unit 1301, a second delay unit 1302, a third delay unit 1303 and a fourth delay unit 1304.

[0151] The input terminal of the first delay unit 1301 is used to input the initial signal ActEn. The output terminal of the first delay unit 1301 is connected to the input terminal of the second delay unit 1302. The output terminal of the second delay unit 1302 is connected to the input terminal of the third delay unit 1303. The output terminal of the third delay unit 1303 is connected to the input terminal of the fourth delay unit 1304. The output terminal of the fourth delay unit 1304 is used to output the rising edge interleaved enable delay signal FnStaggerActEnDly.

[0152] like Figure 14 As shown, the falling edge interleaved enable delay signal generation circuit may include a fifth delay 1305, a sixth delay 1306, a seventh delay 1307, an eighth delay 1308, a NOR gate 1309, and a thirteenth NOT gate INV13.

[0153] The first input terminal of NOR gate 1309 is used to input the initial signal ActEn, the second input terminal of NOR gate 1309 is used to input the falling edge enable signal PreEn, the output terminal of NOR gate 1309 is connected to the input terminal of the thirteenth NOT gate INV13, the output terminal of the thirteenth NOT gate INV13 is connected to the input terminal of the fifth delay unit 1305, the output terminal of the fifth delay unit 1305 is connected to the input terminal of the sixth delay unit 1306, the output terminal of the sixth delay unit 1306 is connected to the input terminal of the seventh delay unit 1307, the output terminal of the seventh delay unit 1307 is connected to the input terminal of the eighth delay unit 1308, and the output terminal of the eighth delay unit 1308 is used to output the falling edge interleaved enable delay signal FnStaggerPreEnDly.

[0154] The signal generation circuit will be described in detail below.

[0155] The signal generation circuit provided in this embodiment of the invention may include multiple signal generation sub-circuits. Each signal generation sub-circuit is used to generate interleaved pulse sub-signals based on the input rising edge trigger signal and the input falling edge trigger signal. Multiple interleaved pulse sub-signals form an interleaved pulse signal.

[0156] In practical implementation, if the rising edge trigger signals of adjacent signal generation sub-circuits input to multiple signal generation sub-circuits have the same interval, the generated interleaved pulse signals are equally spaced interleaved pulse signals.

[0157] If the rising edge trigger signals of adjacent signal generation sub-circuits input to multiple signal generation sub-circuits have different intervals, the generated interleaved pulse signal is an interleaved pulse signal with non-equal intervals.

[0158] If the clock cycles between the rising edge trigger signal and the falling edge trigger signal input to each signal generation sub-circuit are the same, then the generated interleaved pulse signal is an interleaved pulse signal with equal pulse width.

[0159] If the clock cycles between the rising edge trigger signal and the corresponding falling edge trigger signal input to each signal generation sub-circuit are different, the generated interleaved pulse signal will be an interleaved pulse signal with non-uniform pulse width.

[0160] like Figure 15 The diagram shown is a schematic diagram of the signal generation sub-circuit provided in an embodiment of the present invention.

[0161] The signal generation sub-circuit may include an SR latch 1051, a first NOT gate INV1, and a second NOT gate INV2;

[0162] The first input terminal of the SR latch 1051 is used to input the rising edge trigger signal CntActN, the second input terminal of the SR latch 1051 is used to input the falling edge trigger signal CntPreN, and the third input terminal of the SR latch 1051 is used to input the rising edge interleaving enable signal FnStaggerActEn. The output terminal of the SR latch 1051 is connected to the input terminal of the first NOT gate INV1; the output terminal of the first NOT gate INV1 is connected to the input terminal of the second NOT gate INV2; and the output terminal of the second NOT gate INV2 outputs the interleaved pulse sub-signal Pwl(n).

[0163] For ease of understanding, the following explanations will cover interleaved pulse signals as equal-interval equal pulses, equal-interval non-equal pulses, non-equal-interval equal pulses, and non-equal-interval non-equal pulses.

[0164] Example 1:

[0165] like Figure 16 As shown, the rising edge trigger signal input to the first signal generation sub-circuit is CntActN. <0> The falling edge trigger signal is CntPreN <0> The rising edge trigger signal input to the second signal generation sub-circuit is CntActN. <1> The falling edge trigger signal is CntPreN <1> The rising edge trigger signal input to the third signal generation sub-circuit is CntActN. <2> The falling edge trigger signal is CntPreN <2> .

[0166] CntActN <0> and CntActN <1> The time interval between them is one period of the first period pulse signal, CntActN <1> and CntActN <2> The time interval is one period of the first period pulse signal. Therefore, the generated interleaved pulse signal is an equally spaced interleaved pulse signal.

[0167] CntActN <0> and CntPreN <0> The time interval between them is one period of the initial signal ActEn, CntActN <1> and CntPreN <1> The time interval between them is one period of the initial signal ActEn, CntActN <2> and CntPreN <2> The time interval between them is one cycle of the initial signal ActEn. Therefore, the generated interleaved pulse signal is an interleaved pulse signal with equal pulses.

[0168] It should be noted that the circuits for outputting interleaved sub-signals Pwl(1) and Pwl(2) are adjacent signal generation sub-circuits. The circuits for outputting interleaved sub-signals Pwl(2) and Pwl(3) are adjacent signal generation sub-circuits; CntActN <0> and CntActN <1> To generate a rising edge trigger signal in the sub-circuit for the input signal to the adjacent signal, CntActN <1> and CntActN <2> It also generates a rising edge trigger signal in the sub-circuit for input signals to adjacent signals; CntActN <0> and CntPreN <0> To generate a rising edge trigger signal and a corresponding falling edge trigger signal in a sub-circuit that is input to the same signal, CntActN <1> and CntPreN <1> To generate a rising edge trigger signal and a corresponding falling edge trigger signal in a sub-circuit that is input to the same signal, CntActN <2> and CntPreN <2> The rising edge trigger signal and its corresponding falling edge trigger signal are generated in the sub-circuit for input to the same signal.

[0169] like Figure 17 As shown, it is based on Figure 16 The waveform of the generated signal.

[0170] Assuming the clock period of the first pulse signal is t, and the period of the initial signal is T, then the interval between the interleaved pulse signals is t, and the pulse width is T. From Figure 17 As can be seen from the data, the interlaced pulse signal is an interlaced pulse signal with equal intervals and equal pulses.

[0171] Example 2:

[0172] like Figure 18 As shown, the rising edge trigger signal input to the first signal generation sub-circuit is CntActN. <0> The falling edge trigger signal is CntPreN <0> The rising edge trigger signal input to the second signal generation sub-circuit is CntActN. <2> The falling edge trigger signal is CntPreN <1> The rising edge trigger signal input to the third signal generation sub-circuit is CntActN. <5> The falling edge trigger signal is CntPreN <2> .

[0173] CntActN <0> and CntActN <2> The time interval between them is two cycles of the first period pulse signal, CntActN <2> and CntActN <5> The time interval is three cycles of the first period pulse signal. Therefore, the generated interleaved pulse signal is an interleaved pulse signal with non-equal intervals.

[0174] CntActN <0> and CntPreN <0> The time interval between them is one period of the initial signal ActEn, CntActN <2> and CntPreN <1> The time interval between them is one period of the initial signal ActEn minus the clock period of a falling edge inverted signal, CntActN. <5> and CntPreN <2> The time interval between them is one period of the initial signal ActEn minus the clock periods of three falling edge inverse signals. Therefore, the generated interleaved pulse signal is an interleaved pulse signal with non-equal pulses.

[0175] It should be noted that the circuits for outputting interleaved sub-signals Pwl(1) and Pwl(2) are adjacent signal generation sub-circuits. The circuits for outputting interleaved sub-signals Pwl(2) and Pwl(3) are adjacent signal generation sub-circuits; CntActN <0> and CntActN <2> To generate a rising edge trigger signal in the sub-circuit for the input signal to the adjacent signal, CntActN <2> and CntActN <5> It also generates a rising edge trigger signal in the sub-circuit for input signals to adjacent signals; CntActN <0> and CntPreN <0> To generate a rising edge trigger signal and its corresponding falling edge trigger signal in a sub-circuit that is input to the same signal, CntActN <2> and CntPreN <1> To generate a rising edge trigger signal and its corresponding falling edge trigger signal in a sub-circuit that is input to the same signal, CntActN <5> and CntPreN <2> The rising edge trigger signal and its corresponding falling edge trigger signal are generated in the sub-circuit for input to the same signal.

[0176] like Figure 19 As shown, it is based on Figure 18 The waveform of the generated signal.

[0177] Assume the clock period of the first pulse signal is t, the clock period of the falling edge inverted signal is also t, and the period of the initial signal is T. From Figure 17 As can be seen from this, the interlaced pulse signal is an interlaced pulse signal with non-equal intervals and non-equal pulses.

[0178] Example 3:

[0179] like Figure 20 As shown, the rising edge trigger signal input to the first signal generation sub-circuit is CntActN. <0> The falling edge trigger signal is CntPreN <0> The rising edge trigger signal input to the second signal generation sub-circuit is CntActN. <1> The falling edge trigger signal is CntPreN <2> The rising edge trigger signal input to the third signal generation sub-circuit is CntActN. <2> The falling edge trigger signal is CntPreN <5> .

[0180] CntActN <0> and CntActN <1> The time interval between them is one period of the first period pulse signal, CntActN <1> and CntActN <2> The time interval is one period of the first period pulse signal. Therefore, the generated interleaved pulse signal is an equally spaced interleaved pulse signal.

[0181] CntActN <0> and CntPreN <0> The time interval between them is one period of the initial signal ActEn, CntActN <1> and CntPreN <2> The time interval between them is one period of the initial signal ActEn plus the clock period of a falling edge inverted signal, CntActN <5> and CntPreN <2> The time interval between them is one cycle of the initial signal ActEn plus the clock cycles of three falling edge inverse signals. Therefore, the generated interleaved pulse signal is an interleaved pulse signal with non-equal pulses.

[0182] It should be noted that the circuits for outputting interleaved sub-signals Pwl(1) and Pwl(2) are adjacent signal generation sub-circuits. The circuits for outputting interleaved sub-signals Pwl(2) and Pwl(3) are adjacent signal generation sub-circuits; CntActN <0> and CntActN <1> To generate a rising edge trigger signal in the sub-circuit for the input signal to the adjacent signal, CntActN <1> and CntActN <2> It also generates a rising edge trigger signal in the sub-circuit for input signals to adjacent signals; CntActN <0> and CntPreN <0> To generate a rising edge trigger signal and its corresponding falling edge trigger signal in a sub-circuit that is input to the same signal, CntActN <1> and CntPreN <2> To generate a rising edge trigger signal and its corresponding falling edge trigger signal in a sub-circuit that is input to the same signal, CntActN <5> and CntPreN <2> The rising edge trigger signal and its corresponding falling edge trigger signal are generated in the sub-circuit for input to the same signal.

[0183] like Figure 21 As shown, it is based on Figure 20 The waveform of the generated signal.

[0184] Assume the clock period of the first pulse signal is t, the clock period of the falling edge inverted signal is also t, and the period of the initial signal is T. From Figure 21 As can be seen from this, the interlaced pulse signal is an interlaced pulse signal with equal intervals but unequal pulses.

[0185] Example 4:

[0186] like Figure 22As shown, the rising edge trigger signal input to the first signal generation sub-circuit is CntActN. <0> The falling edge trigger signal is CntPreN <0> The rising edge trigger signal input to the second signal generation sub-circuit is CntActN. <1> The falling edge trigger signal is CntPreN <1> The rising edge trigger signal input to the third signal generation sub-circuit is CntActN. <4> The falling edge trigger signal is CntPreN <4> .

[0187] CntActN <0> and CntActN <1> The time interval between them is one period of the first period pulse signal, CntActN <1> and CntActN <4> The time interval is three cycles of the first period pulse signal. Therefore, the generated interleaved pulse signal is an interleaved pulse signal with non-equal intervals.

[0188] CntActN <0> and CntPreN <0> The time interval between them is one period of the initial signal ActEn, CntActN <1> and CntPreN <1> The time interval between them is one period of the initial signal ActEn, CntActN <4> and CntPreN <4> The time interval between them is one cycle of the initial signal ActEn. Therefore, the generated interleaved pulse signal is an interleaved pulse signal with equal pulses.

[0189] It should be noted that the circuits for outputting interleaved sub-signals Pwl(1) and Pwl(2) are adjacent signal generation sub-circuits. The circuits for outputting interleaved sub-signals Pwl(2) and Pwl(3) are adjacent signal generation sub-circuits; CntActN <0> and CntActN <1> To generate a rising edge trigger signal in the sub-circuit for the input signal to the adjacent signal, CntActN <1> and CntActN <4> It also generates a rising edge trigger signal in the sub-circuit for input signals to adjacent signals; CntActN <0> and CntPreN <0> To generate a rising edge trigger signal and a corresponding falling edge trigger signal in a sub-circuit that is input to the same signal, CntActN <1> and CntPreN <1> To generate a rising edge trigger signal and a corresponding falling edge trigger signal in a sub-circuit that is input to the same signal, CntActN <4> and CntPreN <4> The rising edge trigger signal and its corresponding falling edge trigger signal are generated in the sub-circuit for input to the same signal.

[0190] like Figure 23 As shown, it is based on Figure 22 The waveform of the generated signal.

[0191] Assume the clock period of the first pulse signal is t, the clock period of the falling edge inverted signal is also t, and the period of the initial signal is T. From Figure 23 As can be seen from this, the interlaced pulse signal is an interlaced pulse signal with non-equal intervals and equal pulses.

[0192] The interleaved pulse signal generation circuit provided in this embodiment of the invention includes a counting circuit that counts the first and second period pulse signals to generate rising edge trigger signals and falling edge trigger signals. The signal generation circuit generates interleaved pulse signals based on the input rising edge trigger signals and the input falling edge trigger signals. Since the interval between the rising edge trigger signals input to each signal generation circuit can be the same or different, and the interval between the rising edge trigger signals and the falling edge trigger signals input to each signal generation circuit can be the same or different, the pulse width and spacing of the resulting interleaved pulse signals can be flexibly set, thereby improving the flexibility of the interleaved pulse signal generation circuit.

[0193] Based on the same inventive concept, embodiments of the present invention also provide an integrated chip, which includes any of the above-described interleaved signal generation circuits.

[0194] For details on the implementation of the integrated chip, please refer to the implementation of the interleaved signal generation circuit, which will not be elaborated here.

[0195] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. An interleaved signal generation circuit, characterized in that, include: The pulse generation circuit is used to generate a first-cycle pulse signal and a second-cycle pulse signal based on the initial signal. A counting circuit is used to count the first periodic pulse signal and the second periodic pulse signal to generate multiple equally spaced rising edge trigger signals and equally spaced falling edge trigger signals. The signal generation circuit is used to generate interleaved pulse signals based on the input rising edge trigger signal and the input falling edge trigger signal; The pulse generation circuit includes a first period pulse signal generation circuit and a second period pulse signal generation circuit. The first periodic pulse signal generating circuit is used to generate the first periodic pulse signal based on the initial signal and the first control signal; The second periodic pulse signal generating circuit is used to generate the second periodic pulse signal based on the initial signal and the second control signal; The first periodic pulse signal generation circuit includes: a first oscillator and a third NOT gate; the first control signal includes a rising edge interleaving enable signal, a rising edge interleaving adjustment delay signal, and a rising edge interleaving adjustment delay inverse signal; The first input terminal of the first oscillator is used to input the initial signal, the second input terminal of the first oscillator is used to input the rising edge interleaving enable signal, the third input terminal of the first oscillator is used to input the rising edge interleaving adjustment delay signal, the fourth input terminal of the first oscillator is used to input the rising edge interleaving adjustment delay inverse signal, and the output terminal of the first oscillator is connected to the input terminal of the third NOT gate; the output terminal of the third NOT gate is used to output the first periodic pulse signal. The second periodic pulse signal generation circuit includes a second oscillator, a fourth NOT gate, and a first NAND gate; the second control signal includes a falling edge interleaved enable signal, a rising edge interleaved adjustment delay signal, a rising edge interleaved adjustment delay inverse signal, and a falling edge enable signal; The input terminal of the fourth NOT gate is used to input the initial signal, and the output terminal of the fourth NOT gate is connected to the first input terminal of the second oscillator; The second input terminal of the second oscillator is used to input the falling edge interleaving enable signal, the third input terminal of the second oscillator is used to input the rising edge interleaving adjustment delay signal, the fourth input terminal of the second oscillator is used to input the rising edge interleaving adjustment delay inverse signal, and the output terminal of the second oscillator is connected to the first input terminal of the first NAND gate; The second input terminal of the first NAND gate is used to input the falling edge enable signal, and the output terminal of the first NAND gate is used to output the second periodic pulse signal.

2. The circuit according to claim 1, characterized in that, The signal generation circuit includes multiple signal generation sub-circuits; Each signal generation sub-circuit is used to generate interleaved pulse sub-signals based on the input rising edge trigger signal and the input falling edge trigger signal; The interleaved pulse signal is composed of multiple interleaved pulse sub-signals.

3. The circuit according to claim 2, characterized in that, The signal generation sub-circuit includes an SR latch, a first NOT gate, and a second NOT gate. The first input terminal of the SR latch is used to input a rising edge trigger signal, the second input terminal of the SR latch is used to input a falling edge trigger signal, the third input terminal of the SR latch is used to input a rising edge interleaving enable signal, and the output terminal of the SR latch is connected to the input terminal of the first NOT gate. The output of the first NOT gate is connected to the input of the second NOT gate; The output of the second NOT gate is used to output the interleaved pulse sub-signal.

4. The circuit according to claim 2, characterized in that, If the rising edge trigger signals of adjacent signal generation sub-circuits input to multiple signal generation sub-circuits have the same interval, then the interleaved pulse signal is an equally spaced interleaved pulse signal. If the rising edge trigger signals of adjacent signal generation sub-circuits input to multiple signal generation sub-circuits have different intervals, then the interleaved pulse signal is an interleaved pulse signal with non-equal intervals. If the rising edge trigger signal and its corresponding falling edge trigger signal are at the same interval in each of the signal generation sub-circuits, then the interleaved pulse signal is an interleaved pulse signal with equal pulse width. If the interval between the rising edge trigger signal and its corresponding falling edge trigger signal input to each of the signal generation sub-circuits is different, then the interleaved pulse signal is an interleaved pulse signal with non-equal pulse width.

5. The circuit according to claim 1, characterized in that, It also includes the fifth NOT gate and flip-flops; The input terminal of the fifth NOT gate is connected to the clock terminal of the flip-flop to input the first original signal, and the output terminal of the fifth NOT gate is connected to the inverted clock terminal of the flip-flop. The input terminal of the flip-flop is grounded, the asynchronous reset terminal of the flip-flop is used to input the rising edge interleaved enable signal, and the output terminal of the flip-flop is used to output the falling edge enable signal.

6. The circuit according to claim 1, characterized in that, It also includes a second NAND gate, a third NAND gate, a fourth NAND gate, a sixth NOT gate, a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a tenth NOT gate, and a pulse conversion unit; The first input terminal of the second NAND gate is used to input the second original signal, the second input terminal of the second NAND gate is used to input the third original signal, and the output terminal of the second NAND gate is connected to the input terminal of the sixth NOT gate; The output of the sixth NOT gate is used to output a rising edge interleaved enable signal; The first input terminal of the third NAND gate is used to input the fourth original signal, the second input terminal of the third NAND gate is used to input the rising edge interleaved enable signal, and the output terminal of the third NAND gate is connected to the input terminal of the seventh NOT gate. The output of the seventh NOT gate is connected to the input of the pulse conversion unit; The output terminal of the pulse conversion unit is connected to the first input terminal of the fourth NAND gate; The second input terminal of the fourth NAND gate is used to input the rising edge interleaved enable signal, and the output terminal of the fourth NAND gate is connected to the input terminal of the eighth NOT gate. The output of the eighth NOT gate is used to output the falling edge interleaved enable signal; The input terminal of the ninth NOT gate is used to input the fifth original signal, and the output terminal of the ninth NOT gate is connected to the input terminal of the tenth NOT gate to output the rising edge interleaved adjustment delay inverse signal. The output of the tenth NOT gate is used to output the rising edge interleaved delay signal.

7. The circuit according to claim 1, characterized in that, The counting circuit includes multiple series-connected rising edge trigger signal generation circuits and multiple series-connected falling edge trigger signal generation circuits. A rising edge trigger signal generation circuit is used to generate the rising edge trigger signal based on the first periodic pulse signal, the rising edge interleaving enable delay signal, the rising edge interleaving enable signal, the supply voltage, and the rising edge counting signal output by the previous rising edge counting signal generation circuit connected to the rising edge trigger signal generation circuit. The falling edge trigger signal generation circuit is used to generate the falling edge trigger signal based on the second periodic pulse signal, the falling edge interleaving enable delay signal, the falling edge interleaving enable signal, the power supply voltage, and the falling edge count signal output by the previous falling edge count signal generation circuit connected to the falling edge trigger signal generation circuit.

8. The circuit according to claim 7, characterized in that, The rising edge trigger signal generation circuit includes a first counter and an eleventh NOT gate; The first input terminal of the first counter is used to input the first periodic pulse signal, the second input terminal of the first counter is used to input the rising edge interleaving enable delay signal, the third input terminal of the first counter is used to input the power supply voltage or the rising edge counting signal output by the previous first counter connected to the first counter, the fourth input terminal of the first counter is used to input the rising edge interleaving enable signal, the fifth input terminal of the first counter is used to input the power supply voltage, and the output terminal of the first counter is connected to the third input terminal of the next first counter and the input terminal of the eleventh NOT gate to output the rising edge counting signal. The output of the eleventh NOT gate is used to output the rising edge trigger signal; The falling edge trigger signal generation circuit includes a second counter and a twelfth NOT gate; The first input terminal of the second counter is used to input the second periodic pulse signal, the second input terminal of the second counter is used to input the falling edge interleaving enable delay signal, the third input terminal of the second counter is used to input VSS or the falling edge counting signal output by the previous second counter connected to the second counter, the fourth input terminal of the second counter is used to input the falling edge interleaving enable signal, the fifth input terminal of the second counter is used to input the power supply voltage, and the output terminal of the second counter is connected to the input terminal of the twelfth NOT gate to output the falling edge trigger signal; The output of the twelfth NOT gate is used to output the falling edge trigger signal.

9. The circuit according to claim 8, characterized in that, It also includes the first delay, the second delay, the third delay, the fourth delay, the fifth delay, the sixth delay, the seventh delay, the eighth delay, the NOR gate, and the thirteenth NOT gate; The input terminal of the first delay is used to input the initial signal. The output terminal of the first delay is connected to the input terminal of the second delay. The output terminal of the second delay is connected to the input terminal of the third delay. The output terminal of the third delay is connected to the input terminal of the fourth delay. The output terminal of the fourth delay is used to output the rising edge interleaved enable delay signal. The first input terminal of the NOR gate is used to input the initial signal, the second input terminal of the NOR gate is used to input the falling edge enable signal, the output terminal of the NOR gate is connected to the input terminal of the thirteenth NOT gate, the output terminal of the thirteenth NOT gate is connected to the input terminal of the fifth delay, the output terminal of the fifth delay is connected to the input terminal of the sixth delay, the output terminal of the sixth delay is connected to the input terminal of the seventh delay, the output terminal of the seventh delay is connected to the input terminal of the eighth delay, and the output terminal of the eighth delay is used to output the falling edge interleaved enable delay signal.

10. An integrated chip, characterized in that, Includes the interleaved signal generation circuit as described in any one of claims 1-9.

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