Testing method, testing circuit, controller, and semiconductor memory

Abstract

The present application provides a testing method, a testing circuit, a controller, and a semiconductor memory. A positive bias voltage is applied to the gate at a preset temperature to control the accumulation of mobile ion charges in the gate oxide layer at the interface between the substrate and the gate oxide layer, so that the excess charges in the gate oxide layer can all be treated as interface traps. A perturbation signal is applied to the gate at the preset temperature, and at the preset temperature, the semiconductor approaches the intrinsic state and the depletion layer capacitance approaches infinity, so that the capacitance characteristics of the metal oxide semiconductor are only manifested as the gate oxide layer capacitance. When the perturbation signal is applied to the gate, the external circuit current of the transistor is measured. The perturbation signal is used to control the displacement current of the gate oxide layer to be equivalent to the external circuit current of the transistor, and the capacitance of the gate oxide layer is calculated according to the external circuit current of the transistor and the perturbation signal, thereby avoiding the influence of non-ideal charges on the capacitance of the gate oxide layer and accurately testing the capacitance of the gate oxide layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a testing method, a testing circuit, a controller, and a semiconductor memory. Background Art

[0002] The gate oxide capacitance Coxide is an important device parameter. Currently, the test of gate oxide capacitance is mainly based on the absence of depletion layer capacitance C in the multi-carrier accumulation region. S The capacitance characteristic of a metal oxide semiconductor (MIS) is approximately the gate oxide capacitance Coxide.

[0003] However, the gate oxide layer of an actual metal oxide semiconductor has non-ideal charges such as interface states and fixed / mobile ion charges, which affect the test results of the gate oxide layer capacitance. Summary of the Invention

[0004] The present application provides a testing method, a testing circuit, a controller and a semiconductor memory, which avoid the influence of non-ideal charge on the gate oxide layer and accurately test the gate oxide layer capacitance.

[0005] In a first aspect, the present application provides a testing method, comprising:

[0006] applying a positive bias voltage to the gate of the transistor at a preset temperature to control mobile ionic charges in the gate oxide layer of the transistor to accumulate at an interface between the substrate and the gate oxide layer of the transistor;

[0007] applying a disturbance signal to the gate at the preset temperature to test the external circuit current of the transistor, wherein the disturbance signal is used to control the displacement current of the gate oxide layer to be equivalent to the external circuit current of the transistor;

[0008] The capacitance of the gate oxide layer is calculated according to the external circuit current of the transistor and the disturbance signal.

[0009] Optionally, the frequency of the disturbance signal is greater than or equal to a preset frequency.

[0010] Optionally, the disturbance signal is a disturbance voltage;

[0011] Calculating the capacitance of the gate oxide layer according to the external circuit current of the transistor and the disturbance signal specifically includes:

[0012] The capacitance of the gate oxide layer is calculated according to the external circuit current of the transistor and the angular frequency of the disturbance voltage.

[0013] Optionally, applying a positive bias voltage to the gate of the transistor at the preset temperature specifically includes:

[0014] Obtaining the temperature at which the mobile ion charges move and the semiconductor intrinsic state temperature of the substrate at the target doping concentration;

[0015] Selecting the highest temperature among the temperature at which the mobile ion charges move and the semiconductor intrinsic state temperature as the preset temperature;

[0016] Applying a positive bias voltage to the gate of the transistor at the preset temperature.

[0017] Optionally, applying a positive bias voltage to the gate of the transistor at the preset temperature specifically includes:

[0018] Applying a positive bias voltage to the gate of the transistor at the preset temperature for a preset time.

[0019] Optionally, applying a perturbation signal to the gate at the preset temperature specifically includes:

[0020] On the basis of applying a preset bias voltage to the gate at the preset temperature, applying a perturbation voltage to the gate.

[0021] Optionally, the preset bias voltage is less than the positive bias voltage.

[0022] Optionally, the frequency of the perturbation signal is equal to the highest frequency of the device applying the perturbation signal.

[0023] Optionally, the positive bias voltage is less than the breakdown voltage of the transistor.

[0024] In a second aspect, the present application provides a test circuit, and the test circuit includes:

[0025] A capacitance module, an equivalent resistor, and a test module;

[0026] The capacitance module is equivalent to the capacitance of the metal oxide semiconductor formed by the gate, the gate oxide layer, and the substrate of the transistor when a positive bias voltage is applied to the gate of the transistor at a preset temperature;

[0027] The equivalent resistor is equivalent to the resistance of the gate oxide layer;

[0028] The test module is configured to test the currents of the capacitance module and the equivalent resistor, and calculate the capacitance of the gate oxide layer according to the tested currents and a perturbation signal, where the perturbation signal is used to control the displacement current of the gate oxide layer to be equivalent to the current tested by the test module.

[0029] Optionally, the capacitance module includes a first equivalent capacitance, a second equivalent capacitance, and a third equivalent capacitance;

[0030] A first end of the first equivalent capacitance is connected to a first end of the second equivalent capacitance, and a second end of the first equivalent capacitance is connected to a second end of the second equivalent capacitance to serve as a second end of the capacitance module. A second end of the third equivalent capacitance is connected to the first end of the first equivalent capacitance and the first end of the second equivalent capacitance, and a first end of the third capacitance serves as a first end of the capacitance module;

[0031] The first equivalent capacitance is equivalent to the depletion layer capacitance of the transistor when a positive bias voltage is applied to the gate of the transistor at a preset temperature;

[0032] The second equivalent capacitance is equivalent to the surface state capacitance of the transistor;

[0033] The third equivalent capacitance is equivalent to the gate oxide capacitance of the transistor when a disturbance signal is applied to the gate at the preset temperature after a positive bias voltage is applied to the gate at the preset temperature, and the frequency of the disturbance signal is greater than or equal to a preset value.

[0034] Optionally, a first end of the equivalent resistance is connected to a first end of the third equivalent capacitance, and a second end of the equivalent resistance is connected to a second end of the first equivalent capacitance and a second end of the second equivalent capacitance;

[0035] A first end of the test module is connected to a first end of the third equivalent capacitance, and a second end of the test module is connected to a second end of the first equivalent capacitance and a second end of the second equivalent capacitance.

[0036] Optionally, the disturbance signal is a disturbance voltage;

[0037] The test module is configured to test the current of the capacitance module and calculate the third equivalent capacitance according to the current of the capacitance module and the angular frequency of the disturbance voltage.

[0038] In a third aspect, the present application provides a controller for implementing the above test method.

[0039] In a fourth aspect, the present application provides a semiconductor memory including the above test circuit.

[0040] The test method provided by this application applies a positive bias voltage to the gate of a transistor at a preset temperature, controls the accumulation of mobile ion charges in the gate oxide layer of the transistor at the interface between the substrate and the gate oxide layer, so that the excess charges in the gate oxide layer can all be treated as interface traps. Then, while maintaining this preset temperature, a perturbation signal is applied to the gate at the preset temperature. Since the semiconductor approaches the intrinsic state at the preset temperature, the depletion layer capacitance approaches infinity, resulting in a short circuit of the depletion layer capacitance, and making the capacitance characteristics of the metal-oxide semiconductor only exhibit the gate oxide layer capacitance. And when applying the perturbation signal to the gate, the external circuit current of the transistor is measured. The perturbation signal is used to control the displacement current of the gate oxide layer, which is equivalent to the external circuit current of the transistor. Therefore, the capacitance of the gate oxide layer can be calculated according to the external circuit current of the transistor and the perturbation signal, so as to avoid the influence of non-ideal charges on the capacitance of the gate oxide layer and accurately test the capacitance of the gate oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0042] Figure 1 It is the energy band diagram of an ideal metal-oxide semiconductor structure when an external bias negative voltage is applied;

[0043] Figure 2 It is the energy band diagram of an ideal metal-oxide semiconductor structure when an external bias positive voltage is applied;

[0044] Figure 3 It is the equivalent circuit diagram of an ideal metal-oxide semiconductor structure when an external bias positive voltage is applied;

[0045] Figure 4 It is the flowchart of a test method provided by an embodiment of this application;

[0046] Figure 5 It is the structural schematic diagram of a transistor provided by an embodiment of this application;

[0047] Figure 6 It is the equivalent circuit diagram of a transistor provided by an embodiment of this application when an external positive bias voltage is applied;

[0048] Figure 7 It is the equivalent circuit diagram of the external circuit of a transistor provided by an embodiment of this application;

[0049] Figure 8 It is the circuit diagram of a test circuit provided by an embodiment of this application. Detailed implementation manners

[0050] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings in the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the protection scope of the present application.

[0051] Those skilled in the art will readily conceive of other implementation manners of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the claims above.

[0052] The metal oxide semiconductor (Metal Insulator Semiconduction) structure is an insulating layer sandwiched between a metal layer and a semiconductor layer.

[0053] Figure 1 Figure [0000142] is the energy band diagram of an ideal metal oxide semiconductor structure when a negative bias voltage is applied. Refer to Figure 1 As shown, the semiconductor in the metal oxide semiconductor structure is a p-type semiconductor. When the applied bias voltage Vg is a negative voltage, a large number of holes in the semiconductor layer are attracted to the semiconductor surface. Due to the blocking effect of the insulating layer, the holes in the semiconductor layer accumulate on the semiconductor layer surface. At this time, the metal oxide semiconductor is in the accumulation state (Accumulation), and the capacitance of the metal oxide semiconductor is equivalent to the parallel plate capacitance Cox of the insulating layer, and the capacitance value does not change with the change of the applied bias voltage.

[0054] Figure 2 Figure [0000146] is the energy band diagram of an ideal metal oxide semiconductor structure when a positive bias voltage is applied. Refer to Figure 2 As shown, when the applied bias voltage Vg is a positive voltage, the holes in the semiconductor move away from the semiconductor surface, and hole depletion appears on the semiconductor surface. Figure 3 Figure [0000148] is the equivalent circuit diagram of an ideal metal oxide semiconductor structure when a positive bias voltage is applied. As Figure 3 shown, the insulating layer is in series with the space charge region capacitance, and the space charge region capacitance is the depletion layer capacitance. Then, the capacitance characteristic of the ideal metal oxide semiconductor is the series connection of the insulating layer capacitance and the depletion layer capacitance.

[0055] Therefore, for a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), its gate, insulating layer, and substrate form a metal-oxide semiconductor structure. The capacitance of a metal-oxide semiconductor field-effect transistor is composed of a series connection of an oxide layer capacitance and a depletion layer capacitance. The gate oxide layer capacitance is a fixed capacitance value, which is related to the thickness and area of the gate oxide layer capacitor plates. The depletion layer capacitance is a variable capacitance and is related to the operating state of the metal-oxide semiconductor transistor.

[0056] When the applied bias voltage is a negative voltage, the N-channel between the source and drain has not been formed, causing holes in the P-type substrate to accumulate under the gate oxide layer. At this time, the capacitance of the metal-oxide semiconductor field-effect transistor is the gate oxide layer capacitance. When the applied bias voltage is a positive voltage, the holes in the P-type substrate under the gate oxide layer are repelled, forming a depletion layer. The depletion layer is the space charge region, which is a region formed by the combination of electrons and holes. The space charge region is electrically neutral and is an insulator, thus forming a depletion layer capacitance. The depletion layer capacitance is in series with the gate oxide layer capacitance.

[0057] The gate oxide layer capacitance Coxide is an important device parameter. Currently, the measurement of the gate oxide layer capacitance Coxide is mainly based on the fact that there is no depletion layer capacitance C in the multi-carrier accumulation region. S The capacitance characteristics of a Metal Insulator Semiconductor (MIS) are approximately the gate oxide layer capacitance Coxide.

[0058] However, this requires scanning over a large potential range to find the multi-carrier accumulation region, and there are non-ideal charges such as interface states and fixed / mobile ion charges in the gate oxide layer of the actual metal-oxide semiconductor, which affect the test results of the gate oxide layer capacitance Coxide.

[0059] To this end, the present application provides a test method. A positive bias voltage is applied to the gate of a transistor at a preset temperature. The mobile ion charges in the gate oxide layer of the transistor move towards the interface between the substrate and the gate oxide layer under the action of the positive bias voltage and accumulate at the interface between the substrate and the gate oxide layer of the transistor. Then, the excess charges in the gate oxide layer can all be treated as interface traps. Since the semiconductor approaches the intrinsic state at the preset temperature, the depletion layer capacitance approaches infinity, resulting in a short circuit of the depletion layer capacitance, and making the capacitance characteristic of the metal oxide semiconductor only manifested as the gate oxide layer capacitance. Then, while maintaining this preset temperature, a perturbation signal is applied to the gate at the preset temperature, and the external circuit current of the transistor is measured when the perturbation signal is applied to the gate. The perturbation signal is used to control the displacement current of the gate oxide layer to be equivalent to the external circuit current of the transistor. Therefore, the capacitance of the gate oxide layer can be calculated based on the external circuit current of the transistor and the perturbation signal, thereby being able to avoid the influence of non-ideal charges on the capacitance of the gate oxide layer and accurately test the capacitance of the gate oxide layer. And the test can be performed based on the accumulation region, depletion region, and inversion region, without the need to search for the majority carrier accumulation region within a large potential range, improving the test efficiency.

[0060] Figure 4 It is a flowchart of a test method provided by an embodiment of the present application. Refer to Figure 4 As shown, the test method provided by an embodiment of the present application includes:

[0061] S101. Apply a positive bias voltage to the gate of the transistor at a preset temperature to control the mobile ion charges in the gate oxide layer of the transistor to accumulate at the interface between the substrate and the gate oxide layer of the transistor.

[0062] Mobile ion charges exist in the gate oxide layer, mainly alkali metal ions such as Na and K, which carry positive charges and can migrate in the gate oxide layer at a certain temperature and bias voltage.

[0063] Refer to Figure 5 As shown, the transistor includes a substrate 103, a gate oxide layer 102, and a gate 101 stacked in sequence. When a positive bias voltage is applied to the gate 101 of the transistor, the mobile ion charges in the gate oxide layer 102 of the transistor move towards the interface between the substrate 103 and the gate oxide layer 102 under the action of the positive bias voltage and accumulate at the interface between the substrate 103 and the gate oxide layer 102. At this time, the excess charges in the gate oxide layer 102 can all be regarded as interface traps. It should be noted that the main source of mobile ion charges is contamination during the process.

[0064] Interface trap charges are generated by the rapid exchange of charges and holes between interface states and the conduction band or valence band of silicon. Interface states mainly originate from excess trivalent silicon, broken Si-H valence bonds, excess oxygen or impurities, defects, etc., and are located at the interface between the gate oxide layer 102 and the substrate 103. They are the generation centers and recombination centers of minority carriers and can rapidly exchange charges and holes with the conduction band or valence band of silicon.

[0065] Reference Figure 6 As shown, when mobile ion charges accumulate at the interface between the substrate and the gate oxide layer of the transistor, the equivalent circuit of the metal-oxide-semiconductor composed of the gate-gate oxide layer-substrate includes a gate oxide layer capacitance Coxide, a depletion layer capacitance Cs, and an interface state capacitance Cit. The first end of the depletion layer capacitance Cs is connected to the first end of the interface state capacitance Cit, the second end of the depletion layer capacitance Cs is connected to the second end of the interface state capacitance Cit, and the second end of the gate oxide layer capacitance Coxide is connected to the first end of the depletion layer capacitance Cs and the first end of the interface state capacitance Cit.

[0066] Since the semiconductor tends to be in the intrinsic state at high temperatures, the depletion layer capacitance Cs tends to infinity, and the capacitive reactance of the depletion layer capacitance Cs tends to 0, resulting in a short circuit of the depletion layer capacitance Cs. Since the interface state capacitance Cit is in parallel with the depletion layer capacitance Cs, the capacitance characteristics of the metal-oxide-semiconductor are only manifested as the gate oxide layer capacitance Coxide.

[0067] In some embodiments, the temperature at which mobile ion charges move can be obtained, that is, the lowest temperature that prompts the movement of mobile ion charges. For example, the lowest temperature that prompts the movement of mobile ion charges is 100°C. The intrinsic state temperature of the semiconductor of the transistor substrate at the target doping concentration can also be obtained, and the target doping concentration is the current doping concentration of the transistor substrate. Then, the temperature at which mobile ion charges move is compared with the intrinsic state temperature of the semiconductor of the substrate at the target doping concentration, and the highest temperature among the temperature of the mobile ion charges and the intrinsic state temperature of the semiconductor is selected as the preset temperature, so as to ensure that each ion charge in the mobile ion charges moves to the interface between the gate oxide layer and the substrate, and at the same time, the depletion layer capacitance Cs tends to infinity.

[0068] In some embodiments, a positive bias voltage can be applied to the gate of the transistor at a preset temperature for a preset time, so that the mobile ion charges can be gathered as completely as possible at the interface between the substrate and the gate oxide layer of the transistor, further ensuring that the excess charges in the gate oxide layer can all be treated as interface traps. The positive bias voltage is, for example, less than the breakdown voltage of the transistor. The breakdown voltage refers to the drain-source voltage when the drain-source current flowing through is a specific value with the gate grounded, and it is the highest instantaneous voltage value that can be continuously applied to the drain-source before the transistor breaks down. The breakdown voltage is a key parameter for measuring the breakdown voltage of the transistor, and the larger it is, the better the breakdown voltage performance of the transistor. The preset time can be, for example, 8 - 15 min, such as 10 min.

[0069] S102. Apply a perturbation signal to the gate at a preset temperature and measure the external circuit current of the transistor. The perturbation signal is used to control the displacement current of the transistor to be equivalent to the external circuit of the transistor.

[0070] After applying a positive bias voltage to the gate of the transistor at a preset temperature, continue to maintain this preset temperature. Apply a perturbation signal to the gate of the transistor at the preset temperature. Since at the preset temperature, the capacitance characteristic of the metal oxide semiconductor composed of the gate, the gate oxide layer, and the substrate of the transistor only shows as the gate oxide layer capacitance Coxide, the measured external circuit current of the transistor is the current for measuring the gate oxide layer capacitance Coxide.

[0071] When applying a perturbation signal to the gate at a preset temperature, the measured external circuit current of the transistor is equal to the displacement current and the leakage current of the gate oxide layer, that is, ΔI ex =ΔJ E +ΔJ C . Refer to Figure 7 As shown in Figure 7 , it is the equivalent circuit diagram of the external circuit of the transistor. The first end of the gate oxide layer capacitance Coxide is connected to the first end of the gate oxide layer resistance Roxide, and the second end of the gate oxide layer capacitance Coxide is connected to the second end of the gate oxide layer resistance Roxide. The gate oxide layer resistance Roxide is used to indicate the potential barrier formed by the gate oxide layer. Then the gate oxide layer leakage current ΔJ E is the leakage current generated by crossing the potential barrier formed by the gate oxide layer.

[0072] And because a perturbation signal is applied to the gate at a preset temperature, the higher the frequency of the perturbation signal, the smaller the leakage current ΔJ E . Therefore, the frequency of the perturbation signal can be greater than or equal to the preset frequency, and it can control the leakage current ΔJ E to approach 0. Since the charging and discharging of the capacitance require time, when the frequency of the perturbation signal is relatively high, the displacement current ΔJ CThere is not enough time to charge the gate oxide capacitance, and the leakage current ΔJ of the gate oxide layer E approaches 0. When the frequency of the perturbation signal is relatively low, the displacement current ΔJ of the perturbation signal C charges the gate oxide capacitance, and tunneling occurs in the gate oxide layer to generate the gate oxide leakage current ΔJ E . Therefore, the displacement current ΔJ of the gate oxide layer C is equivalent to the external circuit current ΔI of the transistor ex , that is, ΔI ex = ΔJ C . The frequency of the perturbation signal can be equal to, for example, the highest frequency of the device applying the perturbation signal, so that the leakage current ΔJ of the gate oxide layer E is as small as possible.

[0073] In some embodiments, the perturbation signal can be a perturbation voltage. On the basis of applying a preset bias voltage to the gate at a preset temperature, a perturbation voltage can be applied to the gate. Applying a preset bias voltage makes the entire metal-oxide semiconductor in a steady state. It can be understood that the preset bias voltage makes the mobile ion charges in the gate oxide layer still accumulate at the interface between the gate oxide layer and the substrate. The perturbation voltage is used to make the leakage current ΔJ of the gate oxide layer E as small as possible. The perturbation voltage can be, for example, 10 mV to 30 mV, such as 20 mV. The preset temperature can be any bias voltage. Since the depletion layer capacitance tends to be infinitely large at the preset temperature, the change in the depletion layer capacitance does not affect the simplified result of the metal-oxide semiconductor equivalent circuit. Therefore, the entire metal-oxide semiconductor can be ensured to be in a steady state at any bias voltage. For example, the preset bias voltage is less than the positive bias voltage, reducing the voltage applied to the gate and increasing the lifespan of the transistor.

[0074] S103. Calculate the capacitance of the gate oxide layer according to the external circuit current of the transistor and the perturbation signal.

[0075] Since the gate oxide capacitance Coxide is a fixed capacitance value and is related to the thickness and area of the gate oxide capacitance plates. Then the gate oxide capacitance Coxide is the ratio of the charge carried by the gate oxide layer to the voltage between the gate oxide layers, that is, Coxide = dQ / dU. Since dQ / dU = (dQ / dt)×(dt / dU), then Coxide = dQ / dU = (dQ / dt)×(dt / dU). Also, since dQ / dt = ΔJ C , dt / dU = 1 / w, ΔI ex = ΔJ C , then Coxide = dQ / dU = (dQ / dt)×(dt / dU) = ΔI ex×1 / w. Where w is the angular frequency of the disturbance signal. Therefore, the capacitance Coxide of the gate oxide layer can be calculated based on the external circuit current of the transistor and the angular frequency of the disturbance signal. Here, the disturbance signal is the disturbance voltage.

[0076] The above has described in detail the test method provided by this application. By applying a positive bias voltage to the gate of the transistor at a preset temperature, the mobile ion charges in the gate oxide layer of the transistor are aggregated at the interface between the substrate and the gate oxide layer of the transistor, so that the mobile ion charges can be treated as interface traps. And because the preset temperature is relatively high, the depletion layer capacitance tends to be infinite, resulting in a short circuit of the depletion layer capacitance. Then, the capacitance characteristics of the metal-oxide semiconductor composed of the gate-gate oxide layer and the substrate in the transistor only exhibit the capacitance of the gate oxide layer. Then, a disturbance signal is applied to the gate at this preset temperature, and the frequency of the disturbance signal is as large as possible so that the drain current of the transistor is as small as possible. Then, the displacement current of the gate oxide layer is equivalent to the external circuit current of the transistor. After the external circuit current of the transistor is measured, the capacitance of the gate oxide layer can be calculated, so as to avoid the influence of non-ideal charges on the capacitance of the gate oxide layer and accurately measure the capacitance of the gate oxide layer.

[0077] Figure 8 The circuit diagram of a test circuit provided by an embodiment of this application is shown in Figure 8 As shown, an embodiment of this application also provides a test circuit. The test circuit includes a capacitance module 10, an equivalent resistor R, and a test module 20;

[0078] The first end of the capacitance module 10 is connected to the first end of the equivalent resistor R, the second end of the capacitance module 10 is connected to the second end of the equivalent resistor R, the first end of the test module 20 is connected to the first end of the capacitance module 10 and the first end of the equivalent resistor R, and the second end of the test module 20 is connected to the second end of the capacitance module 10 and the second end of the equivalent resistor R;

[0079] The capacitance module 10 is equivalent to the capacitance of the metal-oxide semiconductor composed of the gate, the gate oxide layer, and the substrate of the transistor when a positive bias voltage is applied to the gate of the transistor at a preset temperature;

[0080] The equivalent resistor R is equivalent to the resistance of the gate oxide layer;

[0081] The test module 20 is used to measure the currents of the capacitance module 10 and the equivalent resistor R, and calculate the capacitance Coxide of the gate oxide layer according to the measured currents and the disturbance signal. The disturbance signal is used to control the displacement current of the gate oxide layer to be equivalent to the current measured by the test module 20.

[0082] When a positive bias voltage is applied to the gate of a transistor, the mobile ion charges in the gate oxide layer of the transistor migrate under the action of the positive bias voltage towards the interface between the substrate and the gate oxide layer, and accumulate at the interface between the substrate and the gate oxide layer. At this time, all the excess charges in the gate oxide layer can be treated as interface traps. When the mobile ion charges accumulate at the interface between the substrate and the gate oxide layer of the transistor, the equivalent circuit of the metal-oxide-semiconductor composed of the gate - gate oxide layer - substrate includes a gate oxide capacitance Coxide, a depletion layer capacitance Cs, and an interface state capacitance Cit. The first end of the depletion layer capacitance Cs is connected to the first end of the interface state capacitance Cit, the second end of the depletion layer capacitance Cs is connected to the second end of the interface state capacitance Cit, and the second end of the gate oxide capacitance Coxide is connected to the first end of the depletion layer capacitance Cs and the first end of the interface state capacitance Cit.

[0083] Since the semiconductor tends to be in the intrinsic state at high temperatures, the depletion layer capacitance Cs tends to infinity, so the capacitive reactance of the depletion layer capacitance Cs tends to 0, resulting in a short circuit of the depletion layer capacitance Cs. Since the interface state capacitance Cit is in parallel with the depletion layer capacitance Cs, the capacitance characteristics of the metal-oxide-semiconductor only exhibit as the gate oxide capacitance Coxide.

[0084] Therefore, when a positive bias voltage is applied to the gate of the transistor at a preset temperature, the capacitance of the metal-oxide-semiconductor composed of the gate - gate oxide layer and the substrate of the transistor is the gate oxide capacitance Coxide, and thus the capacitance module 10 is equivalent to the gate oxide capacitance Coxide.

[0085] Since the frequency of the perturbation signal applied to the gate is used to control the leakage current of the gate oxide layer to be as small as possible and approach 0, the current flowing through the equivalent resistance R equivalent to the gate oxide resistance of the transistor approaches 0.

[0086] Therefore, the current of the capacitance module 10 and the equivalent resistance R measured by the test module 20 is the displacement current of the gate oxide capacitance Coxide. Then, the gate oxide capacitance Coxide can be calculated based on the current of the capacitance module 10 and the equivalent resistance R measured by the test module 20 and the perturbation signal.

[0087] In some embodiments, the capacitance module 10 includes: a first equivalent capacitance C1, a second equivalent capacitance C2, and a third equivalent capacitance C3; a first end of the first equivalent capacitance C1 is connected to a first end of the second equivalent capacitance C2, a second end of the first equivalent capacitance C1 is connected to a second end of the second equivalent capacitance C2, and a second end of the third equivalent capacitance C3 is connected to the first end of the first equivalent capacitance C1 and the first end of the second equivalent capacitance C2. The first equivalent capacitance C1 is equivalent to the depletion layer capacitance Cs of the transistor when a positive bias voltage is applied to the gate of the transistor at a preset temperature; the second equivalent capacitance C2 is equivalent to the surface state capacitance Cit of the transistor; the third equivalent capacitance C3 is equivalent to the gate oxide capacitance Coxide of the transistor when a perturbation signal is applied to the gate at a preset temperature after a positive bias voltage is applied to the gate at the preset temperature, and the frequency of the perturbation signal is greater than or equal to a preset value.

[0088] Since the preset temperature makes the semiconductor approach the intrinsic state, the depletion layer capacitance Cs approaches infinity. Therefore, when a positive bias voltage is applied to the gate of the transistor at the preset temperature, the depletion layer capacitance Cs of the transistor tends to infinity. And since the first equivalent capacitance C1 is equivalent to the depletion layer capacitance Cs of the transistor when a positive bias voltage is applied to the gate of the transistor at the preset temperature, the first equivalent capacitance C1 tends to infinity, and the capacitive reactance of the first equivalent capacitance C1 approaches 0.

[0089] Moreover, when a positive bias voltage is applied to the gate of the transistor at the preset temperature, the mobile ion charges in the gate oxide of the transistor move towards the interface between the substrate and the gate oxide of the transistor under the action of the positive bias voltage and accumulate at the interface between the substrate and the gate oxide of the transistor. Then, the excess charges in the gate oxide can all be treated as interface traps. The second equivalent capacitance C2 is equivalent to the surface state capacitance Cit of the transistor. Since the first equivalent capacitance C1 and the second equivalent capacitance C2 are in parallel, and the capacitive reactance of the first equivalent capacitance C1 approaches 0, the current of the parallel circuit formed by the parallel connection of the first equivalent capacitance C1 and the second equivalent capacitance C2 approaches 0.

[0090] Since the third equivalent capacitance C3 is connected to the parallel circuit formed by the first equivalent capacitance C1 and the second equivalent capacitance C2, and the capacitive reactance of the parallel circuit formed by the parallel connection of the first equivalent capacitance C1 and the second equivalent capacitance C2 approaches 0, the current of the capacitance module 10 is equivalent to the current of the third equivalent capacitance C3.

[0091] The first end of the equivalent resistor R is connected to the first end of the third equivalent capacitor C3, and the second end of the equivalent resistor R is connected to the second end of the first equivalent capacitor C1 and the second end of the second equivalent capacitor C2; the equivalent resistor R is equivalent to the gate oxide resistance of the transistor. Therefore, the test module 20 can be used to test the currents of the capacitor module 10 and the equivalent resistor R, and calculate the third equivalent capacitor C3 according to the currents of the capacitor module 10 and the equivalent resistor R and the perturbation signal, so as to obtain the gate oxide capacitance Coxide.

[0092] In some embodiments, the perturbation signal is a perturbation voltage. Since the gate oxide capacitance Coxide is a fixed capacitance value, which is related to the thickness and area of the gate oxide capacitor plates. Then the gate oxide capacitance Coxide is the ratio of the charge carried by the gate oxide to the voltage between the gate oxides, Coxide = dQ / dU = (dQ / dt)×(dt / dU) = ΔI ex ×1 / w. Where w is the angular frequency of the perturbation signal. Therefore, the gate oxide capacitance Coxide can be calculated according to the currents of the capacitor module 10 and the equivalent resistor R measured by the test module 20 and the angular frequency of the perturbation voltage.

[0093] The above has described in detail the test circuit provided by the embodiments of the present application. The test circuit includes a capacitor module, an equivalent resistor and a test module. The capacitor module is equivalent to the capacitance of the metal oxide semiconductor formed by the gate, the gate oxide and the substrate of the transistor when a positive bias voltage is applied to the gate of the transistor at a preset temperature. The equivalent resistor is equivalent to the resistance of the gate oxide. Since when a positive bias voltage is applied to the gate of the transistor at a preset temperature, the capacitance characteristic of the metal oxide semiconductor only shows the gate oxide capacitance. Then the capacitor module is equivalent to the gate oxide capacitance. Also, since the perturbation signal applied to the gate makes the leakage current of the gate oxide approach 0, the current of the equivalent resistor approaches 0. Therefore, the current measured by the test module is the displacement current of the gate oxide, and thus the third equivalent capacitor can be calculated according to the current measured by the test module and the perturbation signal, that is, the gate oxide capacitance is obtained.

[0094] The embodiments of the present application also provide a controller for implementing the above test method. The controller applies a positive bias voltage to the gate of the transistor at a preset temperature, controls the mobile ion charges in the gate oxide of the transistor to accumulate at the interface between the substrate and the gate oxide of the transistor, applies a perturbation signal to the gate at a preset temperature, tests the external circuit current of the transistor. The perturbation signal is used to control the displacement current of the gate oxide to be equivalent to the external circuit current of the transistor, and then calculate the capacitance of the gate oxide according to the external circuit current of the transistor and the perturbation signal.

[0095] The embodiments of the present application also provide a semiconductor memory including the above test circuit.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features. And these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A testing method, characterized in that, The method includes: Applying a positive bias voltage to the gate of the transistor at a preset temperature to control the accumulation of mobile ion charges in the gate oxide layer of the transistor at the interface between the substrate and the gate oxide layer; Applying a perturbation signal to the gate at the preset temperature and testing the external circuit current of the transistor, where the perturbation signal is used to control the displacement current of the gate oxide layer to be equivalent to the external circuit current of the transistor; Calculating the capacitance of the gate oxide layer based on the external circuit current of the transistor and the perturbation signal.

2. The method according to claim 1, characterized in that, The frequency of the perturbation signal is greater than or equal to a preset frequency.

3. The method according to claim 1, wherein The perturbation signal is a perturbation voltage. Calculating the capacitance of the gate oxide layer based on the external circuit current of the transistor and the perturbation signal specifically includes: Calculating the capacitance of the gate oxide layer based on the external circuit current of the transistor and the angular frequency of the perturbation voltage.

4. The method according to claim 1, wherein Applying a positive bias voltage to the gate of the transistor at the preset temperature specifically includes: Obtaining the temperature at which the mobile ion charges move and the semiconductor intrinsic state temperature of the substrate at a target doping concentration; Selecting the highest temperature among the temperature at which the mobile ion charges move and the semiconductor intrinsic state temperature as the preset temperature; Applying a positive bias voltage to the gate of the transistor at the preset temperature.

5. The method according to claim 1, wherein Applying a positive bias voltage to the gate of the transistor at the preset temperature specifically includes: Applying a positive bias voltage to the gate of the transistor for a preset time at the preset temperature.

6. The method according to claim 1, wherein Applying a perturbation signal to the gate at the preset temperature specifically includes: On the basis of applying a preset bias voltage to the gate at the preset temperature, applying a perturbation voltage to the gate.

7. The method according to claim 6, characterized in that, The preset bias voltage is less than the positive bias voltage.

8. The method according to any one of claims 1 to 7, characterized in that, The frequency of the perturbation signal is equal to the highest frequency of the device applying the perturbation signal.

9. The method according to any one of claims 1-7, characterized in that, The positive bias voltage is less than the breakdown voltage of the transistor.

10. A test circuit, characterized in that, The test circuit includes: A capacitance module, an equivalent resistor, and a test module; The first end of the capacitance module is connected to the first end of the equivalent resistor, the second end of the capacitance module is connected to the second end of the equivalent resistor, the first end of the test module is connected to the first end of the capacitance module and the first end of the equivalent resistor, and the second end of the test module is connected to the second end of the capacitance module and the second end of the equivalent resistor; The capacitance module is equivalent to the capacitance of the metal-oxide semiconductor formed by the gate, the gate oxide layer, and the substrate of the transistor when a positive bias voltage is applied to the gate of the transistor at a preset temperature; The equivalent resistor is equivalent to the resistance of the gate oxide layer; The test module is used to test the current of the capacitance module and the equivalent resistor, and calculate the capacitance of the gate oxide layer according to the measured current and the perturbation signal, where the perturbation signal is used to control the displacement current of the gate oxide layer to be equivalent to the current measured by the test module.

11. The test circuit according to claim 10, wherein The capacitance module includes a first equivalent capacitance, a second equivalent capacitance, and a third equivalent capacitance; The first end of the first equivalent capacitor is connected to the first end of the second equivalent capacitor, and the second end of the first equivalent capacitor is connected to the second end of the second equivalent capacitor to serve as the second end of the capacitor module. The second end of the third equivalent capacitor is connected to the first end of the first equivalent capacitor and the first end of the second equivalent capacitor, and the first end of the third equivalent capacitor serves as the first end of the capacitor module; The first equivalent capacitor is equivalent to the depletion layer capacitance of the transistor when a positive bias voltage is applied to the gate of the transistor at a preset temperature; The second equivalent capacitor is equivalent to the surface state capacitance of the transistor; The third equivalent capacitor is equivalent to the gate oxide capacitance of the transistor when a perturbation signal is applied to the gate at the preset temperature after a positive bias voltage is applied to the gate at the preset temperature, and the frequency of the perturbation signal is greater than or equal to a preset value.

12. The test circuit according to claim 11, wherein The first end of the equivalent resistor is connected to the first end of the third equivalent capacitor, and the second end of the equivalent resistor is connected to the second end of the first equivalent capacitor and the second end of the second equivalent capacitor; The first end of the test module is connected to the first end of the third equivalent capacitor, and the second end of the test module is connected to the second end of the first equivalent capacitor and the second end of the second equivalent capacitor.

13. The test circuit according to claim 12, characterized in that, The perturbation signal is a perturbation voltage; The test module is configured to test the current of the capacitor module and calculate the third equivalent capacitor according to the current of the capacitor module and the angular frequency of the perturbation voltage.

14. A controller, characterized in that, For implementing the test method according to any one of claims 1 to 9.

15. A semiconductor memory, characterized in that, Comprising: The test circuit according to any one of claims 11 - 13.

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