A series structure production method for preventing high-voltage LED chips from breaking

Abstract

The application relates to the technical field of LED chips, in particular to a high-voltage LED chip anti-fracture series connection structure production method, which comprises the following steps: S3: applying photoresist on a wafer 1; developing photoresist above a first exposed part; obtaining a wafer 2; S4: baking the wafer 2, baking time 2-6 min, temperature 100-160 DEG C; the high-voltage LED chip anti-fracture series connection structure production method has the beneficial effects that the cross section of the N-layer etched photoetching hole is also trapezoidal, and the side wall slope of the N-layer photoetching hole is only 35-40 DEG at this time. The metal bridge (series connection structure) is covered on the photoetching hole with the small N-layer slope, the metal bridge bending angle is small, and the effect of preventing the series connection structure from being fractured is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of LED chip, and particularly relates to a high-voltage LED chip anti-fracture series connection structure production method. BACKGROUND

[0002] LED (Light Emitting Diode) is a kind of solid-state semiconductor device which converts electrical energy into light energy. As a new type of light-emitting device, LED has the advantages of high light efficiency, energy saving, long service life, short response time, environmental protection, etc., and is therefore called the most potential new generation light source, and is extremely common in the field of lighting.

[0003] In recent years, in order to reduce the power consumption of LED chips and improve the utilization rate of packaging supports, a high-voltage chip is developed and designed, that is, two or more same LED chips are connected in series through a metal bridge, and the same current is provided for the above-mentioned high-voltage chip, so that the light intensity is more than twice that of ordinary chips.

[0004] However, in the actual production and use process, the inventor finds that the metal bridge is often broken, causing a high rate of defective high-voltage chips.

[0005] In the prior art (referring to Chinese patent CN106098899A), an insulating organic silicone glue is filled in the groove, and the groove depth is reduced to reduce the risk of insulation and metal fracture caused by too large height difference during subsequent insulation layer deposition and metal evaporation. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a high-voltage LED chip anti-fracture series connection structure production method to solve the problem that the series connection structure of the metal bridge is easy to break.

[0007] In order to solve the above technical problems, a technical solution adopted by the present application is as follows: a high-voltage LED chip anti-fracture series connection structure production method, comprising the following steps:

[0008] S1: using a metal organic chemical vapor deposition method to grow a N layer, a quantum well layer and a P layer on a sapphire substrate;

[0009] S2: etching the middle part of the P layer and the middle part of the quantum well until the surface of the N layer is exposed; in this step, the exposed N layer is a first exposed part, so that the P layer is divided into a first P layer and a second P layer; so that the quantum well is divided into a first quantum well and a second quantum well; to obtain Wafer1;

[0010] S3: coating a first insulating layer on the Wafer1; a photoresist; developing the photoresist above the middle part of the first exposed part; obtaining Wafer 2;

[0011] S4: baking Wafer 2, baking time 2-6 min, temperature 100-160 degrees; using plasma dry etching to etch the middle part of the first exposed part until the sapphire substrate is exposed; obtaining Wafer 3;

[0012] S5: depositing silicon dioxide on Wafer 3, etching the silicon dioxide near the edge of the first P layer side of the first exposed part, etching the silicon dioxide away from the edge of the first P layer side of the second P layer; the remaining silicon dioxide covering the part of the first exposed part, the exposed sapphire substrate, the second quantum well sidewall, the second P layer sidewall and the side of the second P layer near the first P layer in sequence is the second current blocking layer.

[0013] S6: evaporating metal bridges on the first exposed part not covered by the second current blocking layer, the second current blocking layer and the second P layer; obtaining the high-voltage LED chip anti-fracture series structure.

[0014] The beneficial effects of the present application are that in the high-voltage LED chip anti-fracture series structure production method provided by the present application, the photoresist applied on Wafer 1 is a relatively thick photoresist;

[0015] After developing the photoresist, the photoresist is baked: baking Wafer 2, baking time 2-6 min, temperature 100-160 degrees; while in the prior art, the photoresist is usually not baked. The high baking temperature and long baking time of the photoresist in the present application make the photoresist soften and tend to melt, the sidewall of the photoetching hole is inclined, the inclination of the photoetching hole of the photoresist is small, between 40-45 degrees, and the cross section of the photoetching hole of the photoresist is trapezoidal.

[0016] At this time, the N layer is etched, because the etching process also etches away a layer of photoresist, so the cross section of the photoetching hole of the N layer is also trapezoidal, and the sidewall inclination of the photoetching hole of the N layer is only 35-40 degrees.

[0017] Covering the metal bridge (series structure) on the N layer with a small slope photoetching hole, so that the metal bridge has a small bending angle.

[0018] Therefore, the high-voltage LED chip anti-fracture series structure production method provided by the present application makes the metal bridge have a small bending angle, which has the effect of preventing the series structure from breaking. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a schematic diagram of the overall structure of a high-voltage LED chip according to an embodiment of the present application;

[0020] Label explanation:​

[0021] 1. Sapphire substrate;

[0022] 2. First N layer; 21. Second N layer;

[0023] 3. First quantum well; 31. Second quantum well;

[0024] 4. First P layer; 41. Second P layer;

[0025] 5. First current blocking layer; 51. Second current blocking layer;

[0026] 6. Metal bridge;

[0027] 7. First ITO; 71. Second ITO;

[0028] 8. P pole; 81. N pole;

[0029] 9. Protective layer. DETAILED DESCRIPTION

[0030] To explain the technical content, the purpose and effect of the present application in detail, the following will be described in conjunction with the embodiments and the accompanying drawings.

[0031] Please refer to Figure 1 A series structure production method for preventing high-voltage LED chips from breaking, characterized in that it comprises the following steps:

[0032] S1: using metal organic chemical vapor deposition method to grow N layer, quantum well layer and P layer of gallium nitride base on sapphire substrate;

[0033] S2: etching the middle part of P layer and the middle part of quantum well until the surface of N layer is exposed; the exposed N layer in this step is the first exposed part, which divides the P layer into the first P layer and the second P layer; and the quantum well is divided into the first quantum well and the second quantum well; Wafer1 is obtained;

[0034] S3: applying photoresist on Wafer1; developing the photoresist above the middle part of the first exposed part; Wafer2 is obtained;

[0035] S4: baking Wafer2 for 2-6 min at 100-160 degrees; using plasma dry etching the middle part of the first exposed part until the sapphire substrate is exposed; Wafer3 is obtained;

[0036] ​S5: depositing silicon dioxide on the Wafer3, etching the silicon dioxide close to the side edge of the first P layer of the first exposed part, etching the silicon dioxide away from the side edge of the first P layer of the second P layer, and retaining the silicon dioxide covering the part of the first exposed part, the exposed sapphire substrate, the sidewall of the second quantum well, the sidewall of the second P layer and the side of the second P layer close to the first P layer in sequence as the second current blocking layer.

[0037] S6: evaporating metal bridges on the first exposed part not covered by the second current blocking layer, the second current blocking layer and the second P layer, and obtaining the high-voltage LED chip anti-fracture series structure.

[0038] From the above description, the beneficial effects of the present application are that the inventor has found that the reason why the LED series structure (i.e. the metal bridge) is easy to break is that the bending angle of the metal bridge is too large. Further, the reason why the bending angle of the metal bridge is too large is that the sidewall slope (or gradient) of the N layer etched out after etching the N layer is too large, usually 90 degrees.

[0039] In order to solve the above problems, the high-voltage LED chip anti-fracture series structure production method provided by the present application includes that the photoresist on the Wafer1 is a relatively thick photoresist.

[0040] After developing the photoresist, the photoresist is baked: baking the Wafer2, baking time 2-6 min, temperature 100-160 degrees. In the prior art, the photoresist is usually not baked. The high baking temperature and long baking time of the photoresist in the present application make the photoresist soften and tend to melt, the sidewall of the photoetching hole is inclined, the gradient of the photoetching hole of the photoresist is small, between 40-45 degrees, and the cross section of the photoetching hole of the photoresist is trapezoidal.

[0041] At this time, the N layer is etched, because the etching process also etches away a layer of photoresist, so the cross section of the photoetching hole of the N layer etched is also trapezoidal, and the sidewall gradient of the photoetching hole of the N layer is only 35-40 degrees.

[0042] The metal bridge (series structure) is covered on the photoetching hole of the N layer with the small slope, so that the bending angle of the metal bridge is small.

[0043] Therefore, the high-voltage LED chip anti-fracture series structure production method provided by the present application makes the bending angle of the metal bridge small, and has the effect of preventing the series structure from breaking.

[0044] Further, the S2 includes S2.1 and S2.2.

[0045] The S2 is specifically:

[0046] ​S2.1: etching the middle part of the P layer and the middle part of the quantum well until the surface of the N layer is exposed; the exposed N layer in this step is a first exposed part, the P layer is divided into a first P layer and a second P layer, and the quantum well is divided into a first quantum well and a second quantum well.

[0047] S2.2: etching the second P layer and the second quantum well to expose the second N layer; the exposed second N layer in this step is a second exposed part; and Wafer1 is obtained.

[0048] As can be seen from the above description, S2 further includes S2.2, and the role of S2.2 is to make the MASE of the second P layer and the second quantum well, expose the second N layer, and facilitate the subsequent manufacturing of the N pole.

[0049] Further, S2.3 is further included between S2 and S3.

[0050] S2.3: placing Wafer1 into a cleaning machine, stopping the bubbling cleaning after 120 s of bubbling cleaning;

[0051] Setting the rotation speed of the cleaning machine to 500 r / min, and simultaneously flushing the ion water for 100 s.

[0052] Setting the rotation speed of the cleaning machine to 2000 r / min, and simultaneously opening the air valve for 360 s.

[0053] Taking Wafer1 out of the cleaning machine.

[0054] As can be seen from the above description, the above steps can clean the etching residual impurities, and ensure the cleanliness of the surface of Wafer1.

[0055] Further, S2.4 is further included between S2 and S3.

[0056] S2.4: baking Wafer1 for 80-120 s at a temperature of 80-120 degrees.

[0057] As can be seen from the above description, baking Wafer1 in advance can improve the adhesion of the photoresist when the photoresist is applied subsequently, and improve the reliability of the photoresist.

[0058] Further, S3 is specifically: applying photoresist on Wafer1;

[0059] Exposing after setting a photoetching mask plate on the photoresist, the exposure energy is 230-280 mj, and the time is 5-10 s; then developing 2-4 times, forming photoetching holes on the photoresist after developing, cleaning the photoetching holes after each developing; the total developing time is 50-110 s; and Wafer2 is obtained.

[0060] From the above description, the above steps provide a simple and efficient photoetching photoresist method. Since the photoresist is thick, the photoetching hole formed has high precision.

[0061] Further, the S5 is specifically: depositing silicon dioxide on the Wafer3, etching away the silicon dioxide on the edge of the first P layer; the silicon dioxide remaining in the middle of the first P layer is the first current blocking layer;

[0062] Etching the silicon dioxide on the edge of the first P layer close to the first exposed part, etching the silicon dioxide on the edge of the second P layer away from the first P layer, and etching the silicon dioxide on the second exposed part; the remaining silicon dioxide covering the part of the first exposed part, the exposed sapphire substrate, the sidewall of the second quantum well, the sidewall of the second P layer, and the side of the second P layer close to the first P layer is sequentially connected and is the second current blocking layer.

[0063] From the above description, the first current blocking layer plays a role in diffusing current, thereby improving the light-emitting efficiency of the high-voltage LED chip. The second current blocking layer also has the effect of the first current blocking layer, and it can avoid the direct connection of the first N layer to the second N layer and the second quantum well.

[0064] Further, it further comprises S5.1 between S5 and S6;

[0065] S5.1: sputtering the first ITO on the first P layer and the first current blocking layer, the edge of the first ITO being 4 microns away from the edge of the first P layer, sputtering the second ITO on the second P layer and the second current blocking layer above the second P layer, the edge of the second ITO being 4 microns away from the edge of the second P layer.

[0066] From the above description, the first ITO and the second ITO play a role in diffusing current, thereby improving the light-emitting efficiency of the high-voltage LED chip.

[0067] Further, the S6 is specifically: evaporating the P pole on the first ITO directly above the first current blocking layer, and evaporating the N pole on the second exposed part. Evaporating the metal bridge on the first exposed part not covered by the second current blocking layer, the second current blocking layer, and the side of the second ITO close to the first P layer.

[0068] From the above description, a simple and efficient method for evaporating electrodes and metal bridges is provided.

[0069] Further, it further comprises S7;

[0070] S7: depositing silicon dioxide on the anti-fracture series structure of the high-voltage LED chip, etching the silicon dioxide covering the middle of the P pole until the P pole is exposed, and etching the silicon dioxide covering the middle of the N pole until the N pole is exposed;

[0071] The high-voltage LED chip is obtained.

[0072] From the above description, the protective layer is arranged to prevent electric leakage, and a simple and efficient method for conveniently electrically connecting the N pole and the P pole is provided.

[0073] Embodiment one

[0074] Please refer to Figure 1 A production method of a high-voltage LED chip anti-breaking series structure includes the following steps:

[0075] S1: A metal organic chemical vapor deposition method is used to grow a N layer, a quantum well layer and a P layer of a gallium nitride base on a sapphire substrate 1.

[0076] The middle part of the P layer and the middle part of the quantum well are etched until the surface of the N layer is exposed; in this step, the exposed N layer is a first exposed part, the P layer is divided into a first P layer 4 and a second P layer 41, and the quantum well is divided into a first quantum well 3 and a second quantum well 31.

[0077] The second P layer 41 and the second quantum well 31 are etched to expose the second N layer 21, and in this step, the exposed second N layer 21 is a second exposed part. Wafer 1 is obtained.

[0078] S2: Place the Wafer 1 into a cleaning machine, stop bubbling after 120s of bubbling cleaning;

[0079] Set the cleaning machine speed to 500r / min, and at the same time, flush the ion water for 100s.

[0080] Set the cleaning machine speed to 2000r / min, and at the same time, open the air valve for 360s.

[0081] Take the Wafer 1 out of the cleaning machine.

[0082] S3: Etch the middle part of the surface exposed N layer until the sapphire substrate 1 is exposed, so that the N layer is divided into a first N layer 2 and a second N layer 21.

[0083] S3 is specifically:

[0084] Bake the Wafer 1 for 100s at a temperature of 100 degrees; apply photoresist on the Wafer 1.

[0085] After setting a photoetch mask plate on the photoresist and exposing, the exposure energy is 250-260mj, and the time is 7-8s; then develop twice, form a photoetch hole on the photoresist after developing, and clean the photoetch hole after each developing; total developing time is 80s; Wafer 2 is obtained.

[0086] ​Bake Wafer2, baking time 4min, temperature 130 degrees.

[0087] Use plasma dry etching to etch N layer of Wafer2 until the sapphire substrate 1 is exposed.

[0088] Peel off the photoresist; get Wafer3.

[0089] S4: deposit silicon dioxide on Wafer3, etch off the silicon dioxide on the edge of the first P layer 4; the silicon dioxide remaining in the middle of the first P layer 4 is the first current blocking layer 5.

[0090] Etch the silicon dioxide on the side of the first exposed part close to the first P layer 4, etch the silicon dioxide on the side of the second P layer 41 away from the first P layer 4, and etch the silicon dioxide on the second exposed part. The silicon dioxide remaining on the side of the second P layer 41 close to the first P layer 4, the side wall of the second quantum well 31, the side wall of the second P layer 41, and the side wall of the first exposed part is the second current blocking layer 51.

[0091] S5: sputter the first ITO 7 on the first P layer 4 and the first current blocking layer 5, the edge of the first ITO 7 is 4 microns away from the edge of the first P layer 4, sputter the second ITO 71 on the second P layer 41 and the second current blocking layer 51 above the second P layer 41, the edge of the second ITO 71 is 4 microns away from the edge of the second P layer 41.

[0092] S6: evaporate the P electrode 8 on the first ITO 7 directly above the first current blocking layer 5, and evaporate the N electrode 81 on the second exposed part. Evaporate the metal bridge 6 on the side of the first P layer 4 on the first exposed part not covered by the second current blocking layer 51, the second current blocking layer 51, and the second ITO 71.

[0093] Get the high-voltage LED chip anti-fracture series structure.

[0094] S7: deposit silicon dioxide on the high-voltage LED chip anti-fracture series structure, "deposit silicon dioxide" to form a protective layer 9, etch the silicon dioxide covering the middle of the P electrode 8 until the P electrode 8 is exposed, and etch the silicon dioxide covering the middle of the N electrode 81 until the N electrode 81 is exposed.

[0095] Get the high-voltage LED chip.

[0096] The principle of the high-voltage LED chip anti-fracture series structure production method provided by Example 1 and the principle of the high-voltage LED chip produced:

[0097] The high-voltage LED chip current flows from the P pole into the first ITO, the first ITO layer plays a diffusion role for the current, avoiding the current from flowing through the first P layer and the first quantum well at a point, thereby improving the luminous flux of the high-voltage LED chip.

[0098] After the current flows through the first ITO, it bypasses the first current blocking layer (which plays a similar role to the first ITO), and then flows through the first P layer, the first quantum well, the first N layer, the metal bridge, the second ITO, the second P layer, the second quantum well, the second N layer, and the N pole in turn.

[0099] Wherein, "S3: etching the middle part of the N layer exposed on the surface until the sapphire substrate is exposed", the N layer is divided into a first N layer and a second N layer, and if the first N layer and the second N layer are connected, it will cause a conflict in the current flow, causing the problem of a sharp decrease in the high-voltage LED chip. To further solve this problem, a second current blocking layer structure is also provided, which avoids the metal bridge from contacting the second N layer, the second quantum well, and the P layer directly from the P layer side wall while contacting the first N layer. The second current blocking layer also has the effect of diffusing the current as the first current blocking layer.

[0100] Embodiment Two

[0101] S1: using a metal organic chemical vapor deposition method to grow a gallium nitride-based N layer, quantum well layer, and P layer on a sapphire substrate;

[0102] S2: etching the middle part of the P layer and the middle part of the quantum well until the surface of the N layer is exposed; the N layer exposed in this step is a first exposed part, the P layer is divided into a first P layer and a second P layer in intervals, and the quantum well is divided into a first quantum well and a second quantum well in intervals. Wafer1 is obtained.

[0103] S3: etching the middle part of the N layer exposed on the surface until the sapphire substrate is exposed, so that the N layer is divided into a first N layer and a second N layer in intervals.

[0104] S3 is specifically:

[0105] A photoresist is applied on Wafer1.

[0106] After setting a photomask on the photoresist and exposing it, developing it is performed; Wafer2 is obtained.

[0107] Wafer2 is baked for 4 minutes at a temperature of 130 degrees.

[0108] The N layer of Wafer2 is etched using a plasma dry etching method until the sapphire substrate is exposed.

[0109] Wafer3 is obtained. ​

[0110] S4: depositing silicon dioxide on Wafer3.

[0111] Etching the silicon dioxide on the first exposed part near the side edge of the first P layer, etching the silicon dioxide on the second P layer away from the side edge of the first P layer, and etching the silicon dioxide on the second exposed part. The remaining silicon dioxide covering the part of the first exposed part, the exposed sapphire substrate, the second quantum well sidewall, the second P layer sidewall, and the side of the second P layer near the first P layer in sequence is the second current blocking layer.

[0112] S5: depositing P electrode on the first ITO directly above the first current blocking layer, and depositing N electrode on the second exposed part. Depositing metal bridge on the first exposed part not covered by the second current blocking layer, the second current blocking layer, and the second P layer.

[0113] Obtaining the high-voltage LED chip anti-fracture series structure.

[0114] Embodiment three

[0115] A production method of a high-voltage LED chip anti-fracture series structure includes the following steps:

[0116] S1: using metal organic chemical vapor deposition method to grow N layer, quantum well layer, and P layer of gallium nitride base on sapphire substrate.

[0117] S2: etching the middle part of the P layer and the middle part of the quantum well until the surface of the N layer is exposed; the exposed N layer in this step is the first exposed part, which divides the P layer into the first P layer and the second P layer; and the quantum well is divided into the first quantum well and the second quantum well.

[0118] Etching the second P layer and the second quantum well to expose the second N layer, and the exposed second N layer is the second exposed part. Obtaining Wafer1.

[0119] S3: etching the middle part of the surface exposed N layer until the sapphire substrate is exposed, which divides the N layer into the first N layer and the second N layer.

[0120] S3 is specifically:

[0121] Coating photoresist on Wafer1.

[0122] After setting a photomask on the photoresist and exposing, the exposure energy is 260 mj, and the time is 8 s; then developing twice, forming a photoetching hole on the photoresist after developing, and cleaning the photoetching hole after each developing; total developing time is 80 s; obtaining Wafer2.

[0123] Baking Wafer2, baking time is 4 min, and temperature is 130 degrees.​

[0124] Plasma dry etching the N layer of Wafer 2 until the sapphire substrate is exposed. Wafer 3 is obtained.

[0125] S4: Depositing silicon dioxide on Wafer 3, etching away the silicon dioxide on the edge of the first P layer; the silicon dioxide remaining in the middle of the first P layer is the first current blocking layer.

[0126] Etching the silicon dioxide on the edge of the first exposed part close to the first P layer, etching the silicon dioxide on the edge of the second P layer away from the first P layer, and etching the silicon dioxide on the second exposed part. The silicon dioxide remaining covering the part of the first exposed part, the exposed sapphire substrate, the sidewall of the second quantum well, the sidewall of the second P layer, and the side of the second P layer close to the first P layer in sequence is the second current blocking layer.

[0127] S5: Sputtering the first ITO on the first P layer and the first current blocking layer, the edge of the first ITO being 4 microns away from the edge of the first P layer, and sputtering the second ITO on the second P layer and the second current blocking layer above the second P layer, the edge of the second ITO being 4 microns away from the edge of the second P layer.

[0128] S6: Evaporating the P electrode on the first ITO directly above the first current blocking layer, and evaporating the N electrode on the second exposed part. Evaporating the metal bridge on the part of the first exposed part not covered by the second current blocking layer, the second current blocking layer, and the side of the second ITO close to the first P layer.

[0129] The high-voltage LED chip anti-fracture series structure is obtained.

[0130] S7: Depositing silicon dioxide on the high-voltage LED chip anti-fracture series structure, etching the silicon dioxide covering the middle of the P electrode until the P electrode is exposed, and etching the silicon dioxide covering the middle of the N electrode until the N electrode is exposed.

[0131] The high-voltage LED chip is obtained.

[0132] Comparative Example

[0133] baseline Batch 1 Batch 2 Batch 3 Total number of tests 100 100 100 Number of breaks 71 78 75

[0134] test Batch 1 Batch 2 Batch 3 Total number of tests 150 100 200 Number of breaks 0 0 0

[0135] baseline represents an LED chip produced without using the method of the present application.

[0136] test represents an LED chip produced using the method of the present application.

[0137] The above merely illustrates the embodiments of the present application, and is not intended to limit the patent scope of the present application. Any equivalent transformation or direct or indirect application in the related technical field based on the content of the present application specification and drawings is also included in the patent protection scope of the present application.

Claims

1. A method for producing a series structure for preventing breakage of high-voltage LED chips, characterized in that, Includes the following steps: S1: Using metal-organic chemical vapor deposition, gallium nitride-based N-layers, quantum well layers, and P-layers are grown on a sapphire substrate; S2: Etch the middle of the P layer and the middle of the quantum well until the surface of the N layer is exposed; In this step, the exposed N layer is the first exposed part, which divides the P layer into a first P layer and a second P layer with intervals; the quantum well is divided into a first quantum well and a second quantum well with intervals; Wafer1 is obtained. S3: Apply 8000-12000 Å photoresist to Wafer1; develop the photoresist above the center of the first exposed portion; obtain Wafer2; S4: Bake Wafer 2 for 2-6 minutes at 100-160 degrees Celsius; use plasma dry etching to etch the center of the first exposed part until the sapphire substrate is exposed; obtain Wafer 3. S5: Deposit silicon dioxide on Wafer 3, etch the silicon dioxide on the edge of the first exposed portion near the first P layer, and etch the silicon dioxide on the edge of the second P layer away from the first P layer; the remaining silicon dioxide covering part of the first exposed portion, the exposed sapphire substrate, the second quantum well sidewall, the second P layer sidewall, and the side of the second P layer near the first P layer is the second current blocking layer. S6: Deposit metal bridging on the first exposed portion without the second current blocking layer, the second current blocking layer, and the second P layer; to obtain the series structure of the high voltage LED chip to prevent breakage; The feature is that S2 includes S2.1 and S2.2; Specifically, S2 is: S2.1: Etch the middle of the P layer and the middle of the quantum well until the surface of the N layer is exposed; the exposed N layer in this step is the first exposed part, which divides the P layer into a first P layer and a second P layer with spacing; and divides the quantum well into a first quantum well and a second quantum well with spacing. S2.2: Etch the second P layer and the second quantum well to expose the second N layer. The exposed second N layer in this step is the second exposed part; Wafer1 is obtained.

2. The method for producing a series structure for preventing breakage of high-voltage LED chips according to claim 1, characterized in that, It also includes S2.3, which is between S2 and S3; S2.3: Place Wafer1 into the cleaning machine, bubble clean for 120 seconds, then stop the bubble cleaning; Set the cleaning machine speed to 500 r / min and rinse with deionized water for 100 seconds. Set the cleaning machine speed to 2000 r / min and open the air blowing valve at the same time, and maintain it for 360 seconds; Remove Wafer1 from the cleaning machine.

3. The method for producing a series structure for preventing breakage of high-voltage LED chips according to claim 1, characterized in that, It also includes S2.4, which is between S2 and S3; S2.4: Bake Wafer 1, baking time 80-120 seconds, temperature 80-120 degrees.

4. The method for producing a series structure for preventing breakage of high-voltage LED chips according to claim 1, characterized in that, Specifically, S3 involves coating Wafer1 with 8000-12000 Å of photoresist. After placing a photomask on the photoresist, exposure is performed at an energy of 230-280 mJ for 5-10 seconds. Then, 2-4 development cycles are performed. After development, photolithographic holes are formed on the photoresist. The photolithographic holes are cleaned after each development cycle. The total development time is 50-110 seconds. We obtained Wafer2.

5. The method for producing a series structure for preventing breakage of high-voltage LED chips according to claim 1, characterized in that, Specifically, S5 involves depositing silicon dioxide on Wafer 3 and etching away the silicon dioxide at the edge of the first P layer; the silicon dioxide remaining in the middle of the first P layer serves as the first current blocking layer. The silicon dioxide on the edge of the first exposed portion near the first P layer is etched, the silicon dioxide on the edge of the second P layer away from the first P layer is etched, and the silicon dioxide on the second exposed portion is etched; the silicon dioxide that remains, which is sequentially connected and covers part of the first exposed portion, the exposed sapphire substrate, the second quantum well sidewall, the second P layer sidewall, and the side of the second P layer near the first P layer, is the second current blocking layer.

6. The method for producing a series structure for preventing breakage of high-voltage LED chips according to claim 5, characterized in that, It also includes S5.1 between S5 and S6; S5.1: Sputter a first ITO on the first P layer and the first current blocking layer, with the edge of the first ITO 4 micrometers away from the edge of the first P layer; and sputter a second ITO on the second current blocking layer above the second P layer, with the edge of the second ITO 4 micrometers away from the edge of the second P layer.

7. The method for producing a series structure for preventing breakage of high-voltage LED chips according to claim 6, characterized in that, Specifically, S6 involves: depositing a P-electrode on the first ITO directly above the first current blocking layer, and depositing an N-electrode on the second exposed portion; depositing a metal bridging layer on the side portion of the first exposed portion, the second current blocking layer, and the second ITO that is not covered by the second current blocking layer, near the first P-layer.

8. The method for producing a series structure for preventing breakage of high-voltage LED chips according to claim 7, characterized in that, Also includes S7; S7: Deposit silicon dioxide on the series structure of the high voltage LED chip to prevent breakage, etch silicon dioxide covering the middle of the P electrode until the P electrode is exposed, and etch silicon dioxide covering the middle of the N electrode until the N electrode is exposed. The high-voltage LED chip is obtained.

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