Stacked structures, memory devices, and methods of manufacturing stacked structures

Abstract

The present disclosure relates to a stack structure, a memory device, and a method of manufacturing a stack structure. The stack structure includes a ferroelectric layer and a tunnel barrier layer connected to the ferroelectric layer. A main component of the ferroelectric layer is aluminum nitride, and a main component of the tunnel barrier layer is magnesium oxide.

Description

Technical Field

[0001] This invention relates to stacked structures, memory devices, and methods for manufacturing stacked structures. Background Technology

[0002] Conventional ferroelectric memories, consisting only of a ferroelectric layer disposed between two electrodes, suffer from the disadvantage of destructive reading. On the other hand, memory devices comprising ferroelectric tunnel junctions with a structure having a stacked ferroelectric layer and a tunnel barrier layer can read data non-destructively, thus holding promise for applications in next-generation high-speed random access memories and high-capacity memory types (Non-Patent Document 1). As ferroelectric materials for the ferroelectric layer in ferroelectric tunnel junctions, HfO2 and HfZrO2, formed by doping HfO2 with Zr, are known (Non-Patent Documents 2 and 3). Recently, AlScN, having a wurtzite structure and obtained by doping aluminum nitride (AlN) with scandium (Sc), has been found to exhibit a larger remanent polarization value (Non-Patent Document 4). Methods for reducing the film thickness have been proposed for its application in memory (Non-Patent Document 5). Furthermore, Al2O3 is known as an insulating material for the tunnel barrier layer (Non-Patent Document 2).

[0003] In conventional ferroelectric tunnel junctions and memory devices using these junctions, a high voltage is applied between the upper and lower electrodes to reverse the polarization direction. In this case, in ferroelectric tunnel junction films using Al2O3 as the tunnel barrier layer material, the tunnel barrier layer is highly likely to cause dielectric breakdown.

[0004] [Non-Patent Literature 1] V. Garcia & M. Bibes, “Nature Communications”, 5, 4289 (2014)

[0005] [Non-Patent Literature 2] B. Max et al., The 48th ESSDERC, 2018, pp. 142-145

[0006] [Non-Patent Literature 3] S. Shosuke & M. Saitoh, Toshiba Review, Vol. 72, No. 4, (2017) pp. 66-68

[0007] [Non-Patent Literature 4] S. Fichtner et al., Journal of Applied Physics, Vol. 125, 114103 (2019)

[0008] [Non-Patent Literature 5] S. Yasuoka et al., Journal of Applied Physics, Vol. 128, 114103 (2020) Summary of the Invention

[0009] This invention provides a technique that advantageously increases the dielectric breakdown voltage of the tunnel barrier layer.

[0010] A first aspect of the present invention provides a stacked structure comprising a ferroelectric layer and a tunnel barrier layer connected to the ferroelectric layer, wherein the main component of the ferroelectric layer is aluminum nitride and the main component of the tunnel barrier layer is magnesium oxide.

[0011] A second aspect of the invention provides a memory device including a capacitor, the capacitor comprising a stacked structure as defined in the first aspect of the invention.

[0012] A third aspect of the invention provides a method for manufacturing a stacked structure, comprising forming a junction between a ferroelectric layer and a tunnel barrier layer, wherein the main component of the ferroelectric layer is aluminum nitride and the main component of the tunnel barrier layer is magnesium oxide.

[0013] Further features of the invention will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0014] Figure 1 A cross-sectional view illustrating the structure of a stacked structure or ferroelectric tunnel junction according to one embodiment;

[0015] Figure 2 For illustrative purposes, a cross-sectional view of the stacked structure or ferroelectric tunnel junction according to Example 1 is shown;

[0016] Figure 3 For illustrative purposes, a cross-sectional view of the stacked structure or ferroelectric tunnel junction according to Example 2 is shown; and

[0017] Figure 4 A view showing the configuration of a storage cell of a memory device according to one embodiment. Detailed Implementation

[0018] In the following description, embodiments will be given in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of the claimed invention. Multiple features are described in the embodiments, but this does not limit the invention to requiring all of these features, and multiple such features can be appropriately combined. Furthermore, in the drawings, the same reference numerals are given the same or similar configuration, and redundant descriptions are omitted.

[0019] Figure 1 An exemplary configuration of a stacked structure 100 according to one embodiment is shown. The stacked structure 100 may include a ferroelectric layer 2 and a tunnel barrier layer 3 bonded to the ferroelectric layer 2. The ferroelectric layer 2 and the tunnel barrier layer 3 are bonded to each other via a bonding surface 10. The stacked structure 100 may also be referred to as a ferroelectric tunnel junction.

[0020] The primary component of the ferroelectric layer 2 can be, for example, aluminum nitride (AlN). The ferroelectric layer 2 can contain aluminum nitride at concentrations of, for example, 50 at% or higher, 60 at% or higher, 70 at% or higher, 80 at% or higher, 85 at% or higher, 90 at% or higher, or 95 at% or higher. The primary component of the tunnel barrier layer 3 can be, for example, magnesium oxide (MgO). The tunnel barrier layer 3 can contain magnesium oxide at concentrations of, for example, 50 at% or higher, 60 at% or higher, 70 at% or higher, 80 at% or higher, 85 at% or higher, 90 at% or higher, 95 at% or higher, or 98 at% or higher. The tunnel barrier layer 3 is an insulator.

[0021] The stacked structure 100 may include a first electrode 1 and a second electrode 4, with a ferroelectric layer 2 and a tunnel barrier layer 3 disposed between the first electrode 1 and the second electrode 4. In one example, the first electrode 1 is the lower electrode, the second electrode 4 is the upper electrode, and the tunnel barrier layer 3 may be disposed between the ferroelectric layer 2 and the second electrode 4. In another example, the first electrode 1 is the lower electrode, the second electrode 4 is the upper electrode, and the tunnel barrier layer 3 may be disposed between the first electrode 1 and the ferroelectric layer 2.

[0022] In one example, the ferroelectric layer 2 can be deposited on the first electrode 1, the tunnel barrier layer 3 can be deposited on the ferroelectric layer 2, and the second electrode 4 can be deposited on the tunnel barrier layer 3.

[0023] The first electrode 1 has a NaCl structure, and the (111) surface of the NaCl structure is preferably along the upper surface or bonding surface 10 of the first electrode 1. In other words, the first electrode 1 is preferably a (111) oriented film with a NaCl structure, the (111) surface of the NaCl structure being almost parallel to the upper surface or bonding surface 10 of the first electrode 1. Here, the upper surface of the first electrode 1 is the facing surface S1, which faces the second electrode 4 via the ferroelectric layer 2 and the tunnel barrier layer 3.

[0024] A more detailed example will be described. The first electrode 1 is preferably a titanium nitride (TiN) film having a NaCl structure, the (111) surface of which is along the upper surface or bonding surface 10 of the first electrode 1. Alternatively, the first electrode 1 can be a conductive film configured to facilitate the formation of a ferroelectric layer 2 having a wurtzite structure on the first electrode 1, the (001) surface of which is along the bonding surface 10.

[0025] The ferroelectric layer 2 can be made of a ferroelectric material whose main component is aluminum nitride. When secondary components are added to the main component, the ferroelectric layer 2 can exhibit ferroelectricity. Secondary components may include at least one of, for example, scandium (Sc) and boron (B). However, the invention is not limited thereto. The ferroelectric layer 2 is preferably a film having a wurtzite structure, with the (001) surface of the wurtzite structure along the bonding surface 10; in other words, the ferroelectric layer 2 is a (001) oriented film whose (001) surface is almost parallel to the bonding surface 10.

[0026] The tunnel barrier layer 3 can be made of an insulator whose main component is, for example, magnesium oxide (MgO). The tunnel barrier layer 3 is preferably a film with a NaCl structure, the (111) surface of which is along the bonding surface 10. In other words, the tunnel barrier layer 3 is a (111) oriented film, and its (111) surface is almost parallel to the bonding surface 10.

[0027] The second electrode 4 can be made of a conductor that will hardly cause thermal diffusion between the second electrode 4 and the tunnel barrier layer 3 even under thermal load. The second electrode 4 can be, for example, a titanium nitride (TiN) film, but can be made of another conductor.

[0028] In another example, a tunnel barrier layer 3 may be deposited on a first electrode 1, a ferroelectric layer 2 may be deposited on the tunnel barrier layer 3, and a second electrode 4 may be deposited on the ferroelectric layer 2.

[0029] According to this embodiment, the dielectric breakdown voltage of the tunnel barrier layer 3 is increased.

[0030] Figure 2 An exemplary embodiment shows a stacked structure 100' according to Example 1 and a method of manufacturing therein. The stacked structure 100' may include a first electrode 1, a ferroelectric layer 2 deposited or disposed on the first electrode 1, a tunnel barrier layer 3 deposited or disposed on the ferroelectric layer 2, and a second electrode 4 deposited or disposed on the tunnel barrier layer 3. The stacked structure 100' may also be referred to as a ferroelectric tunnel junction.

[0031] The first electrode 1 can be a TiN film with a NaCl structure, the (111) surface of which is along the bonding surface 10. The first electrode 1 can have a thickness in the range of 10 nm (inclusive) to 50 nm (inclusive). To promote the (111) orientation of the TiN film used as the first electrode 1, a tantalum (Ta) film with a thickness in the range of 5 nm (inclusive) to 10 nm (inclusive) is formed as a base layer 6, and a ruthenium (Ru) film with a thickness in the range of 2 nm (inclusive) to 10 nm (inclusive) is formed thereon as a seed layer 5. Here, the seed layer 5 can be made of platinum (Pt), nickel (Ni), or titanium (Ti). The seed layer 5 can be made of an alloy containing Ru, Pt, Ni, or Ti as the main component. Furthermore, the base layer 6 can be made of tantalum nitride (TaN), Ru, or Pt, and the base layer 6 can be omitted depending on the material and structure of the substrate surface directly below the base layer 6.

[0032] Ferroelectric layer 2 can be deposited on the first electrode 1. Ferroelectric layer 2 can contain, for example, aluminum nitride (AlN) as a main component and can contain boron (B) in the range of 2 at% (inclusive) to 10 at% (inclusive) as a secondary component. The thickness of ferroelectric layer 2 can be, for example, in the range of 5 nm (inclusive) to 20 nm (inclusive). Ferroelectric layer 2 is preferably thin, as long as it maintains ferroelectricity. The secondary component can be, for example, scandium (Sc). In this case, the amount of Sc added preferably falls within, for example, the range of 5 at% (inclusive) to 45 at% (inclusive).

[0033] The tunnel barrier layer 3 can be deposited on the ferroelectric layer 2. The tunnel barrier layer 3 can be made of, for example, magnesium oxide (MgO). The tunnel barrier layer 3 can have a thickness in the range of, for example, 1 nm (inclusive) to 4 nm (inclusive). When the tunnel barrier layer 3 is deposited or formed on the ferroelectric layer 2, a junction is formed between the ferroelectric layer 2 and the tunnel barrier layer 3.

[0034] The second electrode 4 can be deposited on the tunnel barrier layer 3. The second electrode 4 can be made of a conductive film such as TiN. The second electrode 4 can have a thickness of, for example, 10 nm (inclusive) to 50 nm (inclusive).

[0035] To fabricate the stacked structure 100' or ferroelectric tunnel junction, sputtering deposition can be used. Here, the process from the formation of the bottom layer 6 to the formation of the second electrode 4 is preferably performed in a vacuum environment without exposure to the atmosphere.

[0036] Figure 3An exemplary stacked structure 100” according to Example 2 and its manufacturing method are shown. The stacked structure 100” may include a first electrode 1, a tunnel barrier layer 3 deposited or disposed on the first electrode 1, a ferroelectric layer 2 deposited or disposed on the tunnel barrier layer 3, and a second electrode 4 deposited or disposed on the ferroelectric layer 2. The stacked structure 100” may also be referred to as a ferroelectric tunnel junction.

[0037] The first electrode 1 can be a TiN film with a NaCl structure, the (111) surface of which is along the bonding surface 10. The first electrode 1 can have a thickness in the range of 10 nm (inclusive) to 50 nm (inclusive). To promote the (111) orientation of the TiN film used as the first electrode 1, a tantalum (Ta) film with a thickness in the range of 5 nm (inclusive) to 10 nm (inclusive) is formed as a base layer 6, and a ruthenium (Ru) film with a thickness in the range of 2 nm (inclusive) to 10 nm (inclusive) is formed thereon as a seed layer 5. Here, the seed layer 5 can be made of platinum (Pt), nickel (Ni), or titanium (Ti). The seed layer 5 can be made of an alloy containing Ru, Pt, Ni, or Ti as the main component. Furthermore, the base layer 6 can be made of tantalum nitride (TaN), Ru, or Pt, and the base layer 6 can be omitted depending on the material and structure of the substrate surface directly below the base layer 6.

[0038] The tunnel barrier layer 3 can be deposited on the first electrode 1. The tunnel barrier layer 3 can be made of, for example, magnesium oxide (MgO). The tunnel barrier layer 3 can have a thickness in the range of, for example, 1 nm (inclusive) to 4 nm (inclusive).

[0039] Ferroelectric layer 2 can be deposited on tunnel barrier layer 3. Ferroelectric layer 2 may contain, for example, aluminum nitride (AlN) as a main component and may contain boron (B) in the range of 2 at% (inclusive) to 10 at% (inclusive) as a secondary component. The thickness of ferroelectric layer 2 may be in the range of, for example, 5 nm (inclusive) to 20 nm (inclusive). Ferroelectric layer 2 is preferably thin, as long as it maintains ferroelectricity. The secondary component may be, for example, scandium (Sc). In this case, the amount of Sc added is preferably in the range of, for example, 5 at% (inclusive) to 45 at% (inclusive). When ferroelectric layer 2 is deposited or formed on tunnel barrier layer 3, a junction is formed between tunnel barrier layer 3 and ferroelectric layer 2.

[0040] The second electrode 4 can be deposited on the ferroelectric layer 2. The second electrode 4 can be made of a conductive film such as TiN. The second electrode 4 can have a thickness of, for example, 10 nm (inclusive) to 50 nm (inclusive).

[0041] To fabricate a stacked structure 100” or a ferroelectric tunnel junction, sputtering deposition can be used. Here, the process from the formation of the bottom layer 6 to the formation of the second electrode 4 is preferably performed in a vacuum environment without exposure to the atmosphere.

[0042] Figure 4 An example of the configuration of a memory cell MC of a memory device according to one embodiment is shown. The memory cell MC may include a capacitor C formed by the stacked structure represented by the stacked structures 100, 100' and 100” described above, and a selection transistor ST. Similar to the stacked structures 100, 100' and 100” described above, the capacitor C may include a first electrode 1, a second electrode 4, and a ferroelectric layer 2 and a tunnel barrier layer 3 disposed between the first electrode 1 and the second electrode 4.

[0043] One of the first electrode 1 and the second electrode 4 of capacitor C can be connected to the bit line BL via a select transistor ST, and the other of the first electrode 1 and the second electrode 4 can be connected to the board line PL. The gate of the select transistor ST can be connected to the word line WL.

[0044] Although the invention has been described with reference to exemplary embodiments, it should be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims should be given the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. A stacked structure comprising a ferroelectric layer, a tunnel barrier layer connected to the ferroelectric layer, a first electrode, and a second electrode, wherein, The ferroelectric layer and the tunnel barrier layer are disposed between the first electrode and the second electrode, and the stacked structure includes: The bottom layer; and A seed layer is disposed on the bottom layer, wherein the first electrode is disposed on the seed layer. The ferroelectric layer contains aluminum nitride with a concentration of 50 at% or higher, and the tunnel barrier layer contains magnesium oxide with a concentration of 50 at% or higher. The bottom layer is made of one of tantalum, tantalum nitride, ruthenium, and platinum. The seed layer is made of one of ruthenium, platinum, nickel, and titanium.

2. The stacking structure according to claim 1, wherein The ferroelectric layer has a wurtzite structure, and the (001) surface of the wurtzite structure runs along the interface between the ferroelectric layer and the tunnel barrier layer.

3. The stacking structure according to claim 1, wherein The tunnel barrier layer has a NaCl structure, and the (111) surface of the NaCl structure runs along the interface between the ferroelectric layer and the tunnel barrier layer.

4. The stacking structure according to claim 1, wherein The ferroelectric layer has a wurtzite structure, the tunnel barrier layer has a NaCl structure, and The (001) surface of the wurtzite structure and the (111) surface of the NaCl structure are along the interface between the ferroelectric layer and the tunnel barrier layer.

5. The stacking structure according to claim 1, wherein The first electrode is the lower electrode, and the second electrode is the upper electrode. The tunnel barrier layer is positioned between the ferroelectric layer and the second electrode.

6. The stacking structure according to claim 1, wherein The first electrode is the lower electrode, and the second electrode is the upper electrode. The tunnel barrier layer is positioned between the first electrode and the ferroelectric layer.

7. The stacking structure according to claim 1, wherein The first electrode includes a facing surface of the second electrode via a ferroelectric layer and a tunnel barrier layer, the first electrode having a NaCl structure, and the (111) surface of the NaCl structure of the first electrode along the facing surface.

8. The stacking structure according to claim 1, wherein The ferroelectric layer contains boron at concentrations ranging from 2 at% (inclusive) to 10 at% (inclusive).

9. The stacking structure according to claim 1, wherein The ferroelectric layer contains scandium at concentrations ranging from 5 at% (inclusive) to 45 at% (inclusive).

10. A memory device comprising a capacitor, the capacitor comprising the stacked structure of any one of claims 1 to 9.

11. A method for manufacturing a stacked structure, comprising: The underlayer is formed from one of tantalum, tantalum nitride, ruthenium, and platinum; A seed layer is formed on the underlying layer by one of ruthenium, platinum, nickel, and titanium; Electrodes are formed on the seed layer; as well as A layer comprising a ferroelectric layer and a tunnel barrier layer is formed on the electrode, wherein the ferroelectric layer and the tunnel barrier layer form a junction; The ferroelectric layer contains aluminum nitride with a concentration of 50 at% or more, and the tunnel barrier layer contains magnesium oxide with a concentration of 50 at% or more.

12. The method of claim 11, wherein The tunnel barrier layer is formed on the ferroelectric layer.

13. The method of claim 11, wherein The ferroelectric layer is formed on the tunnel barrier layer.

14. The method according to any one of claims 11 to 13, wherein The ferroelectric layer has a wurtzite structure, and the (001) surface of the wurtzite structure runs along the interface between the ferroelectric layer and the tunnel barrier layer.

15. The method according to any one of claims 11 to 13, wherein The tunnel barrier layer has a NaCl structure, and the (111) surface of the NaCl structure runs along the interface between the ferroelectric layer and the tunnel barrier layer.

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