Content addressable memory cell, content addressable memory device and method of operation thereof and method of data search comparison

Abstract

This invention provides a Content Addressable Memory (CAM) unit, a CAM memory device, an operation method thereof, and a data search and comparison method. The CAM unit includes: a first flash memory unit, a first terminal of which receives a first search voltage; and a second flash memory unit, a first terminal of which receives a second search voltage, and a second terminal of the first flash memory unit electrically connected to a second terminal of the second flash memory unit; wherein the first flash memory unit and the second flash memory unit are connected in series, and a stored data in the content addressable memory unit is determined by a combination of multiple threshold voltages of the first flash memory unit and the second flash memory unit.

Description

Technical Field

[0001] This invention relates to a Content Addressable Memory (CAM) unit, a CAM memory device, a method for operating the same, and a method for searching and comparing data. In particular, it relates to a CAM unit, a CAM memory device, a method for operating the same, and a method for searching and comparing data that can be used to implement an in-memory searching (IMS) system. Background Technology

[0002] With the rise of big data and artificial intelligence (AI) hardware accelerators, data search and comparison are crucial functions. Existing ternary content addressable memory (TCAM) can be used to achieve highly parallel searching. Traditional TCAMs are typically composed of static random access memory (SRAM), resulting in low storage density and high access power. To save power through denser storage, non-volatile memory arrays based on TCAMs have recently been proposed.

[0003] Compared to SRAM-based TCAMs with 16 transistors (16T), resistive random access memory (RRAM)-based TCAMs with a 2-transistor, 2-resistor (2T2R) structure have recently been developed to reduce cell area. Standby power consumption can also be improved by using non-volatile RRAM-based TCAMs. However, the limited resistivity (R-ratio) of RRAM makes it difficult to distinguish between matched and mismatched states, thus RRAM is insufficient for parallel searching of large amounts of data. Compared to the 2T2R structure, ferroelectric field-effect transistor (FeFET)-based TCAM arrays offer a higher on / off ratio and denser memory array, but the on / off ratio of FeFET devices is still not high enough, affecting matching accuracy, and therefore unsuitable for long-word search designs.

[0004] Furthermore, in DNA genome analysis, Next Generation Sequencing (NGS) technology is used to measure the number of DNA or RNA sequences. The genome is cut and sequenced into multiple data fragments (reads), and then these data fragments are mapped to a reference genome (called read mapping) for genome matching and localization. Because read mapping requires a large amount of memory, and communication limitations between memory and computing units (CPU / GPU) restrict read mapping, it becomes the most time-consuming part of the genome analysis process.

[0005] Therefore, there is a need for a Content Addressable Memory (CAM) unit, a CAM device, a method for operating the CAM, and a method for data searching and comparison, which can provide high matching accuracy and be suitable for long character search designs when used to implement in-memory searching (IMS) systems and genome analysis.

[0006] Public content

[0007] According to an embodiment of the present invention, a content-addressable memory cell is provided, comprising: a first flash memory cell, a first terminal of the first flash memory cell being used to receive a first search voltage; a second flash memory cell, a first terminal of the second flash memory cell being used to receive a second search voltage, and a second terminal of the first flash memory cell being electrically connected to a second terminal of the second flash memory cell; wherein the first flash memory cell and the second flash memory cell are connected in series, and a stored data in the content-addressable memory cell is determined by a combination of multiple threshold voltages of the first flash memory cell and the second flash memory cell.

[0008] According to another embodiment of the present invention, a content-addressable memory device is provided, comprising: a plurality of first content-addressable memory cell arrays, the first content-addressable memory cell arrays including a plurality of first content-addressable memory cells, each of the first content-addressable memory cells including a plurality of flash memory cells, a stored data of each of the first content-addressable memory cells being determined by a combination of a plurality of threshold voltages of the flash memory cells of the first content-addressable memory cells; a first word line driver for providing a plurality of first search voltages and a plurality of second search voltages to the first content-addressable memory cells; a plurality of first matching lines coupled to the first content-addressable memory cells; a plurality of first sense amplifiers coupled to the first matching lines; and a decoder coupled to the first sense amplifiers, wherein, when the first search voltages and the second search voltages are applied to the first content-addressable memory cells, the first sense amplifiers sense a plurality of first matching currents on the first matching lines to generate a plurality of first sensing results; based on the first sensing results, the decoder generates a first matching address, the first matching address indicating an individual address of the first content-addressable memory cells for which a first search result is matched.

[0009] According to another embodiment of the present invention, a method of operating a content-addressable memory device is provided, comprising: programming a plurality of content-addressable memory cells, each of the content-addressable memory cells including a plurality of flash memory cells, a stored data of each of the content-addressable memory cells being determined by a combination of a plurality of threshold voltages of the flash memory cells of the content-addressable memory cells, the content-addressable memory cells being coupled to a plurality of matching lines; applying a plurality of first search voltages and a plurality of second search voltages to the content-addressable memory cells; sensing a plurality of matching currents on the matching lines to generate a plurality of sensing results; and generating a matching address based on the sensing results, the matching address indicating an individual address of the content-addressable memory cells for which a search result is a match.

[0010] According to another embodiment of the present invention, a content-addressable memory device is provided, comprising: a plurality of content-addressable memory cell arrays, each of the content-addressable memory cell arrays including a plurality of content-addressable memory cells, each of the content-addressable memory cell arrays including a plurality of serial flash memory cells, wherein individual stored data of each of the content-addressable memory cell arrays relates to a portion of reference string data; a word line decoder and driver for providing a plurality of search voltages to the content-addressable memory cells, wherein, in a plurality of comparison rounds, the word line decoder and driver determines the search voltages applied to the content-addressable memory cells based on a data segment (read); a plurality of matching lines coupled to the content-addressable memory cells; a plurality of inductive counting circuits coupled to the matching lines; and a decoder coupled to the inductive counting circuits, wherein, in the plurality of comparison rounds, when the search voltages are applied to the content-addressable memory cells, the inductive counting circuits sense and count a plurality of matching currents on the matching lines to generate a plurality of counting results, and the decoder determines whether the data segment matches the reference string data based on the counting results of the inductive counting circuits.

[0011] According to another embodiment of the present invention, a data search and comparison method is proposed, comprising: programming a plurality of content-addressable memory cells, each of the content-addressable memory cells including a plurality of serially connected flash memory cells, wherein individual stored data in each of the content-addressable memory cells relates to a portion of a reference serial data, the content-addressable memory cells being coupled to a plurality of matching lines; applying a plurality of search voltages to the content-addressable memory cells, wherein in a plurality of comparison rounds, a data segment is used to determine the search voltages applied to the content-addressable memory cells; in the comparison rounds, sensing and counting a plurality of matching currents on the matching lines to generate a plurality of counting results; and determining, based on the counting results, whether the data segment matches the reference serial data.

[0012] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0013] Figure 1 This diagram illustrates a Content Addressable Memory (CAM) unit and its operation according to a first embodiment of the present invention.

[0014] Figure 2 This diagram illustrates a content-addressable memory cell and its operation according to a second embodiment of the present invention.

[0015] Figure 3This diagram illustrates a content-addressable memory cell and its operation according to a third embodiment of the present invention.

[0016] Figure 4 This diagram illustrates a content-addressable memory cell and its operation according to a fourth embodiment of the present invention.

[0017] Figure 5A This diagram shows a circuit schematic of a content-addressable memory device according to a fifth embodiment of the present invention.

[0018] Figure 5B This diagram illustrates the operation of a content-addressable memory device according to a fifth embodiment.

[0019] Figure 6A This diagram shows a circuit schematic of a content-addressable memory device according to a sixth embodiment of the present invention.

[0020] Figure 6B This diagram illustrates the operation of a content-addressable memory device according to the sixth embodiment.

[0021] Figure 7 This diagram shows a circuit schematic of a content-addressable memory device according to a seventh embodiment of the present invention.

[0022] Figure 8A This diagram illustrates the content-addressable memory device and its operation according to the eighth embodiment.

[0023] Figure 8B This diagram illustrates a second operation of the content-addressable memory device according to the eighth embodiment.

[0024] Figure 8C This diagram illustrates a third operation of the content-addressable memory device according to the eighth embodiment.

[0025] Figure 8D This diagram illustrates a fourth operation of the content-addressable memory device according to the eighth embodiment.

[0026] Figure 9 This diagram illustrates how wildcard characters can be used to speed up data search and comparison.

[0027] Figure 10 This invention illustrates an operation method of a content-addressable memory device according to a ninth embodiment of the present invention.

[0028] Figure 11 This invention illustrates an operation method of a content-addressable memory device according to a tenth embodiment of the present invention.

[0029] Explanation of reference numerals in the attached figures

[0030] 100, 200, 300, 400, 504, 604, 704, 804: Content-addressed memory units

[0031] 500A, 500B, 600, 700, 800: Content-addressable memory devices

[0032] 502-1~502-n, 602-1~602-2n, 702-1~702-2n, 802: Content-addressable memory cell serial array

[0033] 508, 608-1, 608-2, 708-1, 708-2: Word line drivers

[0034] 510-1~510-n, 610-1~610-2n, 710-1~710-2n, 812: Matching lines

[0035] 512-1~510-n, 612-1~612-2n, 712-1~712-2n, SA: Induction Amplifier

[0036] 514, 616, 716, 816: Decoders

[0037] 606, 704-1, 704-2, 806, T1, T2: Flash memory cells

[0038] 614-1~614n, 714-1~714n: Logic gates

[0039] 808: Word Line Decoder and Driver

[0040] 810: Bit line driver

[0041] 814-1~814-n: Inductive counting circuit

[0042] 820A, 820B, 820C, 820D: Reference serial data

[0043] 820A-1~820A-X, 820B-1~820B-X, 820C-1~820C-X, 820D-1~820D-X: Partial

[0044] 822A, 822B, 822C, 822D: Data Fragments

[0045] 822A-1~822A-Y, 822B-1~822A-3, 822C-1~822C-Y, 822D-1~822A-Y: Seed Data

[0046] 824, 826: Areas

[0047] MA, MB: Matching address

[0048] SL: Search Voltage

[0049] BL1~BL2n: Bit line voltage

[0050] SL_I~,SL(1)_1,SL(2)_1,...,SL(M)_1,SL(1)_1,SL(2)_1,...,SL(M)_1:First search voltage

[0051] SL_2, SL(1)_2, SL(2)_2, ..., SL(M)_2, SL(1)_2, SL(2)_2, ..., SL(2M)_2: Second search voltage

[0052] SL(M+1)_1, SL(M+2)_1, ..., SL(2M)_1: Third search voltage

[0053] SL(M+1)_2, SL(M+2)_2, ..., SL(2M)_2: Fourth search voltage

[0054] G1, G2: Gate

[0055] S1, S2: Source poles

[0056] C: Counter

[0057] 1002~1008, 1102~1108: Steps Detailed Implementation

[0058] The technical terms used in this specification refer to those commonly used in the field. Where this specification provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions provided in this specification. Each of the embodiments disclosed herein has one or more technical features. Where feasible, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0059] First Embodiment

[0060] Figure 1 This diagram illustrates a Content Addressable Memory (CAM) unit 100 and its operation according to a first embodiment of the present invention. Figure 1 As shown, the content-addressable memory unit 100 of the first embodiment of the present invention, for example but not limited to, can store two-bit multi-level CAM (MLC).

[0061] Content-addressed memory cell 100 includes two flash memory cells T1 and T2 connected in series. These flash memory cells are, for example but not limited to, floating gate memory cells, silicon-oxide-nitride-oxide-silicon (SONOS) memory cells, floating dot memory cells, ferroelectric FET (FeFET) memory cells, etc.

[0062] The gate G1 of flash memory cell T1 is used to receive the first search voltage SL-1, the gate G2 of flash memory cell T2 is used to receive the second search voltage SL_2, and the source S1 of flash memory cell T1 is electrically connected to the source S2 of flash memory cell T2.

[0063] Furthermore, in the first embodiment of the present invention, the threshold voltage (also referred to as the first threshold voltage) of flash memory cell T1, the threshold voltage (also referred to as the second threshold voltage) of flash memory cell T2, the first search voltage SL_1, and the second search voltage SL_2 can have various settings. Figure 1 In this context, the settings for the first threshold voltage, the second threshold voltage, the first search voltage SL_1, and the second search voltage SL_2 can be found in the table below, with details omitted here:

[0064]

[0065]

[0066] In the first embodiment of the present invention, when the stored data is a first predetermined stored data (00), the first threshold voltage is VT1 (also known as the minimum threshold voltage value), and the second threshold voltage is VT4 (also known as the maximum threshold voltage value); when the stored data is a second predetermined stored data (11), the first threshold voltage is a maximum threshold voltage value, and the second threshold voltage is a minimum threshold voltage value; when the stored data is a third predetermined stored data (XX (don't care)), both the first threshold voltage and the second threshold voltage are minimum threshold voltage values; when the stored data is a fourth predetermined stored data (i.e., invalid data), the first threshold voltage and the second threshold voltage are equal to or greater than a maximum threshold voltage value. That is, in the first embodiment of the present invention, the stored data of the content-addressed memory unit 100 is determined by the combination of the first threshold voltage and the second threshold voltage.

[0067] In the first embodiment of the present invention, when the search data is a first predetermined search data (00), the first search voltage SL_1 is VS1 (also known as the minimum search voltage value), and the second search voltage SL_2 is VS4 (also known as the maximum search voltage value), wherein the search data represents the data to be searched; when the search data is a second predetermined search data (11), the first search voltage SL_1 is a maximum search voltage value, and the second search voltage SL_2 is a minimum search voltage value; when the search data is a third predetermined search data (WC), both the first search voltage SL_1 and the second search voltage SL_2 are maximum search voltage values.

[0068] Therefore, during a search, when the search data matches the stored data, both flash memory cells T1 and T2 generate matching current, indicating a match. When the search data does not match the stored data, at least one of flash memory cells T1 and T2 is not conducting and no matching current is generated, indicating a mismatch. When the search data is a wildcard (WC), regardless of the value of the stored data, both flash memory cells T1 and T2 generate matching current, indicating a match. When the stored data is XX (don't care), regardless of the value of the search data, both flash memory cells T1 and T2 generate matching current, indicating a match. For example, when the search data (00) matches the stored data (00), both flash memory cell T1 and flash memory cell T2 generate matching current, indicating that the search result is a match; when the search data (00) does not match the stored data (01), flash memory cell T1 is turned off while flash memory cell T2 is turned on, and no matching current is generated, indicating that the search result is a mismatch. Therefore, the matching situation between the search data and the stored data can be summarized in the table below, the details of which are omitted here:

[0069]

[0070]

[0071] ○: Flash memory cell is on; X: Flash memory cell is not on.

[0072] In another embodiment, the search data is matched against the least similar stored data; that is, a match is considered complete when the found stored data is complementary to the search data. Details will now be explained. The settings for the first threshold voltage, the second threshold voltage, the first search voltage SL_1, and the second search voltage SL_2 can be as follows:

[0073]

[0074]

[0075]

[0076] For example, if the first threshold voltage and the second threshold voltage are VT1 and VT4 respectively, and the stored data is 00, then the stored data (00) is matched with the least similar search data (11) (i.e., the first search voltage SL_1 and the second search voltage SL_2 are VS4 and VS1 respectively), causing both flash memory cells T1 and T2 to be turned on and generate matching current, representing a matching search result; if the search data (11) is compared with the stored data (11) (i.e., the first threshold voltage and the second threshold voltage are VT4 and VT1 respectively), and flash memory cell T1 is turned on while flash memory cell T2 is turned off, then no matching current is generated, representing a mismatch search result; if the search data (11) is compared with the stored data (01) (i.e., the first threshold voltage and the second threshold voltage are VT2 and VT3 respectively), and flash memory cell T1 is turned on while flash memory cell T2 is turned off, then no matching current is generated, representing a mismatch search result. Therefore, the matching situation of the search data and the stored data can be summarized in the following table, the details of which are omitted here:

[0077]

[0078]

[0079] In another embodiment, the search data will be matched against the least similar (complementary) stored data. Details will now be explained. The settings for the first threshold voltage, the second threshold voltage, the first search voltage SL_1, and the second search voltage SL_2 can be as follows:

[0080]

[0081]

[0082] For example, if the first search voltage SL_1 and the second search voltage SL_2 are VS4 and VS1 respectively (i.e., the search data is 00), then the search data (00) matches the least similar (complementary) stored data (11) (i.e., the first threshold voltage and the second threshold voltage are VT4 and VT1 respectively), causing both flash memory cells T1 and T2 to conduct and generate matching current, indicating that the search result is a match; if the search data (00) is compared with the stored data (00) (i.e., the first threshold voltage and the second threshold voltage are VT1 and VT4 respectively), and flash memory cell T1 is on while flash memory cell T2 is off, then no matching current will be generated, indicating that the search result is a mismatch; if the search data (00) is compared with the stored data (01) (i.e., the first threshold voltage and the second threshold voltage are VT2 and VT3 respectively), and flash memory cell T1 is on while flash memory cell T2 is off, then no matching current will be generated, indicating that the search result is a mismatch. Therefore, the matching situation of the search data and the stored data can be summarized in the following table, the details of which are omitted here:

[0083]

[0084] Second Embodiment

[0085] Please refer to Figure 2 The diagram shows a content-addressable memory unit 200 and its operation according to a second embodiment of the present invention. The content-addressable memory unit 200, for example but not limited to, can store three-dimensional triple-level CAM (TLC).

[0086] In the second embodiment of the present invention, the first threshold voltage, the second threshold voltage, the first search voltage SL_1, and the second search voltage SL_2 may also be set differently. Figure 2 In this context, the settings for the first threshold voltage, the second threshold voltage, the first search voltage SL_1, and the second search voltage SL_2 can be found in the table below, with details omitted here:

[0087]

[0088]

[0089]

[0090] In the second embodiment of the present invention, when the stored data is a first predetermined stored data (000), the first threshold voltage is VT1 (also known as the minimum threshold voltage value), and the second threshold voltage is VT8 (also known as the maximum threshold voltage value); when the stored data is a second predetermined stored data (111), the first threshold voltage is a maximum threshold voltage value, and the second threshold voltage is a minimum threshold voltage value; when the stored data is a third predetermined stored data (XXX (don't care)), both the first threshold voltage and the second threshold voltage are minimum threshold voltage values; when the stored data is a fourth predetermined stored data (i.e., invalid data), the first threshold voltage and the second threshold voltage are equal to or greater than a maximum threshold voltage value. That is, in the second embodiment of the present invention, the stored data of the content-addressed memory unit 200 is determined by the combination of the first threshold voltage and the second threshold voltage.

[0091] In the second embodiment of the present invention, when the search data is the first predetermined search data (000), the first search voltage SL_1 is VS1 (also known as the minimum search voltage value), and the second search voltage SL_2 is VS8 (also known as the maximum search voltage value); when the search data is the second predetermined search data (111), the first search voltage SL_1 is a maximum search voltage value, and the second search voltage SL_2 is a minimum search voltage value; when the search data is the third predetermined search data (WC), both the first search voltage SL_1 and the second search voltage SL_2 are maximum search voltage values.

[0092] Therefore, during a search, when the search data matches the stored data, both flash memory cells T1 and T2 generate matching current, indicating a match. When the search data does not match the stored data, at least one of flash memory cells T1 and T2 is not conducting and no matching current is generated, indicating a mismatch. When the search data is a wildcard (WC), regardless of the value of the stored data, both flash memory cells T1 and T2 generate matching current, indicating a match. When the stored data is XX (don't care), regardless of the value of the search data, both flash memory cells T1 and T2 generate matching current, indicating a match. For example, when search data (000) matches stored data (000), both flash memory cell T1 and flash memory cell T2 generate matching current, indicating a match in the search results; when search data (000) does not match stored data (001), flash memory cell T1 is turned off while flash memory cell T2 is turned on, and no matching current is generated, indicating a non-match in the search results. Therefore, the matching status of search data and stored data can be summarized in the table below, the details of which are omitted here:

[0093]

[0094]

[0095]

[0096] Third Embodiment

[0097] Please refer to Figure 3 The diagram shows a content-addressable memory unit 300 and its operation according to a third embodiment of the present invention. The content-addressable memory unit 300, for example but not limited to, can store a four-bit quad-level CAM (QLC).

[0098] In the third embodiment of the present invention, the first threshold voltage, the second threshold voltage, the first search voltage SL_1, and the second search voltage SL_2 may also be set differently. Figure 3 In this context, the settings for the first threshold voltage, the second threshold voltage, the first search voltage SL_1, and the second search voltage SL_2 can be found in the table below, with details omitted here:

[0099]

[0100]

[0101]

[0102]

[0103] In the third embodiment of the present invention, when the stored data is a first predetermined stored data (0000), the first threshold voltage is VT1 (also known as the minimum threshold voltage value), and the second threshold voltage is VT16 (also known as the maximum threshold voltage value); when the stored data is a second predetermined stored data (1111), the first threshold voltage is a maximum threshold voltage value, and the second threshold voltage is a minimum threshold voltage value; when the stored data is a third predetermined stored data (XXXX (don't care)), both the first threshold voltage and the second threshold voltage are minimum threshold voltage values; when the stored data is a fourth predetermined stored data (i.e., invalid data), the first threshold voltage and the second threshold voltage are equal to or greater than a maximum threshold voltage value. That is, in the third embodiment of the present invention, the stored data of the content-addressed memory unit 300 is determined by the combination of the first threshold voltage and the second threshold voltage.

[0104] In the third embodiment of the present invention, when the search data is the first predetermined search data (0000), the first search voltage SL_1 is VS1 (also known as the minimum search voltage value), and the second search voltage SL_2 is VS16 (also known as the maximum search voltage value); when the search data is the second predetermined search data (1111), the first search voltage SL_1 is a maximum search voltage value, and the second search voltage SL_2 is a minimum search voltage value; when the search data is the third predetermined search data (WC), both the first search voltage SL_1 and the second search voltage SL_2 are maximum search voltage values.

[0105] In the third embodiment of the present invention, when the search data matches the stored data, both flash memory unit T1 and flash memory unit T2 generate a matching current, indicating that the search result is a match; when the search data does not match the stored data, at least one of flash memory unit T1 and flash memory unit T2 is not conducting and no matching current is generated, indicating that the search result is a mismatch. That is, the matching conditions between the stored data and the search data in the third embodiment of the present invention are similar to those in the first and second embodiments of the present invention, and the details are omitted here.

[0106] Fourth embodiment

[0107] Please refer to Figure 4 The diagram shows a content-addressable memory unit 400 and its operation according to a fourth embodiment of the present invention. The content-addressable memory unit 400, for example but not limited to, can store a five-bit penta-level CAM (PLC).

[0108] In the fourth embodiment of the present invention, the first threshold voltage, the second threshold voltage, the first search voltage SL_1, and the second search voltage SL_2 may also be set differently. Figure 4 In this context, the settings for the first threshold voltage, the second threshold voltage, the first search voltage SL_1, and the second search voltage SL_2 can be found in the table below, with details omitted here:

[0109]

[0110]

[0111]

[0112]

[0113]

[0114] In the fourth embodiment of the present invention, when the stored data is a first predetermined stored data (00000), the first threshold voltage is VT1 (also known as the minimum threshold voltage value), and the second threshold voltage is VT32 (also known as the maximum threshold voltage value); when the stored data is a second predetermined stored data (11111), the first threshold voltage is a maximum threshold voltage value, and the second threshold voltage is a minimum threshold voltage value; when the stored data is a third predetermined stored data (XXXXX(don't care)), both the first threshold voltage and the second threshold voltage are minimum threshold voltage values; when the stored data is a fourth predetermined stored data (i.e., invalid data), the first threshold voltage and the second threshold voltage are equal to or greater than a maximum threshold voltage value. That is, in the fourth embodiment of the present invention, the stored data of the content-addressed memory unit 400 is determined by the combination of the first threshold voltage and the second threshold voltage.

[0115] In the fourth embodiment of the present invention, when the search data is the first predetermined search data (00000), the first search voltage SL_1 is VS1 (also known as the minimum search voltage value), and the second search voltage SL_2 is VS32 (also known as the maximum search voltage value); when the search data is the second predetermined search data (11111), the first search voltage SL_1 is a maximum search voltage value, and the second search voltage SL_2 is a minimum search voltage value; when the search data is the third predetermined search data (WC), both the first search voltage SL_1 and the second search voltage SL_2 are maximum search voltage values.

[0116] In the fourth embodiment of the present invention, when the search data matches the stored data, both flash memory unit T1 and flash memory unit T2 generate a matching current, indicating that the search result is a match; when the search data does not match the stored data, at least one of flash memory unit T1 and flash memory unit T2 is not conducting and no matching current is generated, indicating that the search result is a mismatch. That is, the matching conditions between the stored data and the search data in the fourth embodiment of the present invention are similar to those in the first, second, and third embodiments of the present invention, and the details are omitted here.

[0117] Fifth embodiment

[0118] Figure 5A A circuit diagram of a CAM memory device 500A according to a fifth embodiment of the present invention is shown. Figure 5B This diagram shows an operation schematic of the CAM memory device 500A according to the fifth embodiment.

[0119] like Figure 5AAs shown, the CAM memory device 500A according to the fifth embodiment includes a plurality of content-addressable memory cell arrays 502-1 to 502-n, a word line driver 508, a plurality of matching lines 510-1 to 510-n, a plurality of induction amplifiers 512-1 to 512-n, and a decoder 514.

[0120] These content-addressable memory cell arrays 502-1 to 502-n include multiple content-addressable memory cells 504, and these content-addressable memory cells 504 include multiple serial flash memory cells 506. These content-addressable memory cells 504 may be the same as or similar to the content-addressable memory cell 100 of the first embodiment, the content-addressable memory cell 200 of the second embodiment, the content-addressable memory cell 300 of the third embodiment, and the content-addressable memory cell 400 of the fourth embodiment.

[0121] Word line driver 508 provides multiple first search voltages SL(1)_1, SL(2)_1, ..., SL(M)_1 and multiple second search voltages SL(1)_2, SL(2)_2, ..., SL(M)_2 to these content-addressed memory cells 504. Bit line voltages BL1 to BLn are applied to these content-addressed memory cell arrays 502-1 to 502-n. Matching lines 510-1 to 510-n are coupled to these content-addressed memory cells 504, sense amplifiers 512-1 to 510-n are coupled to these matching lines 510-1 to 510-n, and decoder 514 is coupled to these sense amplifiers 512-1 to 510-n.

[0122] In the fifth embodiment of the present invention, a stored data in the content-addressable memory unit 504 is determined by a combination of multiple threshold voltages of the flash memory unit 506 of the content-addressable memory unit 504. The threshold voltage settings of the content-addressable memory unit 504 can be the same as or similar to those in the first, second, third, and fourth embodiments; and the settings of the first search voltages SL(1)_1, SL(2)_1, ..., SL(M)_1 and the second search voltages SL(1)_2, SL(2)_2, ..., SL(M)_2 can be the same as or similar to those in the first, second, third, and fourth embodiments. Therefore, the details are omitted here.

[0123] When the first search voltages SL(1)_1, SL(2)_1, ..., SL(M)_1 and the second search voltages SL(1)_2, SL(2)_2, ..., SL(M)_2 are applied to the content-addressed memory cells 504, the inductive amplifiers 512-1 to 510-n sense multiple matching currents on the matching lines 510-1 to 510-n to generate multiple first sensing results. Based on these first sensing results, the decoder 514 generates a matching address MA, which indicates the individual address of the content-addressed memory cells 504 in the array of content-addressed memory cells whose stored data matches the search data.

[0124] At Figure 5A In the search data, there are multiple search characters, and the stored data in the content-addressed memory unit 504 includes multiple data characters.

[0125] To understand the operation of the fifth embodiment, please refer to Figure 5B The following example illustrates the threshold voltage setting and search voltage setting as described in the first embodiment, with the search word being [10110001], the first data word (Data word 1) being [10110001], the second data word (Data word 2) being [10100001], and the third data word (Data word 3) being [01001110]. It should be understood that the present invention is not limited thereto.

[0126] When the search word [10110001] is used to search the content-addressable memory cell array 502-1 (which stores the first data word [10110001]), all flash memory cells of the content-addressable memory cell array 504 in the content-addressable memory cell array 502-1 are turned on, thus generating a matching current on the relevant matching line 510-1. When the search word [10110001] is used to search the first data word [10110001], the search result is a match. Here, MA represents the address of the content-addressable memory cell in the content-addressable memory cell array 502-1.

[0127] Similarly, when searching the content-addressed memory cell array 502-2 (which stores the second data character [10100001]) with the search character [10110001], at least one flash memory cell of these content-addressed memory cells 504 in the content-addressed memory cell array 502-2 is turned off, and therefore no matching current is generated on the associated matching line 510-2. When searching the second data character [10100001] with the search character [10110001], the search result is a mismatch.

[0128] Similarly, when searching for the third data character [01001110] with the search character [10110001], the search result is a mismatch.

[0129] Sixth Embodiment

[0130] Figure 6A A circuit diagram of a CAM memory device 600 according to a sixth embodiment of the present invention is shown. Figure 6B This diagram shows an operation schematic of the CAM memory device 600 according to the sixth embodiment.

[0131] like Figure 6A As shown, the CAM memory device 600 according to the sixth embodiment includes a plurality of content-addressable memory cell arrays 602-1 to 602-2n, word line drivers 608-1 and 608-2, a plurality of matching lines 610-1 to 610-2n, a plurality of induction amplifiers 612-1 to 612-2n, a plurality of logic gates 614-1 to 614n, and a decoder 616.

[0132] These content-addressable memory cell arrays 602-1 to 602-2n include multiple content-addressable memory cells 604, and these content-addressable memory cells 604 include multiple serial flash memory cells 606. These content-addressable memory cells 604 may be identical or similar to the content-addressable memory cell 100 of the first embodiment, the content-addressable memory cell 200 of the second embodiment, the content-addressable memory cell 300 of the third embodiment, and the content-addressable memory cell 400 of the fourth embodiment.

[0133] Word line driver 608-1 provides multiple first search voltages SL(1)_1, SL(2)_1, ..., SL(M)_1 and multiple second search voltages SL(1)_2, SL(2)_2, ..., SL(M)_2 to these content-addressable memory cells 604. Word line driver 608-2 provides multiple third search voltages SL(M+1)_1, SL(M+2)_1, ..., SL(2M)_1 and multiple fourth search voltages SL(M+1)_2, SL(M+2)_2, ..., SL(2M)_2 to these content-addressable memory cells 604.

[0134] Bit line voltages BL1 to BL(2n) are applied to these content-addressable memory cell arrays 602-1 to 602-2n. These matching lines 610-1 to 610-2n are coupled to these content-addressable memory cells 604.

[0135] These inductive amplifiers 612-1 to 612-2n are coupled to these matching lines 610-1 to 610-2n to sense the matching current generated by these content-addressed memory cell arrays 602-1 to 602-2n.

[0136] These logic gates 614-1 to 614-n receive the sensing results from the corresponding inductive amplifiers 612-1 to 612-2n and output the logic operation result to the decoder 616. For example, logic gate 614-1 receives the sensing results from the corresponding inductive amplifiers 612-1 and 612-(n+1) and outputs the logic operation result to the decoder 616. Logic gates 614-1 to 614-n are, for example, but not limited to, AND logic gates.

[0137] In the sixth embodiment of the present invention, a stored data of the content-addressable memory unit 604 is determined by a combination of multiple threshold voltages of the flash memory unit 606 of the content-addressable memory unit 604. The threshold voltage settings of the content-addressable memory unit 604 may be the same as or similar to those of the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment; and the settings of these search voltages SL(1)_1 to SL(2M)_2 may be the same as or similar to those of the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment, so the details are omitted here.

[0138] When the first search voltages SL(1)_1, SL(2)_1, ..., SL(M)_1, the second search voltages SL(1)_2, SL(2)_2, ..., SL(M)_2, the third search voltages SL(M+1)_1, SL(M+2)_1, ..., SL(2M)_1, and the fourth search voltages SL(M+1)_2, SL(M+2)_2, ..., ~SL(2M)_2 are applied to the content-addressed memory cells 604, the inductive amplifiers 612-1 to 612-2n sense multiple matching currents on the matching lines 610-1 to 610-2n to generate multiple first sensing results and second sensing results. The logic gates 614-1 to 614-n perform logical operations based on the first sensing results of the inductive amplifiers 612-1 to 612-n and the second sensing results of the inductive amplifiers 612-(n+1) to 612-2n to generate multiple logical operation results. The decoder 616 generates matching addresses MA and MB based on the logical operation results of these first sensing results and these second sensing results. The matching addresses MA and MB indicate the individual addresses of the content-addressed memory cells 604 in the content-addressed memory cell array where the stored data matches the search data.

[0139] exist Figure 6AIn the search data, there are multiple search characters, and the stored data in the content-addressed memory unit 604 includes multiple data characters.

[0140] The sixth embodiment is applicable to long search characters. A long character can be split into two characters (or more characters). This will be explained below.

[0141] To understand the operation of the sixth embodiment, please refer to Figure 6B The threshold voltage and search voltage settings are as described in the first embodiment. The long search word is split into a first search word [10110001] and a second search word [11001010]. The long data word is split into: the first data word (Data word 1) is [10110001] (stored in content-addressed memory unit string 602-1) and the second data word (Data word 2) is [11001010] (stored in content-addressed memory unit string 602-(n+1)). Similarly, another long data word is split into: the third data word (Data word 3) is [01001110] (stored in content-addressed memory unit string 602-2) and the fourth data word (Data word 4) is [11001010] (stored in content-addressed memory unit string 602-(n+2)). Similarly, another long data word is broken down into: the fifth data word (Data word 5) is [11011010] (stored in content-addressable memory unit string 602-3), and the sixth data word (Data word 6) is [00110101] (stored in content-addressable memory unit string 602-(n+3)). The above example is for illustration only, and it should be understood that the present invention is not limited thereto.

[0142] When the first data character [10110001] is searched using the first search character [10110001], all flash memory cells of all content-addressable memory cells 604 in the content-addressable memory cell array 602-1 are turned on to generate a matching current. Therefore, when the first data character [10110001] is searched using the first search character [10110001], the search result is a match, and the sensing amplifier 612-1 senses the matching current to generate a logic value 1 (i.e., the first sensing result). Similarly, when the second data character [11001010] is searched using the second search character [11001010], all flash memory cells of all content-addressable memory cells 604 in the content-addressable memory cell array 602-(n+1) are turned on to generate a matching current. Therefore, when the second data character [11001010] is searched for using the second search character [11001010], the search result is a match, and the sensing amplifier 612-(n+1) senses the matching current to generate a logic value 1 (i.e., the second sensing result). Since both inputs of logic gate 614-1 are logic 1, logic gate 614-1 outputs logic 1 to decoder 616. Decoder 616 generates matching addresses MA and MB accordingly, where matching address MA represents the address of these content-addressed memory units 604 in content-addressed memory unit array 602-1; matching address MB represents the address of these content-addressed memory units 604 in content-addressed memory unit array 602-(n+1).

[0143] Similarly, when the first search character [10110001] is used to search for the third data character [01001110], the search result is a mismatch, and the sensing amplifier 612-2 does not sense a matching current and generates a logic value of 0 (i.e., the first sensing result). Similarly, when the second search character [11001010] is used to search for the fourth data character [11001010], the search result is a match, and the sensing amplifier 612-(n+2) senses a matching current and generates a logic value of 1 (i.e., the second sensing result). However, since the two inputs of the logic gate 614-2 are not both logic 1, the logic gate 614-2 outputs logic 0 to the decoder 616.

[0144] Similarly, when the first search character [10110001] is used to search for the fifth data character [11011010], the search result is a mismatch, and the sensing amplifier 612-3 does not sense a matching current and generates a logic value of 0 (i.e., the first sensing result). Similarly, when the second search character [11001010] is used to search for the sixth data character [00110101], the search result is a mismatch, and the sensing amplifier 612-(n+3) does not sense a matching current and generates a logic value of 0 (i.e., the second sensing result). However, since the two inputs of the logic gate 614-3 are not both logic 1, the logic gate 614-3 outputs logic 0 to the decoder 616.

[0145] Thus, the CAM memory device 600 can search for long characters, thereby improving the performance of the content-addressable memory device. Furthermore, the CAM memory device 600 can reduce the length of the content-addressable memory cell array (e.g., a NAND array) to reduce RC latency, thereby accelerating the response speed of the content-addressable memory device.

[0146] Seventh Embodiment

[0147] Figure 7 A circuit diagram of a CAM memory device 700 according to a seventh embodiment of the present invention is shown.

[0148] like Figure 7 As shown, the CAM memory device 700 according to the seventh embodiment includes a plurality of content-addressable memory cell arrays 702-1 to 702-2n, word line drivers 708-1 and 708-2, a plurality of matching lines 710-1 to 710-2n, a plurality of sense amplifiers 712-1 to 712-2n, a plurality of logic gates 714-1 to 714n, and a decoder 716. Bit line voltages BL1 to BL(2n) are applied to these content-addressable memory cell arrays 702-1 to 702-2n. The storage data, threshold voltage settings, and matching operation methods of these content-addressable memory cells 704 of the CAM memory device 700 are the same as or similar to those of the CAM memory device 600 of the sixth embodiment, the details of which are omitted here.

[0149] In the seventh embodiment, the content-addressable memory unit 704 includes two flash memory units, which belong to different content-addressable memory unit strings. For example, the content-addressable memory unit 704 includes two flash memory units 704-1 and 704-2, which belong to different content-addressable memory unit strings 702-n and 702-2n, respectively.

[0150] Eighth embodiment

[0151] Please refer to Figures 8A to 8D The eighth embodiment shows a content-addressable memory device 800 and four schematic diagrams of its operation.

[0152] like Figures 8A to 8D As shown, the content-addressable memory device 800 includes a plurality of content-addressable memory cell arrays 802, word line decoders and drivers 808, bit line drivers 810, multiple matching lines 812, multiple inductive counting circuits (SC) 814-1 to 814-n and decoder 816.

[0153] These content-addressable memory cell arrays 802 include multiple content-addressable memory cells 804, and these content-addressable memory cells 804 include multiple flash memory cells 806. These content-addressable memory cells 804 may be the same as or similar to the content-addressable memory cell 100 of the first embodiment, the content-addressable memory cell 200 of the second embodiment, the content-addressable memory cell 300 of the third embodiment, the content-addressable memory cell 400 of the fourth embodiment, the content-addressable memory cell 504 of the fifth embodiment, and the content-addressable memory cell 604 of the sixth embodiment.

[0154] Word line decoder and driver 808 provides multiple search voltages SL to these content-addressable memory cells 804. Matching lines 812 are coupled to these content-addressable memory cells 804, inductive counting circuits 814-1 to 814-n are coupled to these matching lines 812, and decoder 816 is coupled to these inductive counting circuits 814-1 to 814-n.

[0155] Each of these inductive counting circuits 814-1 to 814-n includes multiple inductive amplifiers SA and counters C. These inductive amplifiers SA are used to sense whether there is a matching current in the corresponding content-addressed memory cell array 802. For example, inductive counting circuit 814-1 is coupled to the first to sixth content-addressed memory cell arrays 802 to sense the matching current of the first to sixth content-addressed memory cell arrays 802; inductive counting circuit 814-2 is coupled to the fourth to ninth content-addressed memory cell arrays 802 to sense the matching current of the fourth to ninth content-addressed memory cell arrays 802, and so on.

[0156] When a matching current is sensed in the corresponding content-addressable memory cell array 802, these sensing amplifiers SA output the sensing result to counter C. Counter C then counts the number of sensing amplifiers SA that output the sensing result to obtain the count result.

[0157] In the eighth embodiment of the present invention, individual stored data in the content-addressable memory cell array 802 relates to a portion of a reference string data 820A. The reference string data 820A, for example, but not limited to, is a genome. Figure 8A As shown, the reference string data 820A includes multiple parts 820A-1 to 820A-X (X is a positive integer). The reference string data 820A includes, for example but not limited to, CAATCCCCATCATTAAAGCGATGGCACACAGCATGCCCAATGACTGATTTAGCA. The first part 820A-1 of the reference string data 820A includes the 1st to 4th data bits (CAAT), stored in the first content-addressed memory cell string 802; the second part 820A-2 of the reference string data 820A includes the 5th to 8th data bits (CCCC), stored in the second content-addressed memory cell string 802, and so on. The Xth part 820A-X of the reference string data 820A includes the last two data bits (CA), stored in one of these content-addressed memory cell strings 802. The reference string data is not selected using a sliding method, therefore it can be called a fixed reference string data selection method.

[0158] In multiple comparison rounds, the word line decoder and driver 808 determines the search voltages SL applied to the content-addressed memory units 804 based on a data segment (read) 822A. Specifically, in each comparison round, the word line decoder and driver 808 selects one of a seed data 822A-1 to 822A-Y (where Y is a positive integer; in example 8A, Y = 12, but the invention is not limited thereto) from the data segment 822A, and the word line decoder and driver 808 determines the search voltages SL applied to the content-addressed memory units 804 based on the selected seed data 822A-1 to 822A-Y.

[0159] like Figure 8A As shown, data segment 822A includes multiple data bits, such as, but not limited to, AAAGCGATGGCACA. The first four data bits (AAAG) of data segment 822A are used as seed data 822A-1 for the first alignment round, the second to fifth data bits (AAGC) of data segment 822A are used as seed data 822A-2 for the second alignment round, and so on. This is called the sliding seed selection method.

[0160] Specifically, when the number of data bits in the seed data of the last or several comparison rounds is small, one or more wildcards (WC) are applied to the seed data with the smaller number of data bits, so that the number of data bits in the seed data of the last or several comparison rounds is equal to the number of data bits in the seed data of the previous comparison rounds. For example... Figure 8A As shown, the seed data 822A-12 for the last alignment round consists of the last 3 data bits (ACA) of data segment 822A. Since its number of data bits is relatively small, a wildcard character X is added to the seed data 822A-12 for the last alignment round, making the number of data bits in the seed data of the last alignment round equal to the number of data bits in the seed data of the previous alignment rounds. By adding the wildcard character X to the seed data of the last or several last alignment rounds, the seed data of each alignment round has the same number of data bits.

[0161] In the eighth embodiment, A, T, C, and G represent, for example but not limited to, 00, 01, 10, and 11. For example, when content-addressed memory cell 804 is written to A, it means that the stored data 00 is stored in content-addressed memory cell 804. Similarly, using seed data 822A-1 as AAAAG represents setting the search voltage to 00, 00, 00, and 11. The rest can be deduced in the same way. As for the setting of the threshold voltage and search voltage, refer to the previous embodiments, and the details are not repeated here.

[0162] Therefore, during these comparison rounds, when these search voltages SL are applied to these content-addressable memory cells 804, these inductive counting circuits 814-1 to 814-n sense and count multiple matching currents on these matching lines 812 to generate multiple counting results. The decoder 816 determines whether the data segment 822A matches the reference serial data 820A based on these counting results of the inductive counting circuits 814-1 to 814-n.

[0163] like Figure 8AAs shown, the individual stored data of the 5th to 7th content address memory cell array 802 are matched with the seed data 822A-3 (AGCG) of the 3rd comparison round, the seed data 822A-7 (ATGG) of the 7th comparison round, and the seed data 822A-11 (CACA) of the 11th comparison round, respectively, to generate 3 matching currents. Therefore, the inductive counting circuit 814-1 corresponding to the 5th-6th content-addressed memory cell array 802 senses and counts 2 matching currents to generate a counting result (2), the inductive counting circuit 814-2 corresponding to the 5th-7th content-addressed memory cell array 802 senses and counts 3 matching currents to generate a counting result (3), and the inductive counting circuit 814-3 corresponding to the 7th content-addressed memory cell array 802 senses and counts 1 matching current to generate a counting result (1). Thus, the inductive counting circuit 814 corresponding to the 5th-7th content-addressed memory cell array 802 (with the highest counting result) is selected as a candidate inductive counting circuit. The above operation method is called read mapping using a seed and vote strategy.

[0164] When the counting result of the candidate inductive counting circuits of these inductive counting circuits 814 is higher than a threshold (e.g., 2), it means that the above-mentioned seed and voting strategy is successful, and the decoder 816 determines that the data segment 822A matches the reference serial data 820A. Figure 8A As shown, the counting result (3) of the inductive counting circuit 814-2 (i.e., the candidate inductive counting circuit) corresponding to the 5th-7th content address memory cell array 802 is greater than the threshold (2), and the seed and voting strategy is successful. Therefore, the decoder 816 determines that the data segment 822A matches a part of the reference array data 820A based on the counting result (3).

[0165] like Figure 8AAs shown, when the effective length of the seed data 822A-1 to 822A-Y is less than the number of content-addressed memory cells in the content-addressed memory cell array 802, a portion of the content-addressed memory cell array 802, as shown in region 824, stores "don't care" data, ensuring that these content-addressed memory cells 804 in region 824 are turned on regardless of the search voltage received. Alternatively, when the effective length of the seed data 822A-1 to 822A-Y is less than the number of content-addressed memory cells in the content-addressed memory cell array 802, a universal character search voltage is applied to these content-addressed memory cells 804 in region 824, which also turns on all content-addressed memory cells 804 in region 824. The effective length refers to the number of data bits of the seed data input to the content-addressed memory cell array 802 during each comparison round.

[0166] like Figure 8A As shown, when all portions 820A-1 to 820A-X of the reference serial data 820A have been stored in the content addressing memory cell series 802, if there are remaining content addressing memory cells 804, as shown in region 826, that have not been written to portions 820A-1 to 820A-X of the reference serial data 820A, then invalid data (as in the first to third embodiments) is written to these remaining content addressing memory cells 804. In this way, regardless of the applied search voltage, no current flows through these remaining content addressing memory cells 804 in region 826.

[0167] In one embodiment, a longer data segment represents more seed data. Therefore, using a longer data segment and reference string data reading mapping can reduce voting uncertainty and improve the performance of the seed and voting strategy.

[0168] Thus, through Figure 8A The content-addressable memory device 800 and its operation mode can correctly match data segments and reference serial data, and solve the misalignment problem of seed data.

[0169] Please refer to Figure 8B This shows a second operational schematic diagram of the content-addressable memory device 800 according to the eighth embodiment. Figure 8B Compared to Figure 8A The difference in the operation mode of the content-addressable memory device 800 is that it adopts the sliding reference method instead of the sliding seed method, the details of which will be explained below.

[0170] like Figure 8BAs shown, reference string data 820B includes multiple parts 820B-1 to 820B-X (X is a positive integer). Reference string data 820B includes, for example but not limited to, CAATCCCCATCATTAAAGCGATGGCACACAGCATGCCCAATGACTGATTTAGCA. The first part 820A-1 of reference string data 820B, including the 1st to 4th data bits (CAAT), is stored in the first content-addressed memory cell string 802; the second part 820A-2, including the 2nd to 5th data bits (AATC), is stored in the second content-addressed memory cell string 802, and so on. The Xth part 820B-X of reference string data 820B, including the last data bit (A), is stored in one of these content-addressed memory cell strings 802. This operation is called the sliding reference string data method.

[0171] like Figure 8B As shown, data segment 822B includes multiple data bits, such as, but not limited to, AAAGCGATGGCACA. The first four data bits (AAAG) of data segment 822B are used as seed data 822B-1 for the first alignment round, the fifth to eighth data bits (CGAT) of data segment 822B are used as seed data 822B-2 for the second alignment round, and so on. This is called the fixed seed selection method.

[0172] In the third alignment round, the seed data 822B-3 consists of the last two data bits (GG) of data segment 822B. Since the number of data bits is relatively small, two wildcard characters XX are applied to the seed data 822B-3 of the third alignment round to make the number of data bits of the seed data 822B-3 of the third alignment round equal to the number of data bits of the seed data in the previous alignment rounds.

[0173] Please refer to Figure 8C This shows a third operation schematic diagram of the content-addressable memory device 800 according to the eighth embodiment. Figure 8C The difference in operation between the content-addressable memory device 800 and the content-addressable memory device 800 shown in Figures 8A and 8B lies in the simultaneous use of a sliding seed method and a sliding reference serial data method for read mapping, the details of which will be explained below.

[0174] like Figure 8CAs shown, the reference string data 820C includes multiple parts 820C-1 to 820C-X (X is a positive integer). The reference string data 820C includes, for example but not limited to, TAATCCCCATCATTAAAGCGATGGCACACAGCATGCCCAATGACTGATTTAGCA. Using a sliding reference string data method, the first to third data bits (TAA) of the reference string data 820C are stored in the first content-addressed memory cell string 802, the second to fourth data bits (AAT) of the reference string data 820C are stored in the second content-addressed memory cell string 802, and so on. The Xth part 820C-X of the reference string data 820C includes the last data bit (A), and is stored in one of these content-addressed memory cell strings 802.

[0175] like Figure 8C As shown, data segment 822C includes multiple data bits, such as, but not limited to, AAAGCGATG. A sliding seed method is used, with the first three data bits (AAA) of data segment 822C serving as seed data 822C-1 for the first alignment round, the second to fourth data bits (AAG) of data segment 822C serving as seed data 822C-2 for the second alignment round, and so on. The seed data 822C-Y for the last alignment round consists of the last three data bits (ATG) of data segment 822C.

[0176] Please refer to Figure 8D This shows a fourth operational schematic diagram of the content-addressable memory device 800 according to the eighth embodiment. Figure 8D The difference in operation between the content-addressable memory device 800 and Figures 8A, 8B, and 8C lies in the use of a fixed seed data method and a fixed reference serial data method for read mapping, the details of which will be explained below.

[0177] like Figure 8DAs shown, the reference string data 820D includes multiple parts 820D-1 to 820D-X (where X is a positive integer). The reference string data 820D includes, for example but not limited to, CAATCCCCATCATTAAAGCGATGGCACACAGCATGCCCAATGACTGATTTAGCA. The first part 820D-1 of the reference string data 820D includes the 1st to 4th data bits (CAAT), stored in the first content-addressed memory unit string 802; the second part 820D-2 includes the 5th to 8th data bits (CCCC), stored in the second content-addressed memory unit string 802, and so on. The Xth part 820D-X of the reference string data 820D includes the last two data bits (CA), stored in one of these content-addressed memory unit strings 802. This method of selecting a portion from the reference string data is called the fixed reference string data method.

[0178] like Figure 8D As shown, data segment 822D includes multiple data bits, such as, but not limited to, AAAGCGATGGCACA. The first four data bits (AAAG) of data segment 822D are used as seed data 822D-1 for the first alignment round, the fifth to eighth data bits (CGAT) of data segment 822D are used as seed data 822D-2 for the second alignment round, and so on. This method of selecting seed data from data segments is called the fixed seed data method.

[0179] In this case, the seed data 822D-Y of the last comparison round consists of the last two data bits (CA) of data segment 822D. Since the number of data bits is relatively small, two wildcard characters XX are applied to the seed data 822D-Y of the last comparison round to make the number of data bits of the seed data 822D-Y of the last comparison round equal to the number of data bits of the seed data in the previous comparison rounds.

[0180] In one embodiment, a longer data segment represents more seed data. Therefore, using a longer data segment and reference string data reading mapping can reduce voting uncertainty and improve the performance of the seed and voting strategy.

[0181] Thus, based on the operation of Figures 8A-8D, it can be seen that the content addressing memory device 800 of the eighth embodiment can more accurately match data segments and reference serial data, thereby improving the credibility of seed and voting strategies.

[0182] In one embodiment of the present invention, when the application Figures 8A to 8DWhen performing data search and comparison, if the data search and comparison fails (i.e., the counting result of the inductive counting circuit does not exceed a threshold), then one of the following methods can be used: Figures 8A to 8D Another method is used to perform data search and comparison to obtain the best reading mapping result. This is also within the spirit and scope of the present invention.

[0183] Please refer to Figure 9 This illustrates how wildcard characters can be used to speed up data search and comparison. For example... Figure 9 As shown, when the stored data is AAA, AAC, AAG, or AAT, searching using "AA*" (where * represents a wildcard character) will match all of them. That is, a single search operation can search multiple data entries simultaneously. In contrast, without using wildcard characters, searching for AAA, AAC, AAG, or AAT would require more rounds (4 rounds) to obtain results. Thus, through... Figure 9 This can reduce the number of rounds when reading the mapping and speed up data search and comparison.

[0184] In one embodiment, when a data segment is read and mapped to a reference string of data, if Figures 8A to 8D If all data search and comparison results fail, the data will be searched through a graphics processing unit (GPU) or a central processing unit (CPU), the details of which will not be elaborated here.

[0185] Figure 10 A method of operating a content-addressable memory device according to a ninth embodiment of the present invention includes: in step 1002, programming a plurality of content-addressable memory cells, each of the content-addressable memory cells including a plurality of flash memory cells, a stored data of each of the content-addressable memory cells being determined by a combination of a plurality of threshold voltages of the flash memory cells of the content-addressable memory cells, the content-addressable memory cells being coupled to a plurality of matching lines; in step 1004, applying a plurality of first search voltages and a plurality of second search voltages to the content-addressable memory cells; in step 1006, sensing a plurality of matching currents on the matching lines to generate a plurality of sensing results; and in step 1008, generating a matching address based on the sensing results, the matching address indicating an individual address of the content-addressable memory cells for which a search result is a match.

[0186] The details of steps 1002-1008 are as described in the above embodiments and will not be repeated here. Figure 10 This can be applied to the fifth embodiment.

[0187] Figure 11A method of operating a content-addressable memory device according to a tenth embodiment of the present invention includes: in step 1102, programming a plurality of content-addressable memory cells, each of the content-addressable memory cells including a plurality of serial flash memory cells, each of the content-addressable memory cells storing individual data relating to a portion of a reference serial data, the content-addressable memory cells being coupled to a plurality of matching lines; in step 1104, applying a plurality of search voltages to the content-addressable memory cells, and in a plurality of comparison rounds, a data segment being used to determine the search voltages applied to the content-addressable memory cells; in step 1106, in the plurality of comparison rounds, sensing and counting a plurality of matching currents on the matching lines to generate a plurality of counting results; and in step 1108, determining, based on the counting results, whether the data segment matches the reference serial data.

[0188] The details of steps 1102-1108 are as described in the above embodiments and will not be repeated here. Figure 11 This can be applied to the eighth embodiment.

[0189] In the above embodiments of the present invention, the content-addressable memory unit can be implemented as: a multi-level CAM cell (MLC) capable of storing two bits, a triple-level CAM cell (TLC) capable of storing three bits, a quad-level CAM cell (QLC) capable of storing four bits, a penta-level CAM cell (PLC) capable of storing five bits, etc., all of which are within the spirit and scope of the present invention.

[0190] In the above embodiments of the present invention, the CAM memory device may be a two-dimensional (2D) flash memory architecture or a three-dimensional (3D) flash memory architecture, both of which are within the spirit and scope of the present invention.

[0191] In this embodiment of the invention, a 3D-NAND architecture is used when performing data search and matching, which can save memory space, improve in-memory searching (IMS) density, and improve matching speed and accuracy.

[0192] The embodiments of the present invention are applicable to long character search designs. Therefore, when using the CAM unit and CAM memory device of the embodiments of the present invention to perform big data search, the search density in the memory can be improved.

[0193] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention shall be determined by the appended claims.

Claims

1. A content-addressable memory cell, characterized in that, include: A first flash memory cell, wherein a first terminal of the first flash memory cell is used to receive a first search voltage; A second flash memory cell, a first terminal of the second flash memory cell is used to receive a second search voltage, and a second terminal of the first flash memory cell is electrically connected to a second terminal of the second flash memory cell; The first flash memory cell and the second flash memory cell are connected in series. The stored data of the content-addressable memory cell is determined by a combination of multiple threshold voltages of the first flash memory cell and the second flash memory cell. The first search voltage and the second search voltage are determined by the search data, and the search data is compared with the stored data. When the stored data is a first predetermined stored data, the first threshold voltage of the first flash memory cell is a minimum threshold voltage value, and the second threshold voltage of the second flash memory cell is a maximum threshold voltage value. When the stored data is a second predetermined stored data, the first threshold voltage is the maximum threshold voltage value, and the second threshold voltage is the minimum threshold voltage value; When the stored data is a third predetermined stored data, both the first threshold voltage and the second threshold voltage are the minimum threshold voltage value; And when the stored data is a fourth predetermined stored data, the first threshold voltage and the second threshold voltage are equal to or greater than the maximum threshold voltage value.

2. A content-addressable memory device, characterized in that, include: A plurality of first content-addressable memory cell arrays, the plurality of first content-addressable memory cell arrays including a plurality of first content-addressable memory cells, each of the first content-addressable memory cell including a plurality of flash memory cells, and a stored data in each of the first content-addressable memory cell arrays being determined by a combination of a plurality of threshold voltages of the flash memory cells of the first content-addressable memory cell arrays. A first word line driver is provided to provide a plurality of first search voltages and a plurality of second search voltages to these first content-addressed memory cells; Multiple first matching lines are coupled to these first content-addressable memory cells; Multiple first sensing amplifiers are coupled to these first matching lines; as well as A decoder is coupled to these first inductive amplifiers; Wherein, when the first search voltages and the second search voltages are applied to the first content-addressed memory cells, the first sensing amplifiers sense multiple first matching currents on the first matching lines to generate multiple first sensing results; and Based on these first sensing results, the decoder generates a first matching address, which indicates the individual address of the first content-addressed memory cell for which a first search result is a match. The first search voltage among the plurality of first search voltages and the first search voltage among the plurality of second search voltages are determined based on search data, and the search data is compared with the stored data. When the stored data is a first predetermined stored data, a first threshold voltage of a first flash memory cell of these flash memory cells is a minimum threshold voltage value, and a second threshold voltage of a second flash memory cell of these flash memory cells is a maximum threshold voltage value; when the stored data is a second predetermined stored data, the first threshold voltage is the maximum threshold voltage value, and the second threshold voltage is the minimum threshold voltage value; when the stored data is a third predetermined stored data, both the first threshold voltage and the second threshold voltage are the minimum threshold voltage value; and when the stored data is a fourth predetermined stored data, the first threshold voltage and the second threshold voltage are equal to or greater than the maximum threshold voltage value.

3. The content-addressable memory device according to claim 2, characterized in that, In the first content-addressable memory unit, when the search data is a first predetermined search data, the first search voltage is a minimum search voltage value and the second search voltage is a maximum search voltage value; when the search data is a second predetermined search data, the first search voltage is the maximum search voltage value and the second search voltage is the minimum search voltage value. Furthermore, when the search data is a third predetermined search data, both the first search voltage and the second search voltage are the maximum search voltage value; wherein, when the first matching current appears on the first matching line, the first search result is a match.

4. The content-addressable memory device according to claim 2, characterized in that, The content-addressable memory device also includes: A plurality of second content-addressable memory cell arrays, the plurality of second content-addressable memory cell arrays including a plurality of second content-addressable memory cells, each of the plurality of second content-addressable memory cell arrays including a plurality of flash memory cells, wherein a stored data in each of the plurality of second content-addressable memory cell arrays is determined by a combination of a plurality of threshold voltages of the flash memory cells of the plurality of second content-addressable memory cell arrays. A second word line driver is provided to provide multiple third search voltages and multiple fourth search voltages to these second content-addressed memory cells; Multiple second matching lines are coupled to these second content-addressable memory cells; Multiple second sensing amplifiers are coupled to these second matching lines; and When the third search voltage and the fourth search voltage are applied to the second content-addressed memory cells, the second sensing amplifiers sense multiple second matching currents on the second matching lines to generate multiple second sensing results. The decoder generates a first matching address and a second matching address based on the results of multiple logical operations on the first sensing results and the second sensing results. The second matching address indicates the individual address of the second content-addressed memory cell that is matched by a second search result.

5. The content-addressable memory device according to claim 4, characterized in that, Also includes: Multiple logic gates are coupled between the first sense amplifiers and the decoder, or between the second sense amplifiers and the decoder.

6. A method for operating a content-addressable memory device, characterized in that, include: Programming multiple content-addressable memory cells, each of which includes multiple flash memory cells, a stored data in each of the content-addressable memory cells is determined by a combination of multiple threshold voltages of the flash memory cells of the content-addressable memory cells, and the content-addressable memory cells are coupled to multiple matching lines. Multiple first search voltages and multiple second search voltages are applied to these content-addressable memory cells; Multiple matching currents are sensed on these matching lines to produce multiple sensing results; as well as Based on these sensing results, a matching address is generated, which indicates the individual address of the memory cell where the search result matches the content addressing memory. The first search voltage among the plurality of first search voltages and the first search voltage among the plurality of second search voltages are determined based on search data, and the search data is compared with the stored data. When the stored data is a first predetermined stored data, a first threshold voltage of a first flash memory cell of these flash memory cells is a minimum threshold voltage value, and a second threshold voltage of a second flash memory cell of these flash memory cells is a maximum threshold voltage value; when the stored data is a second predetermined stored data, the first threshold voltage is the maximum threshold voltage value, and the second threshold voltage is the minimum threshold voltage value; when the stored data is a third predetermined stored data, both the first threshold voltage and the second threshold voltage are the minimum threshold voltage value; and when the stored data is a fourth predetermined stored data, the first threshold voltage and the second threshold voltage are equal to or greater than the maximum threshold voltage value.

7. The operating method according to claim 6, characterized in that, In this content-addressable memory unit, when the search data is a first predetermined search data, the first search voltage is a minimum search voltage value, and the second search voltage is a maximum search voltage value; when the search data is a second predetermined search data, the first search voltage is the maximum search voltage value, and the second search voltage is the minimum search voltage value; when the search data is a third predetermined search data, both the first search voltage and the second search voltage are the maximum search voltage value; wherein, when the matching current appears on the matching line, the search result is a match.

8. A content-addressable memory device, characterized in that, include: Multiple content-addressable memory cell arrays, each of these content-addressable memory cell arrays comprising multiple content-addressable memory cells, each of these content-addressable memory cells comprising multiple serial flash memory cells, and each of these content-addressable memory cell arrays storing individual data relating to a portion of a reference string of data; A word line decoder and driver is used to provide multiple search voltages to these content-addressed memory cells. In multiple comparison rounds, the word line decoder and driver determines the search voltages applied to these content-addressed memory cells based on a data segment (read). Multiple matching lines are coupled to these content-addressable memory cells; Multiple inductive counting circuits are coupled to these matching lines; as well as A decoder is coupled to these inductive counting circuits; In these comparison rounds, when these search voltages are applied to these content-addressed memory cells, these inductive counting circuits sense and count multiple matching currents on these matching lines to generate multiple counting results. The decoder determines whether the data segment matches the reference serial data based on these counting results from the inductive counting circuits.

9. The content-addressable memory device according to claim 8, characterized in that, When the highest count among these counts is higher than a threshold, the decoder determines that the data segment matches the reference string data.

10. The content-addressable memory device according to claim 8, characterized in that, In each comparison round, the word line decoder and driver selects a seed data from the data segment, and the word line decoder and driver determines the search voltages to be applied to these content-addressed memory cells based on the seed data.

11. The content-addressable memory device according to claim 10, characterized in that, In these comparison rounds, when an effective length of the seed data is less than the number of content-addressed memory cells in the content-addressed memory cell string, the word line decoder and driver applies predetermined search data to the content-addressed memory cell string or stores predetermined storage data to at least one content-addressed memory cell in the content-addressed memory cell string.

12. The content-addressable memory device according to claim 8, characterized in that, Based on the reference string data, it is determined whether to store invalid data in these content-addressed memory cell strings.

13. A method for data search and comparison, characterized in that, The method includes: Program multiple content-addressable memory cells, each of which includes multiple serial flash memory cells, and each of these content-addressable memory cells stores individual data relating to a portion of a reference string of data, and these content-addressable memory cells are coupled to multiple matching lines; Multiple search voltages are applied to these content-addressed memory cells, and in multiple comparison rounds, a data segment (read) is used to determine these search voltages applied to these content-addressed memory cells; In these comparison rounds, multiple matching currents on these matching lines are sensed and counted to produce multiple counting results; and Based on these counting results, it is determined whether the data segment matches the reference string data.

14. The method according to claim 13, characterized in that, When the highest count among these counts is higher than a threshold, the data segment is determined to match the reference string data.

15. The method according to claim 13, characterized in that, In each comparison round, a seed data is selected from the data segment to determine the search voltages applied to these content-addressed memory cells.

16. The method according to claim 15, characterized in that, In these comparison rounds, when an effective length of the seed data is less than the number of content-addressed memory cells, a predetermined search data is applied to these content-addressed memory cells or a predetermined storage data is stored in at least one content-addressed memory cell in the string of content-addressed memory cells.

17. The method according to claim 13, characterized in that, This reference string data is used to determine whether to store invalid data in these content-addressed memory units.

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