Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same, the method comprising: providing a semiconductor substrate having a device structure; forming a dielectric layer on a surface of the semiconductor substrate; forming a contact hole of the device structure in the dielectric layer; performing ion implantation on the semiconductor substrate, wherein a part of the implanted ions enters the device structure through the contact hole to form a doped region; wherein the type of the doped ions of the doped region is opposite to the device type of the device structure. The present application can improve the quality of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for forming the same. Background Technology

[0002] With the rapid development of the semiconductor industry, power integrated circuits (PICs) are increasingly used in various fields, such as motor control, flat panel display driver control, and computer peripheral driver control.

[0003] Among various power devices, the Lateral Double Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (LDMOS) high-voltage device is an example. It has the characteristics of high operating voltage, simple process, and easy process compatibility with low-voltage Complementary Metal-Oxide Semiconductor (CMOS) circuits, and therefore has received widespread attention.

[0004] However, in the existing technology, the breakdown voltage (BV) and hot carrier effect (HCI) of semiconductor devices, including LDMOS, need to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, which can improve the quality of the semiconductor device.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor device, comprising: providing a semiconductor substrate having a device structure; forming a dielectric layer on the surface of the semiconductor substrate; forming contact holes of the device structure in the dielectric layer; and performing ion implantation on the semiconductor substrate, wherein a portion of the implanted ions enter the device structure through the contact holes to form a doped region; wherein the type of dopant ions in the doped region is opposite to the device type of the device structure.

[0007] Optionally, the device type of the device structure is N-type; ion implantation of the semiconductor substrate includes: P-type ion implantation of the semiconductor substrate.

[0008] Optionally, ion implantation is performed on the semiconductor substrate, including ion implantation with an ion implantation dose less than or equal to a preset dose.

[0009] Optionally, ion implantation is performed on the semiconductor substrate, including: ion implantation with an ion implantation energy less than or equal to a preset energy; and / or ion implantation with an ion implantation depth less than or equal to a preset depth.

[0010] Optionally, the device structure includes source / drain doped regions; the preset depth is selected from 10% to 100% of the depth of the source / drain doped regions.

[0011] Optionally, ion implantation is performed on the semiconductor substrate, including ion implantation at a tilted implantation angle greater than or equal to a preset angle.

[0012] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device, comprising: a semiconductor substrate; a device structure located within the semiconductor substrate; a dielectric layer located on the surface of the semiconductor substrate; a contact hole of the device structure located within the dielectric layer; and a doped region located within the semiconductor substrate; wherein the doped region is formed by ion implantation into the semiconductor substrate, with a portion of the implanted ions entering the device structure via the contact hole; and wherein the type of dopant ions in the doped region is opposite to the device type of the device structure.

[0013] Optionally, at least a portion of the contact holes have a diameter greater than or equal to a preset size; wherein the preset size is determined based on a preset multiple of the characteristic size of the contact holes in the device structure.

[0014] Optionally, the device structure includes: a gate structure located on the surface of the semiconductor substrate; a silicide barrier layer (SAB) partially covering the gate structure; wherein the bottom of some or all contact holes with a diameter greater than or equal to a preset size exposes the SAB.

[0015] Optionally, the semiconductor device is a laterally diffused metal-oxide-semiconductor (LDMOS) device, and the device structure includes a drift doped region; wherein the doped region formed by some or all of the contact holes with a diameter greater than or equal to a preset size is located within the drift doped region.

[0016] Optionally, the device structure includes: source / drain doped regions located within the device structure; wherein the bottom of a portion of the contact hole exposes the top surface of the source / drain doped regions.

[0017] Optionally, the device structure includes: a gate structure located on the surface of the semiconductor substrate; wherein a portion of the bottom of the contact hole exposes the top surface of the gate structure.

[0018] Optionally, the semiconductor device is a laterally diffused metal-oxide-semiconductor (LDMOS) device, wherein the application voltage of the LDMOS device is greater than or equal to a preset voltage.

[0019] Optionally, the semiconductor device is an N-type LDMOS device.

[0020] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0021] In this embodiment of the invention, contact holes for the device structure are formed in a dielectric layer formed on the surface of a semiconductor substrate. Ion implantation is then performed on the semiconductor substrate, wherein a portion of the implanted ions enter the device structure through the contact holes to form a doped region. Furthermore, the type of dopant ions in the doped region is opposite to the device type of the device structure. By employing this method, a doped region with a dopant type opposite to that of the device structure can be formed in the semiconductor substrate. This helps to alter electrical properties, increase the depletion region, and reduce the electric field strength, thereby improving the device's base voltage (BV) and high-performance liquid chromatography (HCI) and enhancing the quality of the semiconductor device.

[0022] Furthermore, P-type ion implantation is performed on the semiconductor substrate to achieve inversion implantation of the N-type device. This helps to increase the depletion region and reduce the electric field strength, thereby improving the BV and HCI of the N-type device. It should be noted that N-type devices are more sensitive to BV and HCI than P-type devices. Therefore, in this embodiment of the invention, no additional mask layer is set to protect the P-type device. Instead, P-type ion implantation is performed directly, thereby effectively controlling production costs and efficiency while improving the more sensitive N-type device.

[0023] Furthermore, using an ion implantation dose less than or equal to a preset dose helps to reduce the impact on second-type devices (e.g., P-type devices) while improving the performance of first-type devices (e.g., N-type devices).

[0024] Furthermore, using an ion implantation energy less than or equal to a preset energy for ion implantation, and / or using an ion implantation depth less than or equal to a preset depth for ion implantation, helps to control the ion implantation area to be the surface adjacent to the semiconductor substrate, thereby achieving surface inversion implantation, increasing the surface depletion region, reducing the surface electric field intensity, and better improving the performance of the semiconductor device.

[0025] Furthermore, considering that the role of large-size contact holes in semiconductor devices is often to balance the electric field, such as forming a balance on the SAB in high-voltage LDMOS devices, by selecting an appropriate tilt injection angle, such as a tilt injection angle greater than or equal to a preset angle, it is possible to inject into the conventional logic region that is difficult to inject into and the large-size contact hole region that is easier to inject into. This helps to better improve the electric field characteristics of such semiconductor devices, such as improving the BV and HCI of high-voltage LDMOS devices.

[0026] Furthermore, considering that the role of large-size contact holes in semiconductor devices is often to balance the electric field, such as in high-voltage LDMOS devices where they can be formed on the SAB to balance the electric field, it is advisable to set large-size contact holes partially or entirely in the gate structure and SAB region. This allows the bottom of some or all contact holes with a diameter greater than or equal to a preset size to be exposed to the SAB, which helps to better improve the electric field characteristics of such semiconductor devices, such as improving the BV and HCI of high-voltage LDMOS devices.

[0027] Furthermore, by placing large-sized contact holes partially or entirely within the drift doping region of the laterally diffused metal-oxide-semiconductor (LDMOS) device, inversion injection can be performed on the surface of the LDMOS device, which helps to increase the depletion region, reduce the electric field strength, and thus improve the device's BV and HCI.

[0028] Furthermore, the semiconductor device is an LDMOS device, wherein the application voltage of the LDMOS device is greater than or equal to a preset voltage. Since high-voltage LDMOS devices are more sensitive to BV and HCI, in this embodiment of the invention, ion implantation is performed on the LDMOS device, which helps to improve the effectiveness of the invention.

[0029] Furthermore, the semiconductor device is an N-type LDMOS device. Since N-type LDMOS devices are more sensitive to BV and HCl, ion implantation is performed on the N-type LDMOS device in this embodiment of the invention, which helps to further improve the effectiveness of the invention. Attached Figure Description

[0030] Figure 1 This is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0031] Figure 2 This is a cross-sectional structural schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0032] Figure 3 This is a cross-sectional structural diagram of another semiconductor device in an embodiment of the present invention.

[0033] Figure label:

[0034] Semiconductor substrate 100; bulk doped region 101; drift doped region 102; isolation structure 111; source / drain doped region 112; source / drain doped region 113; source / drain doped region 114; gate structure 121; SAB 122; dielectric layer 123; contact hole 131; doped region 141; contact hole 232; contact hole 233. Detailed Implementation

[0035] Among various power devices, LDMOS high-voltage devices, for example, have attracted widespread attention due to their high operating voltage, simple manufacturing process, and ease of compatibility with low-voltage CMOS circuits. However, in existing technologies, the base voltage (BV) and high-performance inductance (HCI) of semiconductor devices, including LDMOS, need to be improved.

[0036] The inventors of this invention discovered through research that in the prior art, device structures often have problems such as a small depletion region depth and a large electric field strength, resulting in serious BV and HCI problems in the device structure.

[0037] In this embodiment of the invention, contact holes for the device structure are formed in a dielectric layer formed on the surface of a semiconductor substrate. Ion implantation is then performed on the semiconductor substrate, wherein a portion of the implanted ions enter the device structure through the contact holes to form a doped region. Furthermore, the type of dopant ions in the doped region is opposite to the device type of the device structure. By employing this method, a doped region with a dopant type opposite to that of the device structure can be formed in the semiconductor substrate. This helps to alter electrical properties, increase the depletion region, and reduce the electric field strength, thereby improving the device's base voltage (BV) and high-performance liquid chromatography (HCI) and enhancing the quality of the semiconductor device.

[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Reference Figure 1 , Figure 1 This is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention. The method for forming the semiconductor device may include steps S11 to S14:

[0040] Step S11: Provide a semiconductor substrate having a device structure;

[0041] Step S12: Form a dielectric layer on the surface of the semiconductor substrate;

[0042] Step S13: Form contact holes for the device structure in the dielectric layer;

[0043] Step S14: Ion implantation is performed on the semiconductor substrate, wherein a portion of the implanted ions enter the device structure through the contact hole to form a doped region, wherein the type of dopant ions in the doped region is opposite to the device type of the device structure.

[0044] The following combination Figure 2 The steps described above will be explained. Figure 2 This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention.

[0045] Reference Figure 2 A semiconductor substrate 100 is provided, the semiconductor substrate 100 having a device structure.

[0046] The semiconductor substrate 100 may be a silicon substrate, or the material of the semiconductor substrate 100 may include germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The semiconductor substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or a substrate with an epitaxy layer (Epi layer) grown on it. Specifically, deep well implantation can be achieved by ion implantation into the semiconductor substrate 100.

[0047] It should be noted that the semiconductor substrate 100 may also include structures located on the surface of the semiconductor substrate 100, such as gate structures, metal interconnect structures, and filter structures, and is not limited to the portion within the surface of the semiconductor substrate 100.

[0048] In a specific implementation, the device structure may include a body-implant region 101 and a drift-implant region 102 located within the semiconductor substrate 100.

[0049] As a non-limiting example, if the device type of the device structure is N-type, then the doping type of the body doping region 101 can be P-type, that is, forming a P-body region, and the doping type of the drift doping region 102 can be N-type, that is, forming an N-Drift region.

[0050] Non-limiting, the bulk doped region 101 may include source / drain doped regions 112 and 113, wherein adjacent source / drain doped regions 112 and 113 may be isolated by an isolation structure 111.

[0051] The isolation structure 111 can be obtained, for example, by shallow trench isolation (STI) or other suitable processes, and this is not limited in the embodiments of the present invention.

[0052] Specifically, the doping type of the source / drain doped region 112 can be of the first type, and the doping type of the source / drain doped region 113 can be of the second type, wherein the first type can be different from the second type. Taking the body doped region 101 as a P-body region as an example, the source / drain doped region 112 can be P-type doped, and the source / drain doped region 113 can be N-type doped.

[0053] Furthermore, the doping concentration of the source / drain doped region 112 can be greater than the doping concentration of the bulk doped region 101, and the doping concentration of the source / drain doped region 113 can be greater than the doping concentration of the drift doped region 102.

[0054] Non-limiting, the drift doped region 102 may include source / drain doped regions 114, wherein adjacent source / drain doped regions 114 may be isolated by an isolation structure 111.

[0055] Specifically, the doping type of the source / drain doping region 114 can be the third type. Taking the drift doping region 102 as an N-Drift region as an example, the source / drain doping region 114 can be N-type doped, and the doping concentration can be greater than the doping concentration of the drift doping region 102.

[0056] In a specific implementation, the device structure may also include a gate structure 121 located on the surface of the semiconductor substrate 100, and may also include a silicide block (SAB) 122.

[0057] SAB 122 may partially cover the gate structure 121, for example, it may be formed using a self-aligned process, or it may be formed using other suitable methods, such as a photolithography-etching process based on a mask layer. This embodiment of the invention does not limit this.

[0058] In a specific implementation, the device structure may also include a contact hole (CT) 131.

[0059] In an embodiment of the present invention, the step of forming the contact hole 131 may include: forming a dielectric layer 123 on the surface of the semiconductor substrate 100, and forming the contact hole 131 of the device structure in the dielectric layer 123.

[0060] More specifically, a patterned mask layer (not shown) can be formed on the surface of the dielectric layer 123, and the patterned mask layer can be used as a mask for etching to form contact holes 131.

[0061] It should be noted that the process of forming the contact hole 131 is a critical process in semiconductor manufacturing. It is an essential step to realize the electrical performance of semiconductor devices, and the feature size (Contact Critical Dimension, CTCD) of the contact hole 131 is often determined during the design stage.

[0062] In a specific implementation, ion implantation is performed on the semiconductor substrate 100, wherein a portion of the implanted ions enter the device structure through the contact hole 131 to form a doped region 141, wherein the type of doped ions in the doped region 141 is opposite to the device type of the device structure.

[0063] In this embodiment of the invention, contact holes 131 for the device structure are formed in a dielectric layer 123 formed on the surface of a semiconductor substrate 100. Ion implantation is performed on the semiconductor substrate 100, wherein a portion of the implanted ions enter the device structure through the contact holes 131 to form a doped region 141. Furthermore, the type of dopant ions in the doped region 141 is opposite to the device type of the device structure. By employing this method, a doped region 141 with a device type opposite to that of the device structure can be formed in the semiconductor substrate 100. This helps to alter electrical properties, increase the depletion region, and reduce the electric field strength, thereby improving the device's base voltage (BV) and high-performance liquid chromatography (HCI) and enhancing the quality of the semiconductor device.

[0064] Furthermore, the device type of the device structure can be N-type; ion implantation of the semiconductor substrate 100 includes: P-type ion implantation of the semiconductor substrate 100.

[0065] Without limitation, the P-type ion may be selected from B and BF2.

[0066] In this embodiment of the invention, P-type ion implantation is performed on the semiconductor substrate 100 to achieve inversion implantation of the N-type device. This helps to increase the depletion region and reduce the electric field strength, thereby improving the BV and HCI of the N-type device. It should be noted that N-type devices are more sensitive to BV and HCI than P-type devices. Therefore, in this embodiment of the invention, no additional mask layer is set to protect the P-type device. Instead, P-type ion implantation is performed directly, thereby effectively controlling production costs and efficiency while improving the more sensitive N-type device.

[0067] Furthermore, the step of ion implantation on the semiconductor substrate 100 may include: performing ion implantation with an ion implantation dose less than or equal to a preset dose.

[0068] As a non-limiting example, a preset dose of 1e can be set. 15 / cm 2That is, using less than or equal to 1e 15 / cm 2 The ion implantation dose. In one specific embodiment of the present invention, a dose less than or equal to 1e can be used. 13 / cm 2 The ion implantation dose.

[0069] Specifically, the semiconductor substrate 100 can have various different types of device structures, such as N-type devices and P-type devices at the same time. In the embodiments of the present invention, ion implantation is performed using an ion implantation dose less than or equal to a preset dose, which helps to reduce the impact on the second type of device (e.g., P-type device) while improving the performance of the first type of device (e.g., N-type device).

[0070] Furthermore, the step of ion implantation on the semiconductor substrate 100 may include: performing ion implantation with an ion implantation energy less than or equal to a preset energy; and / or performing ion implantation with an ion implantation depth less than or equal to a preset depth.

[0071] As a non-limiting example, the preset energy can be selected from 10 keV to 1000 keV. Taking a preset energy of 100 keV as an example, an ion implantation energy of less than or equal to 100 keV can be used.

[0072] In one specific implementation of the present invention, a preset energy can be set from 50 keV to 200 keV, for example, 100 keV.

[0073] As a non-limiting example, the preset depth can be determined based on the source and drain doping regions in the device structure.

[0074] The source / drain doped regions can be selected from: source / drain doped region 112, source / drain doped region 113, and source / drain doped region 114. Specifically, source / drain doped regions 112, 113, and 114 can be formed using the same source / drain doping process, and the ion implantation depth has a deviation within a preset error range.

[0075] Furthermore, the device structure includes source / drain doped regions; the preset depth can be selected from 10% to 100% of the depth of the source / drain doped regions.

[0076] Taking a preset depth of 20% of the source / drain doped region depth as an example, an ion implantation depth of less than or equal to 20% of the source / drain doped region depth can be used.

[0077] In this embodiment of the invention, ion implantation is performed using an ion implantation energy less than or equal to a preset energy, and / or ion implantation is performed using an ion implantation depth less than or equal to a preset depth. This helps to control the ion implantation area to be adjacent to the surface of the semiconductor substrate 100, thereby achieving surface inversion implantation, increasing the surface depletion region, reducing the surface electric field strength, and better improving the performance of the semiconductor device.

[0078] Figure 3 This is a schematic cross-sectional view of another semiconductor device according to an embodiment of the present invention. The following describes... Figure 3 and Figure 2 The different contents will be explained.

[0079] Reference Figure 3 The contact hole 131 of the device structure is located on the surface of the drift doped region 102, and the doped region 141 formed after entering the device structure through the contact hole 131 is located within the drift doped region 102.

[0080] It is understandable that during the formation of contact hole 131, contact holes can also be formed at other appropriate locations according to the design requirements of the semiconductor device. For example, contact hole 232 can be formed in the source / drain doped region, and contact hole 233 can also be formed in the gate structure 121.

[0081] As mentioned earlier, the characteristic dimensions of each contact hole are often determined during the design phase, and different contact holes can have their own characteristic dimensions, such as being the same or different.

[0082] Furthermore, the step of ion implantation on the semiconductor substrate 100 may include: performing ion implantation at a tilted implantation angle greater than or equal to a preset angle.

[0083] As a non-limiting example, if a preset angle of 10° or greater can be set, then an inclined injection angle of 10° or greater can be used.

[0084] In this embodiment of the invention, considering that the role of large-size contact holes in semiconductor devices is often to balance the electric field, for example, in high-voltage LDMOS devices, they can be formed on the SAB to balance the electric field. Therefore, by selecting an appropriate tilt injection angle, such as a tilt injection angle greater than or equal to a preset angle, it is possible to inject into the conventional logic region that is difficult to inject into and the large-size contact hole region that is easier to inject into. This helps to better improve the electric field characteristics of such semiconductor devices, such as improving the BV and HCI of high-voltage LDMOS devices.

[0085] In this embodiment of the invention, a semiconductor device is also disclosed, with reference to... Figure 3The device may include: a semiconductor substrate 100; a device structure located in the semiconductor substrate 100; a dielectric layer 123 located on the surface of the semiconductor substrate 100; a contact hole 131 of the device structure located in the dielectric layer 123; and a doped region 141 located within the semiconductor substrate 100. The doped region 141 is formed by ion implantation into the semiconductor substrate 100, with a portion of the implanted ions entering the device structure through the contact hole 131. The type of doped ions in the doped region 141 is opposite to the device type of the device structure.

[0086] In this embodiment of the invention, contact holes 131 for the device structure are formed in a dielectric layer 123 formed on the surface of a semiconductor substrate 100. Ion implantation is performed on the semiconductor substrate 100, wherein a portion of the implanted ions enter the device structure through the contact holes 131 to form a doped region 141. Furthermore, the type of dopant ions in the doped region 141 is opposite to the device type of the device structure. By employing this method, a doped region 141 with a device type opposite to that of the device structure can be formed in the semiconductor substrate 100. This helps to alter electrical properties, increase the depletion region, and reduce the electric field strength, thereby improving the device's base voltage (BV) and high-performance liquid chromatography (HCI) and enhancing the quality of the semiconductor device.

[0087] It should be pointed out that, such as Figure 3 The contact hole shown may include not only contact hole 131, but also contact hole 232 and contact hole 233.

[0088] Furthermore, at least a portion of the contact holes have a diameter greater than or equal to a preset size; wherein the preset size is determined based on a preset multiple of the characteristic size of the contact holes in the device structure.

[0089] In a non-limiting specific embodiment, the semiconductor device is an LDMOS device, and the process is a bipolar-CMOS-DMOS (BCD) process.

[0090] Specifically, based on the 90nm process platform, the minimum feature size (CFP width) of the contact hole in the entire semiconductor device can be approximately 0.12µm, and the feature size (CT CD) of the contact hole 131 can be set to be greater than or equal to 0.4µm.

[0091] Based on the 55nm process platform, the minimum feature size (CFPwidth) of the contact hole in the entire semiconductor device can be approximately 0.054µm, and the feature size (CTCD) of the contact hole 131 can be set to be greater than or equal to 0.4µm.

[0092] Specifically, the implementation target of this embodiment of the invention may be a contact hole with a diameter greater than or equal to a preset multiple (e.g., contact hole 131), which needs to form a doped region 141 based on the contact hole; for contact holes with a diameter less than a preset multiple (e.g., contact hole 232, contact hole 233), the ion dose implanted through the contact hole is not limited, and it is not limited whether it is sufficient to form a doped region.

[0093] Furthermore, the preset multiple can be set to be greater than or equal to 3. Specifically, this can be considered as a multiple between the CT CD of the region to be doped 141 and the CT CD of the gate structure 121 region being greater than or equal to 3.

[0094] Furthermore, the device structure may include: a gate structure 121 located on the surface of the semiconductor substrate 100; and an SAB 122 partially covering the gate structure 121; wherein the bottom of a contact hole 131 with a diameter greater than or equal to a preset size is exposed by the SAB 122.

[0095] In this embodiment of the invention, considering that the role of large-size contact holes in semiconductor devices is often to balance the electric field, for example, in high-voltage LDMOS devices, they can be formed on the SAB to balance the electric field, so that large-size contact holes are partially or entirely located in the gate structure 121 and SAB 122 region, so that the bottom of some or all of the contact holes with a diameter greater than or equal to the preset size is exposed to the SAB 122, which helps to better improve the electric field characteristics of such semiconductor devices, such as improving the BV and HCI of high-voltage LDMOS devices.

[0096] Furthermore, the semiconductor device may be a laterally diffused metal-oxide-semiconductor (LDMOS) device, and the device structure may include a drift doped region 102; wherein, a doped region 141 formed via some or all of contact holes with a diameter greater than or equal to a preset size is located within the drift doped region 102.

[0097] In this embodiment of the invention, by setting a large-size contact hole partially or entirely within the drift doping region of the laterally diffused metal-oxide-semiconductor (LDMOS) device, inversion injection can be performed on the surface of the LDMOS device, which helps to increase the depletion region, reduce the electric field strength, and thus improve the device's BV and HCI.

[0098] Furthermore, the device structure may include: source / drain doped regions located within the device structure; wherein the bottom of a portion of the contact hole exposes the top surface of the source / drain doped regions.

[0099] Wherein, the source / drain doped region can be Figure 3 The source / drain doped region 112 shown can also be Figure 3 The source / drain doped region 113 shown can also be other suitable source / drain doped regions, such as source / drain doped region 114.

[0100] It should be noted that for contact holes located in the source / drain doped regions, if a smaller CT CD is used, the ion dose injected through the contact hole is not limited, and it is not limited whether it is sufficient to form a doped region.

[0101] Furthermore, the semiconductor device is a laterally diffused metal-oxide-semiconductor (LDMOS) device, wherein the application voltage of the LDMOS device is greater than or equal to a preset voltage.

[0102] Specifically, by setting the application voltage of the LDMOS device to be greater than or equal to a preset voltage, the semiconductor device can be made into a high-voltage LDMOS device.

[0103] The preset voltage can be set to 12V without limitation.

[0104] In this embodiment of the invention, the semiconductor device can be an LDMOS device, wherein the application voltage of the LDMOS device is greater than or equal to a preset voltage. Since high-voltage LDMOS devices are more sensitive to BV and HCI, in this embodiment of the invention, ion implantation of the LDMOS device helps to improve the effectiveness of the invention.

[0105] Furthermore, the semiconductor device is an N-type LDMOS device.

[0106] In this embodiment of the invention, the semiconductor device is an N-type LDMOS device. Since N-type LDMOS devices are more sensitive to BV and HCl, ion implantation is performed on the N-type LDMOS device in this embodiment of the invention, which helps to further improve the effectiveness of the invention.

[0107] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0108] In the embodiments of this application, "multiple" refers to two or more.

[0109] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0110] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having a device structure including an N-type device and a P-type device, the N-type device including a gate structure and a silicide barrier layer, the gate structure being located on the surface of the semiconductor substrate, and the silicide barrier layer partially covering the gate structure; A dielectric layer is formed on the surface of the semiconductor substrate; Contact holes are formed in the dielectric layer, with large-sized contact holes exposing the silicide barrier layer, and other contact holes being smaller in size; Ion implantation is performed on the semiconductor substrate. By selecting an appropriate tilting implantation angle, it is possible to implant ions into contact holes that are difficult to implant into and into contact holes that are larger in size. Some of the implanted ions directly enter the N-type device through the large contact holes to form a doped region. The doped region is P-type; the doped region is located below the contact hole exposing the silicide barrier layer and adjacent to the surface of the semiconductor substrate; when ion implantation is performed on the semiconductor substrate, no additional mask layer is provided to protect the P-type device.

2. A semiconductor device, characterized in that, include: Semiconductor substrate; A device structure is located in the semiconductor substrate. The device structure includes an N-type device and a P-type device. The N-type device includes a gate structure and a silicide barrier layer. The gate structure is located on the surface of the semiconductor substrate, and the silicide barrier layer partially covers the gate structure. A dielectric layer is located on the surface of the semiconductor substrate; The contact holes are large-sized contact holes located in the dielectric layer that expose the silicide barrier layer, while the other contact holes are smaller-sized contact holes. The doped region is located within the semiconductor substrate; The doped region is formed by the following method: by selecting an appropriate tilting implantation angle, it is possible to implant into contact holes that are difficult to implant into smaller ones and easier to implant into larger ones, and some implanted ions directly enter the N-type device through the larger contact holes; The doped region is P-type; the doped region is located below the contact hole exposing the silicide barrier layer and adjacent to the surface of the semiconductor substrate; when ion implantation is performed on the semiconductor substrate, no additional mask layer is provided to protect the P-type device.

3. The semiconductor device according to claim 2, characterized in that, The N-type device includes: Source and drain doped regions.

4. The semiconductor device according to claim 2, characterized in that, The N-type device is an LDMOS device.

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